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Differential D104846

[MCA] Allow unlimited cycles in the timeline view
ClosedPublic

Authored by foad on Jun 24 2021, 4:01 AM.

Details

Reviewers
andreadb
holland11
Commits
rGbeebe5a056b8: [MCA] Allow unlimited cycles in the timeline view
Summary

Change --max-timeline-cycles=0 to mean no limit on the number of cycles.
Use this in AMDGPU tests to show all instructions in the timeline view
instead of having it arbitrarily truncated.

Diff Detail

Event Timeline

foad created this revision.Jun 24 2021, 4:01 AM
Herald added subscribers: kerbowa, gbedwell, tpr and 2 others. · View Herald TranscriptJun 24 2021, 4:01 AM
foad requested review of this revision.Jun 24 2021, 4:01 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 24 2021, 4:01 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
foad added a comment.Jun 24 2021, 4:01 AM

Maybe unlimited width could be the default if stdout is not a tty? (And if it is a tty, the default could be to query its width?)

foad mentioned this in D104730: [MCA] [AMDGPU] Adding CustomBehaviour implementation for AMDGPU..Jun 24 2021, 4:03 AM
andreadb accepted this revision.Jun 24 2021, 4:35 AM

I only have a minor request. Otherwise it LGTM.

Could you please update the description of flag timeline-max-cycles in the llvm-mca docs before committing this patch?

Thanks
-Andrea

This revision is now accepted and ready to land.Jun 24 2021, 4:35 AM
foad updated this revision to Diff 354211.Jun 24 2021, 4:40 AM

Update docs.

andreadb accepted this revision.Jun 24 2021, 4:46 AM

Thanks! LGTM

This revision was landed with ongoing or failed builds.Jun 24 2021, 4:55 AM
Closed by commit rGbeebe5a056b8: [MCA] Allow unlimited cycles in the timeline view (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGbeebe5a056b8: [MCA] Allow unlimited cycles in the timeline view.
Harbormaster completed remote builds in B110798: Diff 354211.Jun 24 2021, 5:27 AM
holland11 added a comment.Jun 24 2021, 10:09 AM

+1 Good idea!

Revision Contents

PathSize
llvm/
docs/
CommandGuide/
4 lines
test/
tools/
llvm-mca/
AMDGPU/
2 lines
49 lines
19 lines
tools/
llvm-mca/
Views/
4 lines
10 lines

Diff 354213

llvm/docs/CommandGuide/llvm-mca.rst

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
.. option:: -timeline-max-iterations=<iterations> .. option:: -timeline-max-iterations=<iterations>
Limit the number of iterations to print in the timeline view. By default, the Limit the number of iterations to print in the timeline view. By default, the
timeline view prints information for up to 10 iterations. timeline view prints information for up to 10 iterations.
.. option:: -timeline-max-cycles=<cycles> .. option:: -timeline-max-cycles=<cycles>
Limit the number of cycles in the timeline view. By default, the number of Limit the number of cycles in the timeline view, or use 0 for no limit. By
cycles is set to 80. default, the number of cycles is set to 80.
.. option:: -resource-pressure .. option:: -resource-pressure
Enable the resource pressure view. This is enabled by default. Enable the resource pressure view. This is enabled by default.
.. option:: -register-file-stats .. option:: -register-file-stats
Enable register file usage statistics. Enable register file usage statistics.
▲ Show 20 Lines • Show All 854 Lines • Show Last 20 Lines

llvm/test/tools/llvm-mca/AMDGPU/gfx10-add-sequence.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s
v_add_f32 v0, v0, v0 v_add_f32 v0, v0, v0
v_add_f32 v1, v1, v1 v_add_f32 v1, v1, v1
v_add_f32 v2, v1, v0 v_add_f32 v2, v1, v0
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3 # CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 12 # CHECK-NEXT: Total Cycles: 12
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s
v_cvt_i32_f64 v0, v[0:1] v_cvt_i32_f64 v0, v[0:1]
v_cvt_f64_i32 v[2:3], v2 v_cvt_f64_i32 v[2:3], v2
v_cvt_f32_f64 v4, v[4:5] v_cvt_f32_f64 v4, v[4:5]
v_cvt_f64_f32 v[6:7], v6 v_cvt_f64_f32 v[6:7], v6
v_cvt_u32_f64 v8, v[8:9] v_cvt_u32_f64 v8, v[8:9]
v_cvt_f64_u32 v[10:11], v10 v_cvt_f64_u32 v[10:11], v10
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
# CHECK-NEXT: - - - 1.00 - - 1.00 - v_trig_preop_f64 v[2:3], v[2:3], v0 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_trig_preop_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: - - - 1.00 - - 1.00 - v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - - 1.00 - v_cmp_class_f64_e64 vcc_lo, v[2:3], s0 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cmp_class_f64_e64 vcc_lo, v[2:3], s0
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rcp_f64_e32 v[0:1], v[0:1] # CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rsq_f64_e32 v[2:3], v[2:3] # CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rsq_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[4:5], v[4:5] # CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[4:5], v[4:5]
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789 0 # CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 # CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123
# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_cvt_i32_f64_e32 v0, v[0:1] # CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: [0,1] .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_cvt_f64_i32_e32 v[2:3], v2 # CHECK-NEXT: [0,1] .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f64_i32_e32 v[2:3], v2
# CHECK-NEXT: [0,2] . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . v_cvt_f32_f64_e32 v4, v[4:5] # CHECK-NEXT: [0,2] . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f32_f64_e32 v4, v[4:5]
# CHECK-NEXT: [0,3] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . v_cvt_f64_f32_e32 v[6:7], v6 # CHECK-NEXT: [0,3] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f64_f32_e32 v[6:7], v6
# CHECK-NEXT: [0,4] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . v_cvt_u32_f64_e32 v8, v[8:9] # CHECK-NEXT: [0,4] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_u32_f64_e32 v8, v[8:9]
# CHECK-NEXT: [0,5] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . v_cvt_f64_u32_e32 v[10:11], v10 # CHECK-NEXT: [0,5] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f64_u32_e32 v[10:11], v10
# CHECK-NEXT: [0,6] . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . v_frexp_exp_i32_f64_e32 v0, v[0:1] # CHECK-NEXT: [0,6] . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_frexp_exp_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: [0,7] . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . v_frexp_mant_f64_e32 v[2:3], v[2:3] # CHECK-NEXT: [0,7] . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_frexp_mant_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: [0,8] . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . v_fract_f64_e32 v[4:5], v[4:5] # CHECK-NEXT: [0,8] . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_fract_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: [0,9] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . v_trunc_f64_e32 v[0:1], v[0:1] # CHECK-NEXT: [0,9] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_trunc_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: [0,10] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . v_ceil_f64_e32 v[2:3], v[2:3] # CHECK-NEXT: [0,10] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_ceil_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: [0,11] . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . v_rndne_f64_e32 v[4:5], v[4:5] # CHECK-NEXT: [0,11] . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_rndne_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: [0,12] . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. v_floor_f64_e32 v[6:7], v[6:7] # CHECK-NEXT: [0,12] . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_floor_f64_e32 v[6:7], v[6:7]
# CHECK-NEXT: [0,13] . . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_fma_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: [0,14] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . v_add_f64 v[2:3], v[2:3], v[2:3]
# CHECK-NEXT: [0,15] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . v_mul_f64 v[4:5], v[4:5], v[4:5]
# CHECK-NEXT: [0,16] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . v_min_f64 v[6:7], v[6:7], v[6:7]
# CHECK-NEXT: [0,17] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . v_max_f64 v[8:9], v[8:9], v[8:9]
# CHECK-NEXT: [0,18] . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . v_div_fmas_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: [0,19] . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . v_div_fixup_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: [0,20] . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . v_ldexp_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: [0,21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . v_div_scale_f64 v[0:1], vcc_lo, v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: [0,22] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . v_trig_preop_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: [0,23] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1]
# CHECK-NEXT: [0,24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . . v_cmp_class_f64_e64 vcc_lo, v[2:3], s0
# CHECK-NEXT: [0,25] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE . v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: [0,26] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE. v_rsq_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: [0,27] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE v_sqrt_f64_e32 v[4:5], v[4:5]
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
Show All 29 Lines

llvm/test/tools/llvm-mca/AMDGPU/gfx10-trans.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s
v_log_f32 v0, v0 v_log_f32 v0, v0
v_rcp_f32 v0, v0 v_rcp_f32 v0, v0
v_rsq_f32 v1, v1 v_rsq_f32 v1, v1
v_sqrt_f32 v2, v0 v_sqrt_f32 v2, v0
v_rcp_f64 v[0:1], v[0:1] v_rcp_f64 v[0:1], v[0:1]
v_rsq_f64 v[1:2], v[1:2] v_rsq_f64 v[1:2], v[1:2]
v_sqrt_f64 v[2:3], v[0:1] v_sqrt_f64 v[2:3], v[0:1]
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
# CHECK-NEXT: - - - 1.00 - 1.00 - - v_rcp_f32_e32 v0, v0 # CHECK-NEXT: - - - 1.00 - 1.00 - - v_rcp_f32_e32 v0, v0
# CHECK-NEXT: - - - 1.00 - 1.00 - - v_rsq_f32_e32 v1, v1 # CHECK-NEXT: - - - 1.00 - 1.00 - - v_rsq_f32_e32 v1, v1
# CHECK-NEXT: - - - 1.00 - 1.00 - - v_sqrt_f32_e32 v2, v0 # CHECK-NEXT: - - - 1.00 - 1.00 - - v_sqrt_f32_e32 v2, v0
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rcp_f64_e32 v[0:1], v[0:1] # CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rsq_f64_e32 v[1:2], v[1:2] # CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rsq_f64_e32 v[1:2], v[1:2]
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[2:3], v[0:1] # CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[2:3], v[0:1]
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789 # CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 # CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789
# CHECK: [0,0] DeeeeeeeeeE . . . . . . . . . . . . v_log_f32_e32 v0, v0 # CHECK: [0,0] DeeeeeeeeeE . . . . . . . . . . . . . . . . . v_log_f32_e32 v0, v0
# CHECK-NEXT: [0,1] . . DeeeeeeeeeE . . . . . . . . . . v_rcp_f32_e32 v0, v0 # CHECK-NEXT: [0,1] . . DeeeeeeeeeE . . . . . . . . . . . . . . . v_rcp_f32_e32 v0, v0
# CHECK-NEXT: [0,2] . . .DeeeeeeeeeE . . . . . . . . . . v_rsq_f32_e32 v1, v1 # CHECK-NEXT: [0,2] . . .DeeeeeeeeeE . . . . . . . . . . . . . . . v_rsq_f32_e32 v1, v1
# CHECK-NEXT: [0,3] . . . . DeeeeeeeeeE . . . . . . . . v_sqrt_f32_e32 v2, v0 # CHECK-NEXT: [0,3] . . . . DeeeeeeeeeE . . . . . . . . . . . . . v_sqrt_f32_e32 v2, v0
# CHECK-NEXT: [0,4] . . . . .DeeeeeeeeeeeeeeeeeeeeeeeE . . . . . v_rcp_f64_e32 v[0:1], v[0:1] # CHECK-NEXT: [0,4] . . . . .DeeeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: [0,5] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE v_rsq_f64_e32 v[1:2], v[1:2] # CHECK-NEXT: [0,5] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE. . . . . . v_rsq_f64_e32 v[1:2], v[1:2]
# CHECK-NEXT: [0,6] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE v_sqrt_f64_e32 v[2:3], v[0:1]
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 v_log_f32_e32 v0, v0 # CHECK-NEXT: 0. 1 0.0 0.0 0.0 v_log_f32_e32 v0, v0
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 v_rcp_f32_e32 v0, v0 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 v_rcp_f32_e32 v0, v0
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 v_rsq_f32_e32 v1, v1 # CHECK-NEXT: 2. 1 0.0 0.0 0.0 v_rsq_f32_e32 v1, v1
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 v_sqrt_f32_e32 v2, v0 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 v_sqrt_f32_e32 v2, v0
# CHECK-NEXT: 4. 1 0.0 0.0 0.0 v_rcp_f64_e32 v[0:1], v[0:1] # CHECK-NEXT: 4. 1 0.0 0.0 0.0 v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: 5. 1 0.0 0.0 0.0 v_rsq_f64_e32 v[1:2], v[1:2] # CHECK-NEXT: 5. 1 0.0 0.0 0.0 v_rsq_f64_e32 v[1:2], v[1:2]
# CHECK-NEXT: 6. 1 0.0 0.0 0.0 v_sqrt_f64_e32 v[2:3], v[0:1] # CHECK-NEXT: 6. 1 0.0 0.0 0.0 v_sqrt_f64_e32 v[2:3], v[0:1]
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/tools/llvm-mca/Views/TimelineView.cpp

Show All 15 Lines
namespace llvm { namespace llvm {
namespace mca { namespace mca {
TimelineView::TimelineView(const MCSubtargetInfo &sti, MCInstPrinter &Printer, TimelineView::TimelineView(const MCSubtargetInfo &sti, MCInstPrinter &Printer,
llvm::ArrayRef<llvm::MCInst> S, unsigned Iterations, llvm::ArrayRef<llvm::MCInst> S, unsigned Iterations,
unsigned Cycles) unsigned Cycles)
: InstructionView(sti, Printer, S), CurrentCycle(0), : InstructionView(sti, Printer, S), CurrentCycle(0),
MaxCycle(Cycles == 0 ? 80 : Cycles), LastCycle(0), WaitTime(S.size()), MaxCycle(Cycles == 0 ? std::numeric_limits<unsigned>::max() : Cycles),
UsedBuffer(S.size()) { LastCycle(0), WaitTime(S.size()), UsedBuffer(S.size()) {
unsigned NumInstructions = getSource().size(); unsigned NumInstructions = getSource().size();
assert(Iterations && "Invalid number of iterations specified!"); assert(Iterations && "Invalid number of iterations specified!");
NumInstructions *= Iterations; NumInstructions *= Iterations;
Timeline.resize(NumInstructions); Timeline.resize(NumInstructions);
TimelineViewEntry InvalidTVEntry = {-1, 0, 0, 0, 0}; TimelineViewEntry InvalidTVEntry = {-1, 0, 0, 0, 0};
std::fill(Timeline.begin(), Timeline.end(), InvalidTVEntry); std::fill(Timeline.begin(), Timeline.end(), InvalidTVEntry);
WaitTimeEntry NullWTEntry = {0, 0, 0}; WaitTimeEntry NullWTEntry = {0, 0, 0};
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llvm/tools/llvm-mca/llvm-mca.cpp

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Linesstatic cl::opt<bool> PrintTimelineView("timeline",
cl::desc("Print the timeline view"), cl::desc("Print the timeline view"),
cl::cat(ViewOptions), cl::init(false)); cl::cat(ViewOptions), cl::init(false));
static cl::opt<unsigned> TimelineMaxIterations( static cl::opt<unsigned> TimelineMaxIterations(
"timeline-max-iterations", "timeline-max-iterations",
cl::desc("Maximum number of iterations to print in timeline view"), cl::desc("Maximum number of iterations to print in timeline view"),
cl::cat(ViewOptions), cl::init(0)); cl::cat(ViewOptions), cl::init(0));
static cl::opt<unsigned> TimelineMaxCycles( static cl::opt<unsigned>
"timeline-max-cycles", TimelineMaxCycles("timeline-max-cycles",
cl::desc( cl::desc("Maximum number of cycles in the timeline view, "
"Maximum number of cycles in the timeline view. Defaults to 80 cycles"), "or 0 for unlimited. Defaults to 80 cycles"),
cl::cat(ViewOptions), cl::init(80)); cl::cat(ViewOptions), cl::init(80));
static cl::opt<bool> static cl::opt<bool>
AssumeNoAlias("noalias", AssumeNoAlias("noalias",
cl::desc("If set, assume that loads and stores do not alias"), cl::desc("If set, assume that loads and stores do not alias"),
cl::cat(ToolOptions), cl::init(true)); cl::cat(ToolOptions), cl::init(true));
static cl::opt<unsigned> LoadQueueSize("lqueue", static cl::opt<unsigned> LoadQueueSize("lqueue",
cl::desc("Size of the load queue"), cl::desc("Size of the load queue"),
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