Replace SVE_PT* macros in NativeRegisterContextLinux_arm64.{cpp,h} with their equivalent defintions in LinuxPTraceDefines_arm64sve.h

[cmtice]

Summary

Commit 090306fc80dbf (August 2020) changed most of the arm64 SVE_PT* macros, but apparently did not make the changes in the NativeRegisterContextLinux_arm64.* files (or those files were pulled over from someplace else after that commit). This change replaces the macros NativeRegisterContextLinux_arm64.cpp (which as far as I can tell are no longer defined anywhere) with the replacement definitions in LinuxPTraceDefines_arm64sve.h. It also includes LinuxPTraceDefines_arm64sve.h in NativeRegisterContextLinux_arm64.h.

[omjavaid]

Do you see a specific need for this change? We have used macro definition from ptrace.h in case we are running on native aarch64/linux. This was done deliberately because newer sysroots (ubuntu bionic or focal) include these macros defined in ptrace.h by default. However custom definitions of these macros was only required to cater the need for elf core register access while running on a foreign triple.

[cmtice]

I found a need for this change when I was trying to build (cross-compile) lldb/lldb-server for aarch64 inside Chrome OS -- the build I had was failing for aarch64 with all of these symbols "undefined". If you can tell me the cmake configs and/or build flags I should use to try to get these symbols from ptrace.h, I can try that instead. But since this is a cross-compile, they might not be available on the build system?

[cmtice]

To be clear, this is all elf/linux, and the builds happen on x86_64 machines.

[omjavaid]

You can try following steps on Ubuntu Bionic x86_64 thats what I am running and build works out of the box.

1. Install build dependencies:
2. sudo apt install gcc-8-aarch64-linux-gnu
3. sudo apt install g++-8-aarch64-linux-gnu

BUILD_TYPE=Release
LLDB_TARGET_ARCH=AArch64

C_COMPILER=clang
CXX_COMPILER=clang++

LLVM_SRC_DIR=<llvm-project>

LLDB_HOST_TRIPLE=aarch64-linux-gnu

We need *tblgen from host

LLVM_HOST_BUILD_DIR=../host

BUILD_ENV_TRIPLE=gcc -dumpmachine

GCC_INC=/usr/$LLDB_HOST_TRIPLE/include
#GCC_V3=gcc --version | grep ^gcc | sed 's/^.* //g'
GCC_V3=gcc -dumpversion
TARGET_C_FLAGS="-target $LLDB_HOST_TRIPLE -I/$GCC_INC -I/$GCC_INC/c++/$GCC_V3/$LLDB_HOST_TRIPLE"
TARGET_CXX_FLAGS="$TARGET_C_FLAGS"

cmake -G Ninja \
-DCMAKE_CROSSCOMPILING=1 \
-DCMAKE_C_COMPILER=$C_COMPILER \
-DCMAKE_CXX_COMPILER=$CXX_COMPILER \
-DCMAKE_C_FLAGS="$TARGET_C_FLAGS" \
-DCMAKE_CXX_FLAGS="$TARGET_CXX_FLAGS" \
-DCMAKE_C_COMPILER_LAUNCHER=ccache \
-DCMAKE_CXX_COMPILER_LAUNCHER=ccache \
-DLLVM_USE_LINKER=gold \
-DLLVM_TABLEGEN=$LLVM_HOST_BUILD_DIR/bin/llvm-tblgen \
-DCLANG_TABLEGEN=$LLVM_HOST_BUILD_DIR/bin/clang-tblgen \
-DLLDB_TABLEGEN=$LLVM_HOST_BUILD_DIR/bin/lldb-tblgen \
-DLLVM_HOST_TRIPLE=$LLDB_HOST_TRIPLE \
-DLLVM_TARGETS_TO_BUILD=$LLDB_TARGET_ARCH \
-DLLVM_ENABLE_PROJECTS="clang;lldb" \
-DCMAKE_LIBRARY_ARCHITECTURE=$LLDB_HOST_TRIPLE \
-DCMAKE_IGNORE_PATH=/usr/lib/$BUILD_ENV_TRIPLE \
-DLLDB_TEST_COMPILER=$LLDB_HOST_TRIPLE-gcc \
-DLLDB_EXPORT_ALL_SYMBOLS=1 \
-DLLVM_ENABLE_ASSERTIONS=On \
-DCMAKE_BUILD_TYPE=$BUILD_TYPE \
-DLLDB_ENABLE_PYTHON=0 \
-DLLDB_ENABLE_LIBEDIT=0 \
-DLLDB_ENABLE_CURSES=0 \
-DLLVM_PARALLEL_LINK_JOBS=1 \
$LLVM_SRC_DIR/llvm

ninja lldb-server

[cmtice]

Can we do this just using clang/llvm? We've stopped using GCC in Chrome OS and have pretty much removed it altogether.

[omjavaid]

Above instructions use clang as compiler but utilize GCC for library includes you can replace gcc includes with your version of include paths.

[cmtice]

I have tried to build lldb-server for aarch64 inside Chrome OS following the instructions above, but due to the way things build in Chrome OS (using the Gentoo Linux portage system) this does not work. I also have not been able to find these definitions in ptrace.h files inside Chrome OS.

[omjavaid]

This is LGTM Kindly run clang-format before committing your changes. thanks!

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

 //===-- NativeRegisterContextLinux_arm64.h ---------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #if defined(__arm64__) || defined(__aarch64__)
 
 #ifndef lldb_NativeRegisterContextLinux_arm64_h
 #define lldb_NativeRegisterContextLinux_arm64_h
 
 #include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
+#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"
 #include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
 
 #include <asm/ptrace.h>
 
 namespace lldb_private {
 namespace process_linux {
 
private:
   bool m_pac_mask_is_valid;
 
   struct user_pt_regs m_gpr_arm64; // 64-bit general purpose registers.
 
   RegisterInfoPOSIX_arm64::FPU
       m_fpr; // floating-point registers including extended register sets.
 
   SVEState m_sve_state;
-  struct user_sve_header m_sve_header;
+  struct sve::user_sve_header m_sve_header;
   std::vector<uint8_t> m_sve_ptrace_payload;
 
   bool m_refresh_hwdebug_info;
 
   struct user_pac_mask {
     uint64_t data_mask;
     uint64_t insn_mask;
   };

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

 using namespace lldb_private::process_linux;
 
 std::unique_ptr<NativeRegisterContextLinux>
 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
     const ArchSpec &target_arch, NativeThreadLinux &native_thread) {
   switch (target_arch.GetMachine()) {
   case llvm::Triple::arm:
     return std::make_unique<NativeRegisterContextLinux_arm>(target_arch,
-                                                             native_thread);
   case llvm::Triple::aarch64: {
     // Configure register sets supported by this AArch64 target.
     // Read SVE header to check for SVE support.
     struct user_sve_header sve_header;
     struct iovec ioVec;
     ioVec.iov_base = &sve_header;
     ioVec.iov_len = sizeof(sve_header);
     unsigned int regset = NT_ARM_SVE;
if (m_sve_state == SVEState::Disabled) {
       // FPSR and FPCR will be located right after Z registers in
       // SVEState::FPSIMD while in SVEState::Full they will be located at the
       // end of register data after an alignment correction based on currently
       // selected vector length.
       uint32_t sve_reg_num = LLDB_INVALID_REGNUM;
       if (reg == GetRegisterInfo().GetRegNumFPSR()) {
         sve_reg_num = reg;
         if (m_sve_state == SVEState::Full)
-          offset = SVE_PT_SVE_FPSR_OFFSET(sve_vq_from_vl(m_sve_header.vl));
+          offset = sve::PTraceFPSROffset(sve::vq_from_vl(m_sve_header.vl));
         else if (m_sve_state == SVEState::FPSIMD)
-          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16);
+          offset = sve::ptrace_fpsimd_offset + (32 * 16);
       } else if (reg == GetRegisterInfo().GetRegNumFPCR()) {
         sve_reg_num = reg;
         if (m_sve_state == SVEState::Full)
-          offset = SVE_PT_SVE_FPCR_OFFSET(sve_vq_from_vl(m_sve_header.vl));
+          offset = sve::PTraceFPCROffset(sve::vq_from_vl(m_sve_header.vl));
         else if (m_sve_state == SVEState::FPSIMD)
-          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16) + 4;
+          offset = sve::ptrace_fpsimd_offset + (32 * 16) + 4;
       } else {
         // Extract SVE Z register value register number for this reg_info
         if (reg_info->value_regs &&
             reg_info->value_regs[0] != LLDB_INVALID_REGNUM)
           sve_reg_num = reg_info->value_regs[0];
         offset = CalculateSVEOffset(GetRegisterInfoAtIndex(sve_reg_num));
       }
 
if (m_sve_state == SVEState::Disabled) {
       // FPSR and FPCR will be located right after Z registers in
       // SVEState::FPSIMD while in SVEState::Full they will be located at the
       // end of register data after an alignment correction based on currently
       // selected vector length.
       uint32_t sve_reg_num = LLDB_INVALID_REGNUM;
       if (reg == GetRegisterInfo().GetRegNumFPSR()) {
         sve_reg_num = reg;
         if (m_sve_state == SVEState::Full)
-          offset = SVE_PT_SVE_FPSR_OFFSET(sve_vq_from_vl(m_sve_header.vl));
+          offset = sve::PTraceFPSROffset(sve::vq_from_vl(m_sve_header.vl));
         else if (m_sve_state == SVEState::FPSIMD)
-          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16);
+          offset = sve::ptrace_fpsimd_offset + (32 * 16);
       } else if (reg == GetRegisterInfo().GetRegNumFPCR()) {
         sve_reg_num = reg;
         if (m_sve_state == SVEState::Full)
-          offset = SVE_PT_SVE_FPCR_OFFSET(sve_vq_from_vl(m_sve_header.vl));
+          offset = sve::PTraceFPCROffset(sve::vq_from_vl(m_sve_header.vl));
         else if (m_sve_state == SVEState::FPSIMD)
-          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16) + 4;
+          offset = sve::ptrace_fpsimd_offset + (32 * 16) + 4;
       } else {
         // Extract SVE Z register value register number for this reg_info
         if (reg_info->value_regs &&
             reg_info->value_regs[0] != LLDB_INVALID_REGNUM)
           sve_reg_num = reg_info->value_regs[0];
         offset = CalculateSVEOffset(GetRegisterInfoAtIndex(sve_reg_num));
       }
 
void NativeRegisterContextLinux_arm64::ConfigureRegisterContext() {
   // on every stop and configures SVE vector length.
   // If m_sve_state is set to SVEState::Disabled on first stop, code below will
   // be deemed non operational for the lifetime of current process.
   if (!m_sve_header_is_valid && m_sve_state != SVEState::Disabled) {
     Status error = ReadSVEHeader();
     if (error.Success()) {
       // If SVE is enabled thread can switch between SVEState::FPSIMD and
       // SVEState::Full on every stop.
-      if ((m_sve_header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD)
+      if ((m_sve_header.flags & sve::ptrace_regs_mask) ==
+          sve::ptrace_regs_fpsimd)
         m_sve_state = SVEState::FPSIMD;
-      else if ((m_sve_header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE)
+      else if ((m_sve_header.flags & sve::ptrace_regs_mask) ==
+               sve::ptrace_regs_sve)
         m_sve_state = SVEState::Full;
 
       // On every stop we configure SVE vector length by calling
       // ConfigureVectorLength regardless of current SVEState of this thread.
       uint32_t vq = RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64SVE;
       if (sve_vl_valid(m_sve_header.vl))
-        vq = sve_vq_from_vl(m_sve_header.vl);
+        vq = sve::vq_from_vl(m_sve_header.vl);
 
       GetRegisterInfo().ConfigureVectorLength(vq);
-      m_sve_ptrace_payload.resize(SVE_PT_SIZE(vq, SVE_PT_REGS_SVE));
+      m_sve_ptrace_payload.resize(sve::PTraceSize(vq, sve::ptrace_regs_sve));
     }
   }
 }
 
 uint32_t NativeRegisterContextLinux_arm64::CalculateFprOffset(
     const RegisterInfo *reg_info) const {
   return reg_info->byte_offset - GetGPRSize();
 }
 
 uint32_t NativeRegisterContextLinux_arm64::CalculateSVEOffset(
     const RegisterInfo *reg_info) const {
   // Start of Z0 data is after GPRs plus 8 bytes of vg register
   uint32_t sve_reg_offset = LLDB_INVALID_INDEX32;
   if (m_sve_state == SVEState::FPSIMD) {
     const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
-    sve_reg_offset =
-        SVE_PT_FPSIMD_OFFSET + (reg - GetRegisterInfo().GetRegNumSVEZ0()) * 16;
+    sve_reg_offset = sve::ptrace_fpsimd_offset +
+                     (reg - GetRegisterInfo().GetRegNumSVEZ0()) * 16;
   } else if (m_sve_state == SVEState::Full) {
     uint32_t sve_z0_offset = GetGPRSize() + 16;
     sve_reg_offset =
-        SVE_SIG_REGS_OFFSET + reg_info->byte_offset - sve_z0_offset;
+        sve::SigRegsOffset() + reg_info->byte_offset - sve_z0_offset;
   }
   return sve_reg_offset;
 }
 
 void *NativeRegisterContextLinux_arm64::GetSVEBuffer() {
   if (m_sve_state == SVEState::FPSIMD)
-    return m_sve_ptrace_payload.data() + SVE_PT_FPSIMD_OFFSET;
+    return m_sve_ptrace_payload.data() + sve::ptrace_fpsimd_offset;
 
   return m_sve_ptrace_payload.data();
 }
 
 std::vector<uint32_t> NativeRegisterContextLinux_arm64::GetExpeditedRegisters(
     ExpeditedRegs expType) const {
   std::vector<uint32_t> expedited_reg_nums =
       NativeRegisterContext::GetExpeditedRegisters(expType);