[libunwind] Define and use portable macro for checking for presence of ASAN

[daniel-levin]

Summary

• libunwind does not build with GCC due to a change introduced in adf1561d6ce8 which uses the clang-only __has_feature macro.
• The problem is resolved by defining an "Is asan present?" macro that works across different compilers

[daniel-levin]

Hi all :)

I am new to contributing to LLVM. This change fixes a broken build when bootstrapping with gcc. Both gcc and msvc define the SANITIZE_ADDRESS macro when using asan.

Please give me any and all feedback. I am happy to make changes.

[compnerd]

libunwind/src/libunwind.cpp

24

I think that I would rather see this as:

#if !defined(__has_feature)
#define __has_feature(feature) 0
#endif

Then you can use # if __has_feature(address_sanitizer) || defined(__SANITIZE_ADDRESS__) below.

That along with a comment would be sufficient. The GCC check would still be insufficient as it doesn't cover KASAN, but I don't believe that GCC supports that currently.

[daniel-levin]

[libunwind] Use most appropriate macro for checking for presence of ASan.

[daniel-levin]

Responded to comments from Saleem. Apologies for the noise in getting the diff correct. I had not used arc before.

[compnerd]

LGTM; do you need someone to commit this on your behalf?

[daniel-levin]

Yes please. I do not have commit access. Thank you Saleem :)

libunwind/src/libunwind.cpp

 
 #include <libunwind.h>
 
 #include "libunwind_ext.h"
 #include "config.h"
 
 #include <stdlib.h>
 
-#if defined(__has_feature)
-#define has_asan_portable __has_feature(address_sanitizer)
-#elif defined(__SANITIZE_ADDRESS__)
-#define has_asan_portable __SANITIZE_ADDRESS__
-#else
-#define has_asan_portable 0
+// Define the __has_feature extension for compilers that do not support it so that
+// we can later check for the presence of ASan in a compiler-neutral way.
+#if !defined(__has_feature)
+#define __has_feature(feature) 0
 #endif
 
-#if has_asan_portable
+#if __has__feature(address_sanitizer) || defined(__SANITIZE_ADDRESS__)
 #include <sanitizer/asan_interface.h>
 #endif
 
 #if !defined(__USING_SJLJ_EXCEPTIONS__)
 #include "AddressSpace.hpp"
 #include "UnwindCursor.hpp"
 
 using namespace libunwind;
if (info->end_ip == 0)
     return UNW_ENOINFO;
   return UNW_ESUCCESS;
 }
 _LIBUNWIND_WEAK_ALIAS(__unw_get_proc_info, unw_get_proc_info)
 
 /// Resume execution at cursor position (aka longjump).
 _LIBUNWIND_HIDDEN int __unw_resume(unw_cursor_t *cursor) {
   _LIBUNWIND_TRACE_API("__unw_resume(cursor=%p)", static_cast<void *>(cursor));
-#if has_asan_portable
+#if __has__feature(address_sanitizer) || defined(__SANITIZE_ADDRESS__)
   // Inform the ASan runtime that now might be a good time to clean stuff up.
   __asan_handle_no_return();
 #endif
   AbstractUnwindCursor *co = (AbstractUnwindCursor *)cursor;
   co->jumpto();
   return UNW_EUNSPEC;
 }
 _LIBUNWIND_WEAK_ALIAS(__unw_resume, unw_resume)

lldb/include/lldb/Utility/Timer.h

 //===-- Timer.h -------------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLDB_UTILITY_TIMER_H
 #define LLDB_UTILITY_TIMER_H
 
 #include "lldb/lldb-defines.h"
-#include "llvm/ADT/ScopeExit.h"
 #include "llvm/Support/Chrono.h"
-#include "llvm/Support/Signposts.h"
 #include <atomic>
 #include <cstdint>
 
-namespace llvm {
-  class SignpostEmitter;
-}
-
 namespace lldb_private {
 class Stream;
 
 /// \class Timer Timer.h "lldb/Utility/Timer.h"
 /// A timer class that simplifies common timing metrics.
 
 class Timer {
 public:
protected:
   static std::atomic<bool> g_quiet;
   static std::atomic<unsigned> g_display_depth;
 
 private:
   Timer(const Timer &) = delete;
   const Timer &operator=(const Timer &) = delete;
 };
 
-llvm::SignpostEmitter &GetSignposts();
-
 } // namespace lldb_private
 
 // Use a format string because LLVM_PRETTY_FUNCTION might not be a string
 // literal.
 #define LLDB_SCOPED_TIMER()                                                    \
   static ::lldb_private::Timer::Category _cat(LLVM_PRETTY_FUNCTION);           \
-  ::lldb_private::Timer _scoped_timer(_cat, "%s", LLVM_PRETTY_FUNCTION);       \
-  SIGNPOST_EMITTER_START_INTERVAL(::lldb_private::GetSignposts(),              \
-                                  &_scoped_timer, "%s", LLVM_PRETTY_FUNCTION); \
-  auto _scoped_signpost = llvm::make_scope_exit([&_scoped_timer]() {           \
-    ::lldb_private::GetSignposts().endInterval(&_scoped_timer);                \
-  })
-
-#define LLDB_SCOPED_TIMERF(FMT, ...)                                           \
+  ::lldb_private::Timer _scoped_timer(_cat, "%s", LLVM_PRETTY_FUNCTION)
+#define LLDB_SCOPED_TIMERF(...)                                                \
   static ::lldb_private::Timer::Category _cat(LLVM_PRETTY_FUNCTION);           \
-  ::lldb_private::Timer _scoped_timer(_cat, FMT, __VA_ARGS__);                 \
-  SIGNPOST_EMITTER_START_INTERVAL(::lldb_private::GetSignposts(),              \
-                                  &_scoped_timer, FMT, __VA_ARGS__);           \
-  auto _scoped_signpost = llvm::make_scope_exit([&_scoped_timer]() {           \
-    ::lldb_private::GetSignposts().endInterval(&_scoped_timer);                \
-  })
+  ::lldb_private::Timer _scoped_timer(_cat, __VA_ARGS__)
 
 #endif // LLDB_UTILITY_TIMER_H

lldb/source/Utility/Timer.cpp

 namespace {
 typedef std::vector<Timer *> TimerStack;
 static std::atomic<Timer::Category *> g_categories;
 } // end of anonymous namespace
 
 /// Allows llvm::Timer to emit signposts when supported.
 static llvm::ManagedStatic<llvm::SignpostEmitter> Signposts;
 
-llvm::SignpostEmitter &lldb_private::GetSignposts() { return *Signposts; }
-
 std::atomic<bool> Timer::g_quiet(true);
 std::atomic<unsigned> Timer::g_display_depth(0);
 static std::mutex &GetFileMutex() {
   static std::mutex *g_file_mutex_ptr = new std::mutex();
   return *g_file_mutex_ptr;
 }
 
 static TimerStack &GetTimerStackForCurrentThread() {
do {
     m_next = expected;
   } while (!g_categories.compare_exchange_weak(expected, this));
 }
 
 void Timer::SetQuiet(bool value) { g_quiet = value; }
 
 Timer::Timer(Timer::Category &category, const char *format, ...)
     : m_category(category), m_total_start(std::chrono::steady_clock::now()) {
+  Signposts->startInterval(this, m_category.GetName());
   TimerStack &stack = GetTimerStackForCurrentThread();
 
   stack.push_back(this);
   if (g_quiet && stack.size() <= g_display_depth) {
     std::lock_guard<std::mutex> lock(GetFileMutex());
 
     // Indent
     ::fprintf(stdout, "%*s", int(stack.size() - 1) * TIMER_INDENT_AMOUNT, "");

 
 Timer::~Timer() {
   using namespace std::chrono;
 
   auto stop_time = steady_clock::now();
   auto total_dur = stop_time - m_total_start;
   auto timer_dur = total_dur - m_child_duration;
 
+  Signposts->endInterval(this, m_category.GetName());
+
   TimerStack &stack = GetTimerStackForCurrentThread();
   if (g_quiet && stack.size() <= g_display_depth) {
     std::lock_guard<std::mutex> lock(GetFileMutex());
     ::fprintf(stdout, "%*s%.9f sec (%.9f sec)\n",
               int(stack.size() - 1) * TIMER_INDENT_AMOUNT, "",
               duration<double>(total_dur).count(),
               duration<double>(timer_dur).count());
   }

llvm/cmake/modules/AddLLVM.cmake

sys.stdout.write(';'.join(relpath(p) for p in sys.argv[2].split(';')))"
   set(${out_pathlist} "${pathlist_relative}" PARENT_SCOPE)
 endfunction()
 
 # Converts a file that's relative to the current python file to an absolute
 # path. Since this uses __file__, it has to be emitted into python files that
 # use it and can't be in a lit module. Use with make_paths_relative().
 string(CONCAT LLVM_LIT_PATH_FUNCTION
   "# Allow generated file to be relocatable.\n"
+  "from pathlib import Path\n"
   "def path(p):\n"
   "    if not p: return ''\n"
-  "    return os.path.join(os.path.dirname(os.path.abspath(__file__)), p)\n"
+  "    return str((Path(__file__).parent / p).resolve())\n"
   )
 
 # This function provides an automatic way to 'configure'-like generate a file
 # based on a set of common and custom variables, specifically targeting the
 # variables needed for the 'lit.site.cfg' files. This function bundles the
 # common variables that any Lit instance is likely to need, and custom
 # variables can be passed in.
 # The keyword PATHS is followed by a list of cmake variable names that are

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
   ///     unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
   ///     findCommutedOpIndices(MI, Op1, Op2);
   /// can be interpreted as a query asking to find an operand that would be
   /// commutable with the operand#1.
   virtual bool findCommutedOpIndices(const MachineInstr &MI,
                                      unsigned &SrcOpIdx1,
                                      unsigned &SrcOpIdx2) const;
 
-  /// Returns true if the target has a preference on the operands order of
-  /// the given machine instruction. And specify if \p Commute is required to
-  /// get the desired operands order.
-  virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {
-    return false;
-  }
-
   /// A pair composed of a register and a sub-register index.
   /// Used to give some type checking when modeling Reg:SubReg.
   struct RegSubRegPair {
     Register Reg;
     unsigned SubReg;
 
     RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
         : Reg(Reg), SubReg(SubReg) {}

llvm/include/llvm/Support/Signposts.h

 /// of Interest track on the instruments timeline.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_SUPPORT_SIGNPOSTS_H
 #define LLVM_SUPPORT_SIGNPOSTS_H
 
 #include "llvm/ADT/StringRef.h"
-#include "llvm/Config/config.h"
 #include <memory>
 
-#if LLVM_SUPPORT_XCODE_SIGNPOSTS
-#include <Availability.h>
-#include <os/signpost.h>
-#endif
-
-#define SIGNPOSTS_AVAILABLE()                                                  \
-  __builtin_available(macos 10.14, iOS 12, tvOS 12, watchOS 5, *)
-
 namespace llvm {
 class SignpostEmitterImpl;
 
 /// Manages the emission of signposts into the recording method supported by
 /// the OS.
 class SignpostEmitter {
   std::unique_ptr<SignpostEmitterImpl> Impl;
 
 public:
   SignpostEmitter();
   ~SignpostEmitter();
 
   bool isEnabled() const;
 
   /// Begin a signposted interval for a given object.
   void startInterval(const void *O, StringRef Name);
-
-#if LLVM_SUPPORT_XCODE_SIGNPOSTS
-  os_log_t &getLogger() const;
-  os_signpost_id_t getSignpostForObject(const void *O);
-#endif
-    
-  /// A macro to take advantage of the special format string handling
-  /// in the os_signpost API. The format string substitution is
-  /// deferred to the log consumer and done outside of the
-  /// application.
-#if LLVM_SUPPORT_XCODE_SIGNPOSTS
-#define SIGNPOST_EMITTER_START_INTERVAL(SIGNPOST_EMITTER, O, ...)              \
-  do {                                                                         \
-    if ((SIGNPOST_EMITTER).isEnabled())                                        \
-      if (SIGNPOSTS_AVAILABLE())                                               \
-        os_signpost_interval_begin((SIGNPOST_EMITTER).getLogger(),             \
-                                   (SIGNPOST_EMITTER).getSignpostForObject(O), \
-                                   "LLVM Timers", __VA_ARGS__);                \
-  } while (0)
-#else
-#define SIGNPOST_EMITTER_START_INTERVAL(SIGNPOST_EMITTER, O, ...)              \
-  do {                                                                         \
-  } while (0)
-#endif
-  
   /// End a signposted interval for a given object.
-  void endInterval(const void *O);
+  void endInterval(const void *O, StringRef Name);
 };
 
 } // end namespace llvm
 
 #endif // LLVM_SUPPORT_SIGNPOSTS_H

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

bool TwoAddressInstructionPass::isProfitableToCommute(Register RegA,
   // instruction pass should be integrated with register allocation pass where
   // interference graph is available.
   if (isRevCopyChain(RegC, RegA, MaxDataFlowEdge))
     return true;
 
   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))
     return false;
 
-  // Look for other target specific commute preference.
-  bool Commute;
-  if (TII->hasCommutePreference(*MI, Commute))
-    return Commute;
-
   // Since there are no intervening uses for both registers, then commute
   // if the def of RegC is closer. Its live interval is shorter.
   return LastDefB && LastDefC && LastDefC > LastDefB;
 }
 
 /// Commute a two-address instruction and update the basic block, distance map,
 /// and live variables if needed. Return true if it is successful.
 bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI,

llvm/lib/Support/Signposts.cpp

 //===-- Signposts.cpp - Interval debug annotations ------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/Signposts.h"
 #include "llvm/Support/Timer.h"
 
+#include "llvm/Config/config.h"
 #if LLVM_SUPPORT_XCODE_SIGNPOSTS
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/Support/Mutex.h"
+#include <Availability.h>
+#include <os/signpost.h>
 #endif // if LLVM_SUPPORT_XCODE_SIGNPOSTS
 
 using namespace llvm;
 
 #if LLVM_SUPPORT_XCODE_SIGNPOSTS
+#define SIGNPOSTS_AVAILABLE()                                                  \
+  __builtin_available(macos 10.14, iOS 12, tvOS 12, watchOS 5, *)
 namespace {
 os_log_t *LogCreator() {
   os_log_t *X = new os_log_t;
   *X = os_log_create("org.llvm.signposts", OS_LOG_CATEGORY_POINTS_OF_INTEREST);
   return X;
 }
 struct LogDeleter {
   void operator()(os_log_t *X) const {
     os_release(*X);
     delete X;
   }
 };
 } // end anonymous namespace
 
 namespace llvm {
 class SignpostEmitterImpl {
   using LogPtrTy = std::unique_ptr<os_log_t, LogDeleter>;
+  using LogTy = LogPtrTy::element_type;
 
   LogPtrTy SignpostLog;
   DenseMap<const void *, os_signpost_id_t> Signposts;
   sys::SmartMutex<true> Mutex;
 
-public:
-  os_log_t &getLogger() const { return *SignpostLog; }
+  LogTy &getLogger() const { return *SignpostLog; }
   os_signpost_id_t getSignpostForObject(const void *O) {
     sys::SmartScopedLock<true> Lock(Mutex);
     const auto &I = Signposts.find(O);
     if (I != Signposts.end())
       return I->second;
     os_signpost_id_t ID = {};
     if (SIGNPOSTS_AVAILABLE()) {
       ID = os_signpost_id_make_with_pointer(getLogger(), O);
     }
     const auto &Inserted = Signposts.insert(std::make_pair(O, ID));
     return Inserted.first->second;
   }
 
+public:
   SignpostEmitterImpl() : SignpostLog(LogCreator()) {}
 
   bool isEnabled() const {
     if (SIGNPOSTS_AVAILABLE())
       return os_signpost_enabled(*SignpostLog);
     return false;
   }
 
   void startInterval(const void *O, llvm::StringRef Name) {
     if (isEnabled()) {
       if (SIGNPOSTS_AVAILABLE()) {
         // Both strings used here are required to be constant literal strings.
         os_signpost_interval_begin(getLogger(), getSignpostForObject(O),
                                    "LLVM Timers", "%s", Name.data());
       }
     }
   }
 
-  void endInterval(const void *O) {
+  void endInterval(const void *O, llvm::StringRef Name) {
     if (isEnabled()) {
       if (SIGNPOSTS_AVAILABLE()) {
         // Both strings used here are required to be constant literal strings.
         os_signpost_interval_end(getLogger(), getSignpostForObject(O),
                                  "LLVM Timers", "");
       }
     }
   }

 void SignpostEmitter::startInterval(const void *O, StringRef Name) {
 #if HAVE_ANY_SIGNPOST_IMPL
   if (Impl == nullptr)
     return;
   return Impl->startInterval(O, Name);
 #endif // if !HAVE_ANY_SIGNPOST_IMPL
 }
 
-#if HAVE_ANY_SIGNPOST_IMPL
-os_log_t &SignpostEmitter::getLogger() const { return Impl->getLogger(); }
-os_signpost_id_t SignpostEmitter::getSignpostForObject(const void *O) {
-  return Impl->getSignpostForObject(O);
-}
-#endif
-
-void SignpostEmitter::endInterval(const void *O) {
+void SignpostEmitter::endInterval(const void *O, StringRef Name) {
 #if HAVE_ANY_SIGNPOST_IMPL
   if (Impl == nullptr)
     return;
-  Impl->endInterval(O);
+  Impl->endInterval(O, Name);
 #endif // if !HAVE_ANY_SIGNPOST_IMPL
 }

llvm/lib/Support/Timer.cpp

void Timer::startTimer() {
   StartTime = TimeRecord::getCurrentTime(true);
 }
 
 void Timer::stopTimer() {
   assert(Running && "Cannot stop a paused timer");
   Running = false;
   Time += TimeRecord::getCurrentTime(false);
   Time -= StartTime;
-  Signposts->endInterval(this);
+  Signposts->endInterval(this, getName());
 }
 
 void Timer::clear() {
   Running = Triggered = false;
   Time = StartTime = TimeRecord();
 }
 
 static void printVal(double Val, double Total, raw_ostream &OS) {

llvm/lib/Target/X86/X86FixupLEAs.cpp

void processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I,
                                  MachineBasicBlock &MBB, bool OptIncDec);
 
   /// Look for LEAs that are really two address LEAs that we might be able to
   /// turn into regular ADD instructions.
   bool optTwoAddrLEA(MachineBasicBlock::iterator &I,
                      MachineBasicBlock &MBB, bool OptIncDec,
                      bool UseLEAForSP) const;
 
-  /// Look for and transform the sequence
-  ///     lea (reg1, reg2), reg3
-  ///     sub reg3, reg4
-  /// to
-  ///     sub reg1, reg4
-  ///     sub reg2, reg4
-  /// It can also optimize the sequence lea/add similarly.
-  bool optLEAALU(MachineBasicBlock::iterator &I, MachineBasicBlock &MBB) const;
-
-  /// Step forwards in MBB, looking for an ADD/SUB instruction which uses
-  /// the dest register of LEA instruction I.
-  MachineBasicBlock::iterator searchALUInst(MachineBasicBlock::iterator &I,
-                                            MachineBasicBlock &MBB) const;
-
-  /// Check instructions between LeaI and AluI (exclusively).
-  /// Set BaseIndexDef to true if base or index register from LeaI is defined.
-  /// Set AluDestRef to true if the dest register of AluI is used or defined.
-  void checkRegUsage(MachineBasicBlock::iterator &LeaI,
-                     MachineBasicBlock::iterator &AluI, bool &BaseIndexDef,
-                     bool &AluDestRef) const;
-
   /// Determine if an instruction references a machine register
   /// and, if so, whether it reads or writes the register.
   RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
 
   /// Step backwards through a basic block, looking
   /// for an instruction which writes a register within
   /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
   MachineBasicBlock::iterator searchBackwards(MachineOperand &p,
static inline unsigned getADDrrFromLEA(unsigned LEAOpcode) {
   case X86::LEA32r:
   case X86::LEA64_32r:
     return X86::ADD32rr;
   case X86::LEA64r:
     return X86::ADD64rr;
   }
 }
 
-static inline unsigned getSUBrrFromLEA(unsigned LEAOpcode) {
-  switch (LEAOpcode) {
-  default:
-    llvm_unreachable("Unexpected LEA instruction");
-  case X86::LEA32r:
-  case X86::LEA64_32r:
-    return X86::SUB32rr;
-  case X86::LEA64r:
-    return X86::SUB64rr;
-  }
-}
-
 static inline unsigned getADDriFromLEA(unsigned LEAOpcode,
                                        const MachineOperand &Offset) {
   bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
   switch (LEAOpcode) {
   default:
     llvm_unreachable("Unexpected LEA instruction");
   case X86::LEA32r:
   case X86::LEA64_32r:
static inline unsigned getINCDECFromLEA(unsigned LEAOpcode, bool IsINC) {
   case X86::LEA32r:
   case X86::LEA64_32r:
     return IsINC ? X86::INC32r : X86::DEC32r;
   case X86::LEA64r:
     return IsINC ? X86::INC64r : X86::DEC64r;
   }
 }
 
-MachineBasicBlock::iterator
-FixupLEAPass::searchALUInst(MachineBasicBlock::iterator &I,
-                            MachineBasicBlock &MBB) const {
-  const int InstrDistanceThreshold = 5;
-  int InstrDistance = 1;
-  MachineBasicBlock::iterator CurInst = std::next(I);
-
-  unsigned LEAOpcode = I->getOpcode();
-  unsigned AddOpcode = getADDrrFromLEA(LEAOpcode);
-  unsigned SubOpcode = getSUBrrFromLEA(LEAOpcode);
-  Register DestReg = I->getOperand(0).getReg();
-
-  while (CurInst != MBB.end()) {
-    if (CurInst->isCall() || CurInst->isInlineAsm())
-      break;
-    if (InstrDistance > InstrDistanceThreshold)
-      break;
-
-    // Check if the lea dest register is used in an add/sub instruction only.
-    for (unsigned I = 0, E = CurInst->getNumOperands(); I != E; ++I) {
-      MachineOperand &Opnd = CurInst->getOperand(I);
-      if (Opnd.isReg()) {
-        if (Opnd.getReg() == DestReg) {
-          if (Opnd.isDef() || !Opnd.isKill())
-            return MachineBasicBlock::iterator();
-
-          unsigned AluOpcode = CurInst->getOpcode();
-          if (AluOpcode != AddOpcode && AluOpcode != SubOpcode)
-            return MachineBasicBlock::iterator();
-
-          MachineOperand &Opnd2 = CurInst->getOperand(3 - I);
-          MachineOperand AluDest = CurInst->getOperand(0);
-          if (Opnd2.getReg() != AluDest.getReg())
-            return MachineBasicBlock::iterator();
-
-          // X - (Y + Z) may generate different flags than (X - Y) - Z when
-          // there is overflow. So we can't change the alu instruction if the
-          // flags register is live.
-          if (!CurInst->registerDefIsDead(X86::EFLAGS, TRI))
-            return MachineBasicBlock::iterator();
-
-          return CurInst;
-        }
-        if (TRI->regsOverlap(DestReg, Opnd.getReg()))
-          return MachineBasicBlock::iterator();
-      }
-    }
-
-    InstrDistance++;
-    ++CurInst;
-  }
-  return MachineBasicBlock::iterator();
-}
-
-void FixupLEAPass::checkRegUsage(MachineBasicBlock::iterator &LeaI,
-                                 MachineBasicBlock::iterator &AluI,
-                                 bool &BaseIndexDef, bool &AluDestRef) const {
-  BaseIndexDef = AluDestRef = false;
-  Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg();
-  Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg();
-  Register AluDestReg = AluI->getOperand(0).getReg();
-
-  MachineBasicBlock::iterator CurInst = std::next(LeaI);
-  while (CurInst != AluI) {
-    for (unsigned I = 0, E = CurInst->getNumOperands(); I != E; ++I) {
-      MachineOperand &Opnd = CurInst->getOperand(I);
-      if (!Opnd.isReg())
-        continue;
-      Register Reg = Opnd.getReg();
-      if (TRI->regsOverlap(Reg, AluDestReg))
-        AluDestRef = true;
-      if (Opnd.isDef() &&
-          (TRI->regsOverlap(Reg, BaseReg) || TRI->regsOverlap(Reg, IndexReg))) {
-        BaseIndexDef = true;
-      }
-    }
-    ++CurInst;
-  }
-}
-
-bool FixupLEAPass::optLEAALU(MachineBasicBlock::iterator &I,
-                             MachineBasicBlock &MBB) const {
-  // Look for an add/sub instruction which uses the result of lea.
-  MachineBasicBlock::iterator AluI = searchALUInst(I, MBB);
-  if (AluI == MachineBasicBlock::iterator())
-    return false;
-
-  // Check if there are any related register usage between lea and alu.
-  bool BaseIndexDef, AluDestRef;
-  checkRegUsage(I, AluI, BaseIndexDef, AluDestRef);
-
-  MachineBasicBlock::iterator InsertPos = AluI;
-  if (BaseIndexDef) {
-    if (AluDestRef)
-      return false;
-    InsertPos = I;
-  }
-
-  // Check if there are same registers.
-  Register AluDestReg = AluI->getOperand(0).getReg();
-  Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg();
-  Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg();
-  if (I->getOpcode() == X86::LEA64_32r) {
-    BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
-    IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
-  }
-  if (AluDestReg == IndexReg) {
-    if (BaseReg == IndexReg)
-      return false;
-    std::swap(BaseReg, IndexReg);
-  }
-
-  // Now it's safe to change instructions.
-  MachineInstr *NewMI1, *NewMI2;
-  unsigned NewOpcode = AluI->getOpcode();
-  NewMI1 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode),
-                   AluDestReg)
-               .addReg(AluDestReg)
-               .addReg(BaseReg);
-  NewMI1->addRegisterDead(X86::EFLAGS, TRI);
-  NewMI2 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode),
-                   AluDestReg)
-               .addReg(AluDestReg)
-               .addReg(IndexReg);
-  NewMI2->addRegisterDead(X86::EFLAGS, TRI);
-
-  MBB.getParent()->substituteDebugValuesForInst(*AluI, *NewMI1, 1);
-  MBB.getParent()->substituteDebugValuesForInst(*AluI, *NewMI2, 1);
-  MBB.erase(I);
-  MBB.erase(AluI);
-  I = NewMI1;
-  return true;
-}
-
 bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
                                  MachineBasicBlock &MBB, bool OptIncDec,
                                  bool UseLEAForSP) const {
   MachineInstr &MI = *I;
 
   const MachineOperand &Base =    MI.getOperand(1 + X86::AddrBaseReg);
   const MachineOperand &Scale =   MI.getOperand(1 + X86::AddrScaleAmt);
   const MachineOperand &Index =   MI.getOperand(1 + X86::AddrIndexReg);
if (MI.getOpcode() == X86::LEA64_32r) {
     if (BaseReg != 0)
       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
     if (IndexReg != 0)
       IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
   }
 
   MachineInstr *NewMI = nullptr;
 
-  // Case 1.
   // Look for lea(%reg1, %reg2), %reg1 or lea(%reg2, %reg1), %reg1
   // which can be turned into add %reg2, %reg1
   if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
       (DestReg == BaseReg || DestReg == IndexReg)) {
     unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode());
     if (DestReg != BaseReg)
       std::swap(BaseReg, IndexReg);
 
     if (MI.getOpcode() == X86::LEA64_32r) {
       // TODO: Do we need the super register implicit use?
       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
         .addReg(BaseReg).addReg(IndexReg)
         .addReg(Base.getReg(), RegState::Implicit)
         .addReg(Index.getReg(), RegState::Implicit);
     } else {
       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
         .addReg(BaseReg).addReg(IndexReg);
     }
   } else if (DestReg == BaseReg && IndexReg == 0) {
-    // Case 2.
     // This is an LEA with only a base register and a displacement,
     // We can use ADDri or INC/DEC.
 
     // Does this LEA have one these forms:
     // lea  %reg, 1(%reg)
     // lea  %reg, -1(%reg)
     if (OptIncDec && (Disp.getImm() == 1 || Disp.getImm() == -1)) {
       bool IsINC = Disp.getImm() == 1;
if (OptIncDec && (Disp.getImm() == 1 || Disp.getImm() == -1)) {
         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
           .addReg(BaseReg).addImm(Disp.getImm())
           .addReg(Base.getReg(), RegState::Implicit);
       } else {
         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
           .addReg(BaseReg).addImm(Disp.getImm());
       }
     }
-  } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) {
-    // Case 3.
-    // Look for and transform the sequence
-    //     lea (reg1, reg2), reg3
-    //     sub reg3, reg4
-    return optLEAALU(I, MBB);
   } else
     return false;
 
   MBB.getParent()->substituteDebugValuesForInst(*I, *NewMI, 1);
   MBB.erase(I);
   I = NewMI;
   return true;
 }

llvm/lib/Target/X86/X86InstrInfo.h

public:
   /// For example, calling this method this way:
   ///     unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
   ///     findCommutedOpIndices(MI, Op1, Op2);
   /// can be interpreted as a query asking to find an operand that would be
   /// commutable with the operand#1.
   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
                              unsigned &SrcOpIdx2) const override;
 
-  /// Returns true if we have preference on the operands order in MI, the
-  /// commute decision is returned in Commute.
-  bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
-
   /// Returns an adjusted FMA opcode that must be used in FMA instruction that
   /// performs the same computations as the given \p MI but which has the
   /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
   /// It may return 0 if it is unsafe to commute the operands.
   /// Note that a machine instruction (instead of its opcode) is passed as the
   /// first parameter to make it possible to analyze the instruction's uses and
   /// commute the first operand of FMA even when it seems unsafe when you look
   /// at the opcode. For example, it is Ok to commute the first operand of

llvm/lib/Target/X86/X86InstrInfo.cpp

if (X86II::isKMasked(Desc.TSFlags)) {
       return true;
     }
 
     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
   }
   return false;
 }
 
-static bool isConvertibleLEA(MachineInstr *MI) {
-  unsigned Opcode = MI->getOpcode();
-  if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
-      Opcode != X86::LEA64_32r)
-    return false;
-
-  const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt);
-  const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp);
-  const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg);
-
-  if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
-      Scale.getImm() > 1)
-    return false;
-
-  return true;
-}
-
-bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
-  // Currently we're interested in following sequence only.
-  //   r3 = lea r1, r2
-  //   r5 = add r3, r4
-  // Both r3 and r4 are killed in add, we hope the add instruction has the
-  // operand order
-  //   r5 = add r4, r3
-  // So later in X86FixupLEAs the lea instruction can be rewritten as add.
-  unsigned Opcode = MI.getOpcode();
-  if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
-    return false;
-
-  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
-  Register Reg1 = MI.getOperand(1).getReg();
-  Register Reg2 = MI.getOperand(2).getReg();
-
-  // Check if Reg1 comes from LEA in the same MBB.
-  if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg1)) {
-    if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
-      Commute = true;
-      return true;
-    }
-  }
-
-  // Check if Reg2 comes from LEA in the same MBB.
-  if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg2)) {
-    if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
-      Commute = false;
-      return true;
-    }
-  }
-
-  return false;
-}
-
 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default: return X86::COND_INVALID;
   case X86::JCC_1:
     return static_cast<X86::CondCode>(
         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
   }
 }

llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll

 ; CHECK-NEXT:    movq X(%rip), %rdx
 ; CHECK-NEXT:    addq %r15, %rdx
 ; CHECK-NEXT:    movq X(%rip), %rsi
 ; CHECK-NEXT:    bswapq %rsi
 ; CHECK-NEXT:    leaq (%r11,%r14), %rbx
 ; CHECK-NEXT:    addq %r15, %rbx
 ; CHECK-NEXT:    addq %rdx, %rbx
 ; CHECK-NEXT:    addq %rsi, %rbx
-; CHECK-NEXT:    leaq (%r9,%r10), %rdx
-; CHECK-NEXT:    addq %rdx, %rdx
-; CHECK-NEXT:    addq %r8, %rdx
+; CHECK-NEXT:    leaq (%r9,%r10), %rsi
+; CHECK-NEXT:    leaq (%rsi,%r8), %rdx
+; CHECK-NEXT:    addq %rsi, %rdx
 ; CHECK-NEXT:    movq X(%rip), %rdi
 ; CHECK-NEXT:    addq %rbx, %r12
 ; CHECK-NEXT:    addq %r8, %rdx
 ; CHECK-NEXT:    bswapq %rdi
 ; CHECK-NEXT:    addq %rbx, %rdx
 ; CHECK-NEXT:    leaq (%r15,%r14), %rsi
 ; CHECK-NEXT:    addq %r12, %rsi
 ; CHECK-NEXT:    addq %r11, %rdi
 ; CHECK-NEXT:    addq %rsi, %rdi
-; CHECK-NEXT:    leaq (%r10,%r8), %rsi
-; CHECK-NEXT:    addq %rsi, %rsi
-; CHECK-NEXT:    addq %rdx, %rsi
+; CHECK-NEXT:    leaq (%r10,%r8), %rbx
+; CHECK-NEXT:    leaq (%rdx,%rbx), %rsi
+; CHECK-NEXT:    addq %rbx, %rsi
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %r12, %rdi
 ; CHECK-NEXT:    addq %rdi, %r9
 ; CHECK-NEXT:    addq %rdx, %rsi
 ; CHECK-NEXT:    addq %rdi, %rsi
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%r12,%r15), %rdi
 ; CHECK-NEXT:    addq %r9, %rdi
 ; CHECK-NEXT:    addq %r14, %rbx
 ; CHECK-NEXT:    addq %rdi, %rbx
-; CHECK-NEXT:    leaq (%rdx,%r8), %rdi
-; CHECK-NEXT:    addq %rdi, %rdi
-; CHECK-NEXT:    addq %rsi, %rdi
+; CHECK-NEXT:    leaq (%rdx,%r8), %rax
+; CHECK-NEXT:    leaq (%rsi,%rax), %rdi
+; CHECK-NEXT:    addq %rax, %rdi
 ; CHECK-NEXT:    movq X(%rip), %rcx
 ; CHECK-NEXT:    addq %r9, %rbx
 ; CHECK-NEXT:    addq %rbx, %r10
 ; CHECK-NEXT:    addq %rsi, %rdi
 ; CHECK-NEXT:    bswapq %rcx
 ; CHECK-NEXT:    addq %rbx, %rdi
 ; CHECK-NEXT:    leaq (%r9,%r12), %rax
 ; CHECK-NEXT:    addq %r10, %rax
 ; CHECK-NEXT:    addq %r15, %rcx
 ; CHECK-NEXT:    addq %rax, %rcx
-; CHECK-NEXT:    leaq (%rsi,%rdx), %r11
-; CHECK-NEXT:    addq %r11, %r11
-; CHECK-NEXT:    addq %rdi, %r11
+; CHECK-NEXT:    leaq (%rsi,%rdx), %rbx
+; CHECK-NEXT:    leaq (%rdi,%rbx), %r11
+; CHECK-NEXT:    addq %rbx, %r11
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %r10, %rcx
 ; CHECK-NEXT:    addq %rcx, %r8
 ; CHECK-NEXT:    addq %rdi, %r11
 ; CHECK-NEXT:    addq %rcx, %r11
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%r10,%r9), %rcx
 ; CHECK-NEXT:    addq %r8, %rcx
 ; CHECK-NEXT:    addq %r12, %rbx
 ; CHECK-NEXT:    addq %rcx, %rbx
-; CHECK-NEXT:    leaq (%rdi,%rsi), %r14
-; CHECK-NEXT:    addq %r14, %r14
-; CHECK-NEXT:    addq %r11, %r14
+; CHECK-NEXT:    leaq (%rdi,%rsi), %rax
+; CHECK-NEXT:    leaq (%r11,%rax), %r14
+; CHECK-NEXT:    addq %rax, %r14
 ; CHECK-NEXT:    movq X(%rip), %rax
 ; CHECK-NEXT:    addq %r8, %rbx
 ; CHECK-NEXT:    addq %rbx, %rdx
 ; CHECK-NEXT:    addq %r11, %r14
 ; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    addq %rbx, %r14
 ; CHECK-NEXT:    leaq (%r8,%r10), %rbx
 ; CHECK-NEXT:    addq %rdx, %rbx
 ; CHECK-NEXT:    addq %r9, %rax
 ; CHECK-NEXT:    addq %rbx, %rax
-; CHECK-NEXT:    leaq (%r11,%rdi), %r9
-; CHECK-NEXT:    addq %r9, %r9
-; CHECK-NEXT:    addq %r14, %r9
+; CHECK-NEXT:    leaq (%r11,%rdi), %rbx
+; CHECK-NEXT:    leaq (%r14,%rbx), %r9
+; CHECK-NEXT:    addq %rbx, %r9
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %rdx, %rax
 ; CHECK-NEXT:    addq %rax, %rsi
 ; CHECK-NEXT:    addq %r14, %r9
 ; CHECK-NEXT:    addq %rax, %r9
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%rdx,%r8), %rax
 ; CHECK-NEXT:    addq %rsi, %rax
 ; CHECK-NEXT:    addq %r10, %rbx
 ; CHECK-NEXT:    addq %rax, %rbx
-; CHECK-NEXT:    leaq (%r14,%r11), %r10
-; CHECK-NEXT:    addq %r10, %r10
-; CHECK-NEXT:    addq %r9, %r10
+; CHECK-NEXT:    leaq (%r14,%r11), %rax
+; CHECK-NEXT:    leaq (%r9,%rax), %r10
+; CHECK-NEXT:    addq %rax, %r10
 ; CHECK-NEXT:    movq X(%rip), %rax
 ; CHECK-NEXT:    addq %rsi, %rbx
 ; CHECK-NEXT:    addq %rbx, %rdi
 ; CHECK-NEXT:    addq %r9, %r10
 ; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    addq %rbx, %r10
 ; CHECK-NEXT:    leaq (%rsi,%rdx), %rbx
 ; CHECK-NEXT:    addq %rdi, %rbx
 ; CHECK-NEXT:    addq %r8, %rax
 ; CHECK-NEXT:    addq %rbx, %rax
-; CHECK-NEXT:    leaq (%r9,%r14), %r8
-; CHECK-NEXT:    addq %r8, %r8
-; CHECK-NEXT:    addq %r10, %r8
+; CHECK-NEXT:    leaq (%r9,%r14), %rbx
+; CHECK-NEXT:    leaq (%r10,%rbx), %r8
+; CHECK-NEXT:    addq %rbx, %r8
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %rdi, %rax
 ; CHECK-NEXT:    addq %rax, %r11
 ; CHECK-NEXT:    addq %r10, %r8
 ; CHECK-NEXT:    addq %rax, %r8
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%rdi,%rsi), %rax
 ; CHECK-NEXT:    addq %r11, %rax
 ; CHECK-NEXT:    addq %rdx, %rbx
 ; CHECK-NEXT:    addq %rax, %rbx
-; CHECK-NEXT:    leaq (%r10,%r9), %r15
-; CHECK-NEXT:    addq %r15, %r15
-; CHECK-NEXT:    addq %r8, %r15
+; CHECK-NEXT:    leaq (%r10,%r9), %rax
+; CHECK-NEXT:    leaq (%r8,%rax), %r15
+; CHECK-NEXT:    addq %rax, %r15
 ; CHECK-NEXT:    movq X(%rip), %rax
 ; CHECK-NEXT:    addq %r11, %rbx
 ; CHECK-NEXT:    addq %rbx, %r14
 ; CHECK-NEXT:    addq %r8, %r15
 ; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    addq %rbx, %r15
 ; CHECK-NEXT:    leaq (%r11,%rdi), %rbx
 ; CHECK-NEXT:    addq %r14, %rbx
 ; CHECK-NEXT:    addq %rsi, %rax
 ; CHECK-NEXT:    addq %rbx, %rax
-; CHECK-NEXT:    leaq (%r8,%r10), %rsi
-; CHECK-NEXT:    addq %rsi, %rsi
-; CHECK-NEXT:    addq %r15, %rsi
+; CHECK-NEXT:    leaq (%r8,%r10), %rbx
+; CHECK-NEXT:    leaq (%r15,%rbx), %rsi
+; CHECK-NEXT:    addq %rbx, %rsi
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %r14, %rax
 ; CHECK-NEXT:    addq %rax, %r9
 ; CHECK-NEXT:    addq %r15, %rsi
 ; CHECK-NEXT:    addq %rax, %rsi
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%r14,%r11), %rax
 ; CHECK-NEXT:    addq %r9, %rax
 ; CHECK-NEXT:    addq %rdi, %rbx
 ; CHECK-NEXT:    addq %rax, %rbx
-; CHECK-NEXT:    leaq (%r15,%r8), %r12
-; CHECK-NEXT:    addq %r12, %r12
-; CHECK-NEXT:    addq %rsi, %r12
+; CHECK-NEXT:    leaq (%r15,%r8), %rax
+; CHECK-NEXT:    leaq (%rsi,%rax), %r12
+; CHECK-NEXT:    addq %rax, %r12
 ; CHECK-NEXT:    movq X(%rip), %rcx
 ; CHECK-NEXT:    addq %r9, %rbx
 ; CHECK-NEXT:    addq %rbx, %r10
 ; CHECK-NEXT:    addq %rsi, %r12
 ; CHECK-NEXT:    bswapq %rcx
 ; CHECK-NEXT:    addq %rbx, %r12
 ; CHECK-NEXT:    leaq (%r9,%r14), %rax
 ; CHECK-NEXT:    addq %r10, %rax
 ; CHECK-NEXT:    addq %r11, %rcx
 ; CHECK-NEXT:    addq %rax, %rcx
-; CHECK-NEXT:    leaq (%rsi,%r15), %rax
-; CHECK-NEXT:    addq %rax, %rax
-; CHECK-NEXT:    addq %r12, %rax
+; CHECK-NEXT:    leaq (%rsi,%r15), %rbx
+; CHECK-NEXT:    leaq (%r12,%rbx), %rax
+; CHECK-NEXT:    addq %rbx, %rax
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %r10, %rcx
 ; CHECK-NEXT:    addq %rcx, %r8
 ; CHECK-NEXT:    addq %r12, %rax
 ; CHECK-NEXT:    addq %rcx, %rax
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%r10,%r9), %rcx
 ; CHECK-NEXT:    addq %r8, %rcx
 ; CHECK-NEXT:    addq %r14, %rbx
 ; CHECK-NEXT:    addq %rcx, %rbx
-; CHECK-NEXT:    leaq (%r12,%rsi), %rcx
-; CHECK-NEXT:    addq %rcx, %rcx
-; CHECK-NEXT:    addq %rax, %rcx
+; CHECK-NEXT:    leaq (%r12,%rsi), %rdx
+; CHECK-NEXT:    leaq (%rax,%rdx), %rcx
+; CHECK-NEXT:    addq %rdx, %rcx
 ; CHECK-NEXT:    movq X(%rip), %rdx
 ; CHECK-NEXT:    addq %r8, %rbx
 ; CHECK-NEXT:    addq %rbx, %r15
 ; CHECK-NEXT:    addq %rax, %rcx
 ; CHECK-NEXT:    bswapq %rdx
 ; CHECK-NEXT:    addq %rbx, %rcx
 ; CHECK-NEXT:    leaq (%r8,%r10), %rbx
 ; CHECK-NEXT:    addq %r15, %rbx
 ; CHECK-NEXT:    addq %r9, %rdx
 ; CHECK-NEXT:    addq %rbx, %rdx
-; CHECK-NEXT:    leaq (%rax,%r12), %rbx
-; CHECK-NEXT:    addq %rbx, %rbx
-; CHECK-NEXT:    addq %rcx, %rbx
+; CHECK-NEXT:    leaq (%rax,%r12), %r9
+; CHECK-NEXT:    leaq (%rcx,%r9), %rbx
+; CHECK-NEXT:    addq %r9, %rbx
 ; CHECK-NEXT:    addq %r15, %rdx
 ; CHECK-NEXT:    addq %rdx, %rsi
 ; CHECK-NEXT:    addq %rcx, %rbx
 ; CHECK-NEXT:    addq %rdx, %rbx
 ; CHECK-NEXT:    movq X(%rip), %rdx
 ; CHECK-NEXT:    bswapq %rdx
 ; CHECK-NEXT:    addq %r10, %rdx
 ; CHECK-NEXT:    leaq (%r15,%r8), %rdi
 ; CHECK-NEXT:    addq %rsi, %rdi
 ; CHECK-NEXT:    addq %rdi, %rdx
 ; CHECK-NEXT:    addq %rax, %rcx
-; CHECK-NEXT:    addq %rcx, %rcx
-; CHECK-NEXT:    addq %rbx, %rcx
-; CHECK-NEXT:    addq %rbx, %rcx
+; CHECK-NEXT:    leaq (%rbx,%rcx), %rdi
+; CHECK-NEXT:    addq %rcx, %rdi
+; CHECK-NEXT:    addq %rbx, %rdi
 ; CHECK-NEXT:    addq %rsi, %rdx
 ; CHECK-NEXT:    addq %rdx, %r12
-; CHECK-NEXT:    addq %rdx, %rcx
+; CHECK-NEXT:    addq %rdx, %rdi
 ; CHECK-NEXT:    addq %r15, %rsi
 ; CHECK-NEXT:    movq X(%rip), %rax
 ; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    movq %rax, X(%rip)
 ; CHECK-NEXT:    addq %r8, %rax
 ; CHECK-NEXT:    addq %r12, %rsi
 ; CHECK-NEXT:    addq %rsi, %rax
 ; CHECK-NEXT:    addq %r12, %rax
-; CHECK-NEXT:    addq %rcx, %rax
+; CHECK-NEXT:    addq %rdi, %rax
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    popq %r12
 ; CHECK-NEXT:    popq %r14
 ; CHECK-NEXT:    popq %r15
 ; CHECK-NEXT:    retq
   %tmp = load volatile i64, i64* @X    ; <i64> [#uses=7]
   %tmp1 = load volatile i64, i64* @X    ; <i64> [#uses=5]
   %tmp2 = load volatile i64, i64* @X    ; <i64> [#uses=3]

llvm/test/CodeGen/X86/lea-opt2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
 
 ; This file tests following optimization
 ;
 ;        leal    (%rdx,%rax), %esi
 ;        subl    %esi, %ecx
 ;
 ; can be transformed to
 ;
 ;        subl    %edx, %ecx
 ;        subl    %eax, %ecx
 
+; TODO: replace lea with sub.
 ; C - (A + B)   -->    C - A - B
 define i32 @test1(i32* %p, i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $edx killed $edx def $rdx
 ; CHECK-NEXT:    movl %esi, %eax
-; CHECK-NEXT:    subl %edx, %ecx
-; CHECK-NEXT:    subl %eax, %ecx
+; CHECK-NEXT:    leal (%rdx,%rax), %esi
+; CHECK-NEXT:    subl %esi, %ecx
 ; CHECK-NEXT:    movl %ecx, (%rdi)
 ; CHECK-NEXT:    subl %edx, %eax
 ; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
 ; CHECK-NEXT:    retq
 entry:
   %0 = add i32 %b, %a
   %sub = sub i32 %c, %0
   store i32 %sub, i32* %p, align 4
   %sub1 = sub i32 %a, %b
   ret i32 %sub1
 }
 
+; TODO: replace lea with add.
 ; (A + B) + C   -->    C + A + B
 define i32 @test2(i32* %p, i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $edx killed $edx def $rdx
 ; CHECK-NEXT:    movl %esi, %eax
-; CHECK-NEXT:    addl %eax, %ecx
-; CHECK-NEXT:    addl %edx, %ecx
-; CHECK-NEXT:    movl %ecx, (%rdi)
+; CHECK-NEXT:    leal (%rax,%rdx), %esi
+; CHECK-NEXT:    addl %ecx, %esi
+; CHECK-NEXT:    movl %esi, (%rdi)
 ; CHECK-NEXT:    subl %edx, %eax
 ; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
 ; CHECK-NEXT:    retq
 entry:
   %0 = add i32 %a, %b
   %1 = add i32 %c, %0
   store i32 %1, i32* %p, align 4
   %sub1 = sub i32 %a, %b
   ret i32 %sub1
 }
 
+; TODO: replace lea with add.
 ; C + (A + B)   -->    C + A + B
 define i32 @test3(i32* %p, i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $edx killed $edx def $rdx
 ; CHECK-NEXT:    movl %esi, %eax
-; CHECK-NEXT:    addl %eax, %ecx
-; CHECK-NEXT:    addl %edx, %ecx
-; CHECK-NEXT:    movl %ecx, (%rdi)
+; CHECK-NEXT:    leal (%rax,%rdx), %esi
+; CHECK-NEXT:    addl %ecx, %esi
+; CHECK-NEXT:    movl %esi, (%rdi)
 ; CHECK-NEXT:    subl %edx, %eax
 ; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
 ; CHECK-NEXT:    retq
 entry:
   %0 = add i32 %a, %b
   %1 = add i32 %0, %c
   store i32 %1, i32* %p, align 4
   %sub1 = sub i32 %a, %b

 entry:
   %0 = add i32 %b, %a
   %sub = sub i32 %0, %c
   store i32 %sub, i32* %p, align 4
   %sub1 = sub i32 %a, %b
   ret i32 %sub1
 }
 
+; TODO: replace lea with sub.
 define i64 @test5(i64* %p, i64 %a, i64 %b, i64 %c) {
 ; CHECK-LABEL: test5:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movq (%rdi), %rax
-; CHECK-NEXT:    subq %rdx, %rcx
-; CHECK-NEXT:    subq %rax, %rcx
+; CHECK-NEXT:    leaq (%rdx,%rax), %rsi
+; CHECK-NEXT:    subq %rsi, %rcx
 ; CHECK-NEXT:    movq %rcx, (%rdi)
 ; CHECK-NEXT:    subq %rdx, %rax
 ; CHECK-NEXT:    retq
 entry:
   %ld = load i64, i64* %p, align 8
   %0 = add i64 %b, %ld
   %sub = sub i64 %c, %0
   store i64 %sub, i64* %p, align 8
   %sub1 = sub i64 %ld, %b
   ret i64 %sub1
 }
 
+; TODO: replace lea with add.
 define i64 @test6(i64* %p, i64 %a, i64 %b, i64 %c) {
 ; CHECK-LABEL: test6:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movq (%rdi), %rax
-; CHECK-NEXT:    addq %rdx, %rcx
-; CHECK-NEXT:    addq %rax, %rcx
-; CHECK-NEXT:    movq %rcx, (%rdi)
+; CHECK-NEXT:    leaq (%rdx,%rax), %rsi
+; CHECK-NEXT:    addq %rcx, %rsi
+; CHECK-NEXT:    movq %rsi, (%rdi)
 ; CHECK-NEXT:    subq %rdx, %rax
 ; CHECK-NEXT:    retq
 entry:
   %ld = load i64, i64* %p, align 8
   %0 = add i64 %b, %ld
   %1 = add i64 %0, %c
   store i64 %1, i64* %p, align 8
   %sub1 = sub i64 %ld, %b
   ret i64 %sub1
 }
 
+; TODO: replace lea with add.
 define i64 @test7(i64* %p, i64 %a, i64 %b, i64 %c) {
 ; CHECK-LABEL: test7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movq (%rdi), %rax
-; CHECK-NEXT:    addq %rdx, %rcx
-; CHECK-NEXT:    addq %rax, %rcx
-; CHECK-NEXT:    movq %rcx, (%rdi)
+; CHECK-NEXT:    leaq (%rdx,%rax), %rsi
+; CHECK-NEXT:    addq %rcx, %rsi
+; CHECK-NEXT:    movq %rsi, (%rdi)
 ; CHECK-NEXT:    subq %rdx, %rax
 ; CHECK-NEXT:    retq
 entry:
   %ld = load i64, i64* %p, align 8
   %0 = add i64 %b, %ld
   %1 = add i64 %c, %0
   store i64 %1, i64* %p, align 8
   %sub1 = sub i64 %ld, %b
   ret i64 %sub1
 }
 
-; The sub instruction generated flags is used by following branch,
-; so it should not be transformed.
-define i64 @test8(i64* %p, i64 %a, i64 %b, i64 %c) {
-; CHECK-LABEL: test8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movq (%rdi), %rax
-; CHECK-NEXT:    leaq (%rdx,%rax), %rsi
-; CHECK-NEXT:    subq %rsi, %rcx
-; CHECK-NEXT:    ja .LBB7_2
-; CHECK-NEXT:  # %bb.1: # %then
-; CHECK-NEXT:    movq %rcx, (%rdi)
-; CHECK-NEXT:    subq %rdx, %rax
-; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB7_2: # %else
-; CHECK-NEXT:    movq $0, (%rdi)
-; CHECK-NEXT:    subq %rdx, %rax
-; CHECK-NEXT:    retq
-entry:
-  %ld = load i64, i64* %p, align 8
-  %0 = add i64 %b, %ld
-  %sub = sub i64 %c, %0
-  %cond = icmp ule i64 %c, %0
-  br i1 %cond, label %then, label %else
-
-then:
-  store i64 %sub, i64* %p, align 8
-  br label %endif
-
-else:
-  store i64 0, i64* %p, align 8
-  br label %endif
-
-endif:
-  %sub1 = sub i64 %ld, %b
-  ret i64 %sub1
-}
-
-; PR50615
-; The sub register usage of lea dest should block the transformation.
-define void @test9(i64 %p, i64 %s) {
-; CHECK-LABEL: test9:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    leaq (%rsi,%rdi), %rax
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    testl $4095, %eax # imm = 0xFFF
-; CHECK-NEXT:    setne %cl
-; CHECK-NEXT:    shlq $12, %rcx
-; CHECK-NEXT:    addq %rax, %rcx
-; CHECK-NEXT:    andq $-4096, %rcx # imm = 0xF000
-; CHECK-NEXT:    addq %rcx, %rdi
-; CHECK-NEXT:    jmp bar@PLT # TAILCALL
-entry:
-  %add = add i64 %s, %p
-  %rem = and i64 %add, 4095
-  %cmp.not = icmp eq i64 %rem, 0
-  %add18 = select i1 %cmp.not, i64 0, i64 4096
-  %div9 = add i64 %add18, %add
-  %mul = and i64 %div9, -4096
-  %add2 = add i64 %mul, %p
-  tail call void @bar(i64 %add2, i64 %s)
-  ret void
-}
-
-declare void @bar(i64, i64)
-

llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll

 ; X86-NEXT:    kmovw %k0, %edi
 ; X86-NEXT:    addl %edi, %eax
 ; X86-NEXT:    kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k2 # 2-byte Reload
 ; X86-NEXT:    kmovw {{[-0-9]+}}(%e{{[sb]}}p), %k3 # 2-byte Reload
 ; X86-NEXT:    kmovw %k2, %edi
 ; X86-NEXT:    addl %ecx, %edx
 ; X86-NEXT:    kmovw %k1, %ecx
 ; X86-NEXT:    addl %edi, %ecx
-; X86-NEXT:    addl %ecx, %eax
-; X86-NEXT:    addl %edx, %eax
-; X86-NEXT:    movw %ax, (%esi)
+; X86-NEXT:    addl %eax, %ecx
+; X86-NEXT:    addl %edx, %ecx
+; X86-NEXT:    movw %cx, (%esi)
 ; X86-NEXT:    leal -8(%ebp), %esp
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    popl %edi
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test:
 ; X64:       # %bb.0: # %entry

 ; X64-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
 ; X64-NEXT:    kmovw %k0, %esi
 ; X64-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 2-byte Reload
 ; X64-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 # 2-byte Reload
 ; X64-NEXT:    kmovw %k0, %edi
 ; X64-NEXT:    kmovw %k1, %ebx
 ; X64-NEXT:    addl %edi, %eax
 ; X64-NEXT:    addl %ecx, %edx
-; X64-NEXT:    addl %ebx, %eax
-; X64-NEXT:    addl %esi, %eax
-; X64-NEXT:    addl %edx, %eax
-; X64-NEXT:    movw %ax, (%r14)
+; X64-NEXT:    leal (%rbx,%rsi), %ecx
+; X64-NEXT:    addl %eax, %ecx
+; X64-NEXT:    addl %edx, %ecx
+; X64-NEXT:    movw %cx, (%r14)
 ; X64-NEXT:    leaq -16(%rbp), %rsp
 ; X64-NEXT:    popq %rbx
 ; X64-NEXT:    popq %r14
 ; X64-NEXT:    popq %rbp
 ; X64-NEXT:    retq
 entry:
   %0 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a0, <16 x i32> %b0)
   %1 = call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %a1, <16 x i32> %b1)

llvm/utils/lit/lit/discovery.py

def search1(path):
         # translation of configuration paths.  Specifically, this parameter
         # can be set to a dictionary that the discovery process will consult
         # when it finds a configuration it is about to load.  If the given
         # path is in the map, the value of that key is a path to the
         # configuration to load instead.
         config_map = litConfig.params.get('config_map')
         if config_map:
             cfgpath = os.path.realpath(cfgpath)
-            cfgpath = os.path.normcase(cfgpath)
-            target = config_map.get(cfgpath)
+            target = config_map.get(os.path.normcase(cfgpath))
             if target:
                 cfgpath = target
 
         # We found a test suite, create a new config for it and load it.
         if litConfig.debug:
             litConfig.note('loading suite config %r' % cfgpath)
 
         cfg = TestingConfig.fromdefaults(litConfig)