Add missing AArch64 data synchronization barrier (dsb) to __clear_cache

[srhines]

Summary

https://developer.arm.com/documentation/den0024/a/Caches/Cache-maintenance
covers how to properly clear caches on AArch64, and the builtin
implementation was missing a dsb ish after clearing the icache for the
selected range.

[kristof.beyls]

Thank you Stephen; LGTM!

[pcc]

Do we still need the DSB on line 119?

[kristof.beyls]

In D104094#2817317, @pcc wrote:

Do we still need the DSB on line 119?

I believe so.
Quoting from the ArmARM (ARM DDI 0487G.a), "B2.3.8 Ordering of instruction fetches":

Ordering of instruction fetches
For two memory locations A and B, if A has been written to and been made coherent with the instruction fetches of
the shareability domain, before an update to B by an observer in the same shareability domain, then the instruction
stream of each observer in the shareability domain will not see the updated value of B without also seeing the
updated value of A.
A write has been made coherent with an instruction fetch of a shareability domain when:

CTR_EL0.{DIC, IDC} == {0, 0}

The location written to has been cleaned to the Point of unification (PoU) from the data cache, and
that clean is complete for the shareability domain. Subsequently the location has been invalidated
to the Point of unification (PoU) from the instruction cache, and that invalidation is complete for
the shareability domain.

The last paragraph ("..., and that clean is complete for the shareability domain. Subsequently...") implies that dsb on line 119 is needed.

compiler-rt/lib/builtins/clear_cache.c

#elif defined(__aarch64__) && !defined(__APPLE__)
   // If CTR_EL0.DIC is set, instruction cache invalidation to the point of
   // unification is not required for instruction to data coherence.
   if (((ctr_el0 >> 29) & 0x1) == 0x0) {
     const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
     for (addr = xstart & ~(icache_line_size - 1); addr < xend;
          addr += icache_line_size)
       __asm __volatile("ic ivau, %0" ::"r"(addr));
   }
+  __asm __volatile("dsb ish");
   __asm __volatile("isb sy");
 #elif defined(__powerpc64__)
   const size_t line_size = 32;
   const size_t len = (uintptr_t)end - (uintptr_t)start;
 
   const uintptr_t mask = ~(line_size - 1);
   const uintptr_t start_line = ((uintptr_t)start) & mask;
   const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask;