[mlir][SPIRV] Add lowering for math.log1p operation to SPIR-V dialect.

[antiagainst]

mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp

331

This is for sure == 1?

mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp

if (SPIRVOp::template hasTrait<OpTrait::spirv::UnsignedOp>() &&
       return operation.emitError(
           "bitwidth emulation is not implemented yet on unsigned op");
     }
     rewriter.template replaceOpWithNewOp<SPIRVOp>(operation, dstType, operands);
     return success();
   }
 };
 
+/// Converts math.log1p to SPIR-V ops.
+///
+/// SPIR-V does not have a direct operations for log(1+x). Explicitly lower to
+/// these operations.
+class Log1pOpPattern final : public OpConversionPattern<math::Log1pOp> {
+public:
+  using OpConversionPattern<math::Log1pOp>::OpConversionPattern;
+
+  LogicalResult
+  matchAndRewrite(math::Log1pOp operation, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const override {
+    assert(operands.size() == 1);
+    Location loc = operation.getLoc();
+    auto type =
+        this->getTypeConverter()->convertType(operation.operand().getType());
+    auto one = spirv::ConstantOp::getOne(type, operation.getLoc(), rewriter);
+    auto onePlus = rewriter.create<spirv::FAddOp>(loc, one, operands[0]);
+    rewriter.replaceOpWithNewOp<spirv::GLSLLogOp>(operation, type, onePlus);
+    return success();
+  }
+};
+
 /// Converts std.remi_signed to SPIR-V ops.
 ///
 /// This cannot be merged into the template unary/binary pattern due to
 /// Vulkan restrictions over spv.SRem and spv.SMod.
 class SignedRemIOpPattern final : public OpConversionPattern<SignedRemIOp> {
 public:
   using OpConversionPattern<SignedRemIOp>::OpConversionPattern;
 
patterns.add<
       UnaryAndBinaryOpPattern<SignedDivIOp, spirv::SDivOp>,
       UnaryAndBinaryOpPattern<SignedShiftRightOp,
                               spirv::ShiftRightArithmeticOp>,
       UnaryAndBinaryOpPattern<SubIOp, spirv::ISubOp>,
       UnaryAndBinaryOpPattern<SubFOp, spirv::FSubOp>,
       UnaryAndBinaryOpPattern<UnsignedDivIOp, spirv::UDivOp>,
       UnaryAndBinaryOpPattern<UnsignedRemIOp, spirv::UModOp>,
       UnaryAndBinaryOpPattern<UnsignedShiftRightOp, spirv::ShiftRightLogicalOp>,
-      SignedRemIOpPattern, XOrOpPattern, BoolXOrOpPattern,
+      Log1pOpPattern, SignedRemIOpPattern, XOrOpPattern, BoolXOrOpPattern,
 
       // Comparison patterns
       BoolCmpIOpPattern, CmpFOpPattern, CmpFOpNanNonePattern, CmpIOpPattern,
 
       // Constant patterns
       ConstantCompositeOpPattern, ConstantScalarOpPattern,
 
       // Memory patterns

mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir

func @float32_unary_scalar(%arg0: f32) {
   // CHECK: spv.GLSL.Ceil %{{.*}}: f32
   %1 = ceilf %arg0 : f32
   // CHECK: spv.GLSL.Cos %{{.*}}: f32
   %2 = math.cos %arg0 : f32
   // CHECK: spv.GLSL.Exp %{{.*}}: f32
   %3 = math.exp %arg0 : f32
   // CHECK: spv.GLSL.Log %{{.*}}: f32
   %4 = math.log %arg0 : f32
+  // CHECK: %[[ONE:.+]] = spv.Constant 1.000000e+00 : f32
+  // CHECK: %[[ADDONE:.+]] = spv.FAdd %[[ONE]], %{{.+}}
+  // CHECK: spv.GLSL.Log %[[ADDONE]]
+  %40 = math.log1p %arg0 : f32
   // CHECK: spv.FNegate %{{.*}}: f32
   %5 = negf %arg0 : f32
   // CHECK: spv.GLSL.InverseSqrt %{{.*}}: f32
   %6 = math.rsqrt %arg0 : f32
   // CHECK: spv.GLSL.Sqrt %{{.*}}: f32
   %7 = math.sqrt %arg0 : f32
   // CHECK: spv.GLSL.Tanh %{{.*}}: f32
   %8 = math.tanh %arg0 : f32