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Differential D101932

[GlobalISel] Don't form zero/sign extending loads for atomics
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Authored by aemerson on May 5 2021, 11:40 AM.

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Reviewers
paquette
Commits
rG808bc11d9e1a: [GlobalISel] Don't form zero/sign extending loads for atomics.
Summary

For importing patterns, we only support matching G_LOAD, not G_ZEXTLOAD or G_SEXTLOAD.

Diff Detail

Event Timeline

aemerson created this revision.May 5 2021, 11:40 AM
Herald added subscribers: jfb, hiraditya, rovka. · View Herald TranscriptMay 5 2021, 11:40 AM
aemerson requested review of this revision.May 5 2021, 11:40 AM
Harbormaster completed remote builds in B102807: Diff 343126.May 5 2021, 12:36 PM
aemerson updated this revision to Diff 343540.May 6 2021, 5:05 PM

Hadn't rerun test since an update. Move check to before the LI check so that it runs unconditionally.

Harbormaster completed remote builds in B103093: Diff 343540.May 6 2021, 6:01 PM
paquette accepted this revision.May 7 2021, 12:05 PM

LGTM

This revision is now accepted and ready to land.May 7 2021, 12:05 PM
Closed by commit rG808bc11d9e1a: [GlobalISel] Don't form zero/sign extending loads for atomics. (authored by aemerson). · Explain WhyMay 7 2021, 5:00 PM
This revision was automatically updated to reflect the committed changes.
aemerson added a commit: rG808bc11d9e1a: [GlobalISel] Don't form zero/sign extending loads for atomics..

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
5 lines
test/
CodeGen/
AArch64/
GlobalISel/
412 lines

Diff 343786

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 476 Lines • ▼ Show 20 Lines unsigned PreferredOpcode = MI.getOpcode() == TargetOpcode::G_LOAD
: MI.getOpcode() == TargetOpcode::G_SEXTLOAD : MI.getOpcode() == TargetOpcode::G_SEXTLOAD
? TargetOpcode::G_SEXT ? TargetOpcode::G_SEXT
: TargetOpcode::G_ZEXT; : TargetOpcode::G_ZEXT;
Preferred = {LLT(), PreferredOpcode, nullptr}; Preferred = {LLT(), PreferredOpcode, nullptr};
for (auto &UseMI : MRI.use_nodbg_instructions(LoadValue.getReg())) { for (auto &UseMI : MRI.use_nodbg_instructions(LoadValue.getReg())) {
if (UseMI.getOpcode() == TargetOpcode::G_SEXT || if (UseMI.getOpcode() == TargetOpcode::G_SEXT ||
UseMI.getOpcode() == TargetOpcode::G_ZEXT || UseMI.getOpcode() == TargetOpcode::G_ZEXT ||
(UseMI.getOpcode() == TargetOpcode::G_ANYEXT)) { (UseMI.getOpcode() == TargetOpcode::G_ANYEXT)) {
const auto &MMO = **MI.memoperands_begin();
// For atomics, only form anyextending loads.
if (MMO.isAtomic() && UseMI.getOpcode() != TargetOpcode::G_ANYEXT)
continue;
// Check for legality. // Check for legality.
if (LI) { if (LI) {
LegalityQuery::MemDesc MMDesc; LegalityQuery::MemDesc MMDesc;
const auto &MMO = **MI.memoperands_begin();
MMDesc.SizeInBits = MMO.getSizeInBits(); MMDesc.SizeInBits = MMO.getSizeInBits();
MMDesc.AlignInBits = MMO.getAlign().value() * 8; MMDesc.AlignInBits = MMO.getAlign().value() * 8;
MMDesc.Ordering = MMO.getOrdering(); MMDesc.Ordering = MMO.getOrdering();
LLT UseTy = MRI.getType(UseMI.getOperand(0).getReg()); LLT UseTy = MRI.getType(UseMI.getOperand(0).getReg());
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
if (LI->getAction({MI.getOpcode(), {UseTy, SrcTy}, {MMDesc}}).Action != if (LI->getAction({MI.getOpcode(), {UseTy, SrcTy}, {MMDesc}}).Action !=
LegalizeActions::Legal) LegalizeActions::Legal)
continue; continue;
▲ Show 20 Lines • Show All 3,438 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir

# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
define void @test_anyext(i8* %addr) {
entry:
ret void
}
define void @test_anyext_with_copy(i8* %addr) {
entry:
ret void
}
define void @test_signext(i8* %addr) {
entry:
ret void
}
define void @test_zeroext(i8* %addr) {
entry:
ret void
}
define void @test_2anyext(i8* %addr) {
entry:
ret void
}
define void @test_1anyext_1signext(i8* %addr) {
entry:
ret void
}
define void @test_1xor_1signext(i8* %addr) {
entry:
ret void
}
define void @test_1anyext_1zeroext(i8* %addr) {
entry:
ret void
}
define void @test_1signext_1zeroext(i8* %addr) {
entry:
ret void
}
define void @test_1anyext64_1signext32(i8* %addr) {
entry:
ret void
}
define void @test_1anyext32_1signext64(i8* %addr) {
entry:
ret void
}
define void @test_2anyext32_1signext64(i8* %addr) {
entry:
ret void
}
define void @test_multiblock_anyext(i8* %addr) {
entry:
ret void
}
define void @test_multiblock_signext(i8* %addr) {
entry:
ret void
}
define void @test_multiblock_zeroext(i8* %addr) {
entry:
ret void
}
define void @test_multiblock_2anyext(i8* %addr) {
entry:
ret void
}
define void @test_multiblock_1anyext64_1signext32(i8* %addr) {
entry:
ret void
}
define void @test_multiblock_1anyext32_1signext64(i8* %addr) {
entry:
ret void
}
define void @test_multiblock_2anyext32_1signext64(i8* %addr) {
entry:
ret void
}
...
--- ---
name: test_anyext name: test_anyext
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_anyext ; CHECK-LABEL: name: test_anyext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: $w0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$w0 = COPY %2 $w0 = COPY %2
... ...
--- ---
name: test_anyext_with_copy name: test_anyext_with_copy
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_anyext ; CHECK-LABEL: name: test_anyext_with_copy
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: $w0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s8) = COPY %1 %2:_(s8) = COPY %1
%3:_(s32) = G_ANYEXT %1 %3:_(s32) = G_ANYEXT %1
$w0 = COPY %3 $w0 = COPY %3
... ...
--- ---
name: test_signext name: test_signext
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_signext ; CHECK-LABEL: name: test_signext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
$w0 = COPY %2 $w0 = COPY %2
... ...
--- ---
name: test_zeroext name: test_zeroext
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_zeroext ; CHECK-LABEL: name: test_zeroext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ZEXT %1 %2:_(s32) = G_ZEXT %1
$w0 = COPY %2 $w0 = COPY %2
... ...
--- ---
name: test_2anyext name: test_2anyext
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_2anyext ; CHECK-LABEL: name: test_2anyext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: $w0 = COPY [[LOAD]](s32)
; CHECK: $w1 = COPY [[T1]](s32) ; CHECK: $w1 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
%3:_(s32) = G_ANYEXT %1 %3:_(s32) = G_ANYEXT %1
$w0 = COPY %2 $w0 = COPY %2
$w1 = COPY %3 $w1 = COPY %3
... ...
--- ---
name: test_1anyext_1signext name: test_1anyext_1signext
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_1anyext_1signext ; CHECK-LABEL: name: test_1anyext_1signext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
; CHECK: $w1 = COPY [[T1]](s32) ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
%3:_(s32) = G_SEXT %1 %3:_(s32) = G_SEXT %1
$w0 = COPY %2 $w0 = COPY %2
$w1 = COPY %3 $w1 = COPY %3
... ...
--- ---
name: test_1xor_1signext name: test_1xor_1signext
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_1xor_1signext ; CHECK-LABEL: name: test_1xor_1signext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s32)
; CHECK: [[T3:%[0-9]+]]:_(s8) = G_XOR [[T2]], {{%[0-9]+}} ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
; CHECK: [[T4:%[0-9]+]]:_(s32) = G_ANYEXT [[T3]] ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[C]]
; CHECK: $w0 = COPY [[T4]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s8)
; CHECK: $w1 = COPY [[T1]](s32) ; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s8) = G_CONSTANT i8 -1 %2:_(s8) = G_CONSTANT i8 -1
%3:_(s8) = G_XOR %1, %2 %3:_(s8) = G_XOR %1, %2
%5:_(s32) = G_ANYEXT %3 %5:_(s32) = G_ANYEXT %3
%6:_(s32) = G_SEXT %1 %6:_(s32) = G_SEXT %1
$w0 = COPY %5 $w0 = COPY %5
$w1 = COPY %6 $w1 = COPY %6
... ...
--- ---
name: test_1anyext_1zeroext name: test_1anyext_1zeroext
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_1anyext_1zeroext ; CHECK-LABEL: name: test_1anyext_1zeroext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
; CHECK: $w1 = COPY [[T1]](s32) ; CHECK: $w1 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
%3:_(s32) = G_ZEXT %1 %3:_(s32) = G_ZEXT %1
$w0 = COPY %2 $w0 = COPY %2
$w1 = COPY %3 $w1 = COPY %3
... ...
--- ---
name: test_1signext_1zeroext name: test_1signext_1zeroext
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_1signext_1zeroext ; CHECK-LABEL: name: test_1signext_1zeroext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s32)
; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ZEXT [[T2]] ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
; CHECK: $w0 = COPY [[T3]](s32) ; CHECK: $w0 = COPY [[ZEXT]](s32)
; CHECK: $w1 = COPY [[T1]](s32) ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ZEXT %1 %2:_(s32) = G_ZEXT %1
%3:_(s32) = G_SEXT %1 %3:_(s32) = G_SEXT %1
$w0 = COPY %2 $w0 = COPY %2
$w1 = COPY %3 $w1 = COPY %3
... ...
--- ---
name: test_1anyext64_1signext32 name: test_1anyext64_1signext32
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_1anyext64_1signext32 ; CHECK-LABEL: name: test_1anyext64_1signext32
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK-NOT: [[T1]] ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
; CHECK: [[T2:%[0-9]+]]:_(s64) = G_ANYEXT [[T1]] ; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK-NOT: [[T1]] ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
; CHECK: $x0 = COPY [[T2]](s64)
; CHECK: $w1 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s64) = G_ANYEXT %1 %2:_(s64) = G_ANYEXT %1
%3:_(s32) = G_SEXT %1 %3:_(s32) = G_SEXT %1
$x0 = COPY %2 $x0 = COPY %2
$w1 = COPY %3 $w1 = COPY %3
... ...
--- ---
name: test_1anyext32_1signext64 name: test_1anyext32_1signext64
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_1anyext32_1signext64 ; CHECK-LABEL: name: test_1anyext32_1signext64
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]] ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
; CHECK: $w0 = COPY [[T3]](s32) ; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: $x1 = COPY [[T1]](s64) ; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
%3:_(s64) = G_SEXT %1 %3:_(s64) = G_SEXT %1
$w0 = COPY %2 $w0 = COPY %2
$x1 = COPY %3 $x1 = COPY %3
... ...
--- ---
name: test_2anyext32_1signext64 name: test_2anyext32_1signext64
body: | body: |
bb.0.entry: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_2anyext32_1signext64 ; CHECK-LABEL: name: test_2anyext32_1signext64
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]] ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
; CHECK: [[T5:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]] ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
; CHECK: $w0 = COPY [[T3]](s32) ; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: $x1 = COPY [[T1]](s64) ; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
; CHECK: $w2 = COPY [[T5]](s32) ; CHECK: $w2 = COPY [[ANYEXT1]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
%3:_(s64) = G_SEXT %1 %3:_(s64) = G_SEXT %1
%4:_(s32) = G_ANYEXT %1 %4:_(s32) = G_ANYEXT %1
$w0 = COPY %2 $w0 = COPY %2
$x1 = COPY %3 $x1 = COPY %3
$w2 = COPY %4 $w2 = COPY %4
... ...
--- ---
name: test_multiblock_anyext name: test_multiblock_anyext
body: | body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_multiblock_anyext ; CHECK-LABEL: name: test_multiblock_anyext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: bb.0:
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
; CHECK: G_BR %bb.1 ; CHECK: G_BR %bb.1
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: bb.1:
; CHECK: $w0 = COPY [[LOAD]](s32)
bb.0:
liveins: $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1 G_BR %bb.1
bb.1: bb.1:
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$w0 = COPY %2 $w0 = COPY %2
... ...
--- ---
name: test_multiblock_signext name: test_multiblock_signext
body: | body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_multiblock_signext ; CHECK-LABEL: name: test_multiblock_signext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: bb.0:
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: G_BR %bb.1
; CHECK: bb.1:
; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
bb.0:
liveins: $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1 G_BR %bb.1
bb.1: bb.1:
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
$w0 = COPY %2 $w0 = COPY %2
... ...
--- ---
name: test_multiblock_zeroext name: test_multiblock_zeroext
body: | body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_multiblock_zeroext ; CHECK-LABEL: name: test_multiblock_zeroext
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: bb.0:
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: $w0 = COPY [[T1]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: G_BR %bb.1
; CHECK: bb.1:
; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
bb.0:
liveins: $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1 G_BR %bb.1
bb.1: bb.1:
%2:_(s32) = G_ZEXT %1 %2:_(s32) = G_ZEXT %1
$w0 = COPY %2 $w0 = COPY %2
... ...
--- ---
name: test_multiblock_2anyext name: test_multiblock_2anyext
body: | body: |
bb.0.entry: ; CHECK-LABEL: name: test_multiblock_2anyext
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
; CHECK: G_BR %bb.1
; CHECK: bb.1:
; CHECK: $w0 = COPY [[LOAD]](s32)
; CHECK: $w1 = COPY [[LOAD]](s32)
bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_multiblock
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
; CHECK: $w0 = COPY [[T1]](s32)
; CHECK: $w1 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
G_BR %bb.1 G_BR %bb.1
bb.1: bb.1:
%3:_(s32) = G_ANYEXT %1 %3:_(s32) = G_ANYEXT %1
$w0 = COPY %2 $w0 = COPY %2
$w1 = COPY %3 $w1 = COPY %3
... ...
--- ---
name: test_multiblock_1anyext64_1signext32 name: test_multiblock_1anyext64_1signext32
body: | body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_multiblock_1anyext64_1signext32 ; CHECK-LABEL: name: test_multiblock_1anyext64_1signext32
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: bb.0:
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: G_BR %bb.1 ; CHECK: G_BR %bb.1
; CHECK: [[T2:%[0-9]+]]:_(s64) = G_ANYEXT [[T1]] ; CHECK: bb.1:
; CHECK: $x0 = COPY [[T2]](s64) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
; CHECK: $w1 = COPY [[T1]](s32) ; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
bb.0:
liveins: $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1 G_BR %bb.1
bb.1: bb.1:
%2:_(s64) = G_ANYEXT %1 %2:_(s64) = G_ANYEXT %1
%3:_(s32) = G_SEXT %1 %3:_(s32) = G_SEXT %1
$x0 = COPY %2 $x0 = COPY %2
$w1 = COPY %3 $w1 = COPY %3
... ...
--- ---
name: test_multiblock_1anyext32_1signext64 name: test_multiblock_1anyext32_1signext64
body: | body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_multiblock_1anyext32_1signext64 ; CHECK-LABEL: name: test_multiblock_1anyext32_1signext64
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: bb.0:
; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: G_BR %bb.1 ; CHECK: G_BR %bb.1
; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]] ; CHECK: bb.1:
; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
; CHECK: $w0 = COPY [[T3]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
; CHECK: $x1 = COPY [[T1]](s64) ; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
bb.0:
liveins: $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1 G_BR %bb.1
bb.1: bb.1:
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
%3:_(s64) = G_SEXT %1 %3:_(s64) = G_SEXT %1
$w0 = COPY %2 $w0 = COPY %2
$x1 = COPY %3 $x1 = COPY %3
... ...
--- ---
name: test_multiblock_2anyext32_1signext64 name: test_multiblock_2anyext32_1signext64
body: | body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_multiblock_2anyext32_1signext64 ; CHECK-LABEL: name: test_multiblock_2anyext32_1signext64
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: bb.0:
; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]] ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]] ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
; CHECK: G_BR %bb.1 ; CHECK: G_BR %bb.1
; CHECK: [[T4:%[0-9]+]]:_(s8) = G_TRUNC [[T1]] ; CHECK: bb.1:
; CHECK: [[T5:%[0-9]+]]:_(s32) = G_ANYEXT [[T4]] ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
; CHECK: $w0 = COPY [[T5]](s32) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8)
; CHECK: $x1 = COPY [[T1]](s64) ; CHECK: $w0 = COPY [[ANYEXT1]](s32)
; CHECK: $w2 = COPY [[T3]](s32) ; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
; CHECK: $w2 = COPY [[ANYEXT]](s32)
bb.0:
liveins: $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %1:_(s8) = G_LOAD %0 :: (load 1)
%4:_(s32) = G_ANYEXT %1 %4:_(s32) = G_ANYEXT %1
G_BR %bb.1 G_BR %bb.1
bb.1: bb.1:
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
%3:_(s64) = G_SEXT %1 %3:_(s64) = G_SEXT %1
$w0 = COPY %2 $w0 = COPY %2
$x1 = COPY %3 $x1 = COPY %3
$w2 = COPY %4 $w2 = COPY %4
... ...
---
name: test_atomic
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_atomic
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load unordered 2)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16)
; CHECK: $w0 = COPY [[ZEXT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%1:_(s16) = G_LOAD %0(p0) :: (load unordered 2)
%2:_(s32) = G_ZEXT %1(s16)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...