[WebAssembly] Fix constness of pointer params to load intrinsics

[tlively]

Summary

Update the SIMD builtin load functions to take pointers to const data and update
the intrinsics themselves to not cast away constness.

[aheejin]

Why do only these instructions have const? It doesn't apply to other read-only arguments?

[tlively]

It only matters for pointer parameters. For example, const int * is meaningfully different from int *, but const int is not usefully different from int.

[aheejin]

I see, thanks. Then other load instructions are OK not to be fixed?

• v128.load
• v128.loadN_splat
• v128.loadNxM_s/u

[tlively]

In D101884#2739898, @aheejin wrote:

I see, thanks. Then other load instructions are OK not to be fixed?

• v128.load
• v128.loadN_splat
• v128.loadNxM_s/u

Yep, the intrinsics for those instructions were already using const pointers correctly.

clang/include/clang/Basic/BuiltinsWebAssembly.def

 TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8UsV4iV4i", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4, "V4UiV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_demote_zero_f64x2_f32x4, "V4fV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_promote_low_f32x4_f64x2, "V2dV4f", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_load32_zero, "V4ii*", "n", "simd128")
-TARGET_BUILTIN(__builtin_wasm_load64_zero, "V2LLiLLi*", "n", "simd128")
+TARGET_BUILTIN(__builtin_wasm_load32_zero, "V4iiC*", "n", "simd128")
+TARGET_BUILTIN(__builtin_wasm_load64_zero, "V2LLiLLiC*", "n", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_load8_lane, "V16ScSc*V16ScIi", "n", "simd128")
-TARGET_BUILTIN(__builtin_wasm_load16_lane, "V8ss*V8sIi", "n", "simd128")
-TARGET_BUILTIN(__builtin_wasm_load32_lane, "V4ii*V4iIi", "n", "simd128")
-TARGET_BUILTIN(__builtin_wasm_load64_lane, "V2LLiLLi*V2LLiIi", "n", "simd128")
+TARGET_BUILTIN(__builtin_wasm_load8_lane, "V16ScScC*V16ScIi", "n", "simd128")
+TARGET_BUILTIN(__builtin_wasm_load16_lane, "V8ssC*V8sIi", "n", "simd128")
+TARGET_BUILTIN(__builtin_wasm_load32_lane, "V4iiC*V4iIi", "n", "simd128")
+TARGET_BUILTIN(__builtin_wasm_load64_lane, "V2LLiLLiC*V2LLiIi", "n", "simd128")
 TARGET_BUILTIN(__builtin_wasm_store8_lane, "vSc*V16ScIi", "n", "simd128")
 TARGET_BUILTIN(__builtin_wasm_store16_lane, "vs*V8sIi", "n", "simd128")
 TARGET_BUILTIN(__builtin_wasm_store32_lane, "vi*V4iIi", "n", "simd128")
 TARGET_BUILTIN(__builtin_wasm_store64_lane, "vLLi*V2LLiIi", "n", "simd128")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/Headers/wasm_simd128.h

wasm_v128_load64_zero(const void *__mem) {
   struct __wasm_v128_load64_zero_struct {
     int64_t __v;
   } __attribute__((__packed__, __may_alias__));
   int64_t __v = ((const struct __wasm_v128_load64_zero_struct *)__mem)->__v;
   return (v128_t)(__i64x2){__v, 0};
 }
 
 #define wasm_v128_load8_lane(__ptr, __vec, __i)                                \
-  ((v128_t)__builtin_wasm_load8_lane((signed char *)(__ptr), (__i8x16)(__vec), \
-                                     (__i)))
+  ((v128_t)__builtin_wasm_load8_lane((const signed char *)(__ptr),             \
+                                     (__i8x16)(__vec), (__i)))
 
 #define wasm_v128_load16_lane(__ptr, __vec, __i)                               \
-  ((v128_t)__builtin_wasm_load16_lane((short *)(__ptr), (__i16x8)(__vec),      \
-                                      (__i)))
+  ((v128_t)__builtin_wasm_load16_lane((const short *)(__ptr),                  \
+                                      (__i16x8)(__vec), (__i)))
 
 #define wasm_v128_load32_lane(__ptr, __vec, __i)                               \
-  ((v128_t)__builtin_wasm_load32_lane((int *)(__ptr), (__i32x4)(__vec), (__i)))
+  ((v128_t)__builtin_wasm_load32_lane((const int *)(__ptr), (__i32x4)(__vec),  \
+                                      (__i)))
 
 #define wasm_v128_load64_lane(__ptr, __vec, __i)                               \
-  ((v128_t)__builtin_wasm_load64_lane((long long int *)(__ptr),                \
+  ((v128_t)__builtin_wasm_load64_lane((const long long int *)(__ptr),          \
                                       (__i64x2)(__vec), (__i)))
 
 static __inline__ void __DEFAULT_FN_ATTRS wasm_v128_store(void *__mem,
                                                           v128_t __a) {
   // UB-free unaligned access copied from xmmintrin.h
   struct __wasm_v128_store_struct {
     __v128_u __v;
   } __attribute__((__packed__, __may_alias__));

clang/test/CodeGen/builtins-wasm.c

 }
 
 f64x2 replace_lane_f64x2(f64x2 v, double x) {
   return __builtin_wasm_replace_lane_f64x2(v, 1, x);
   // WEBASSEMBLY: insertelement <2 x double> %v, double %x, i32 1
   // WEBASSEMBLY-NEXT: ret
 }
 
-i8x16 load8_lane(signed char *p, i8x16 v) {
+i8x16 load8_lane(const signed char *p, i8x16 v) {
   return __builtin_wasm_load8_lane(p, v, 0);
   // WEBASSEMBLY: tail call <16 x i8> @llvm.wasm.load8.lane(
   // WEBASSEMBLY-SAME: i8* %p, <16 x i8> %v, i32 0)
   // WEBASSEMBLY-NEXT: ret
 }
 
-i16x8 load16_lane(short *p, i16x8 v) {
+i16x8 load16_lane(const short *p, i16x8 v) {
   return __builtin_wasm_load16_lane(p, v, 0);
   // WEBASSEMBLY: tail call <8 x i16> @llvm.wasm.load16.lane(
   // WEBASSEMBLY-SAME: i16* %p, <8 x i16> %v, i32 0)
   // WEBASSEMBLY-NEXT: ret
 }
 
-i32x4 load32_lane(int *p, i32x4 v) {
+i32x4 load32_lane(const int *p, i32x4 v) {
   return __builtin_wasm_load32_lane(p, v, 0);
   // WEBASSEMBLY: tail call <4 x i32> @llvm.wasm.load32.lane(
   // WEBASSEMBLY-SAME: i32* %p, <4 x i32> %v, i32 0)
   // WEBASSEMBLY-NEXT: ret
 }
 
-i64x2 load64_lane(long long *p, i64x2 v) {
+i64x2 load64_lane(const long long *p, i64x2 v) {
   return __builtin_wasm_load64_lane(p, v, 0);
   // WEBASSEMBLY: tail call <2 x i64> @llvm.wasm.load64.lane(
   // WEBASSEMBLY-SAME: i64* %p, <2 x i64> %v, i32 0)
   // WEBASSEMBLY-NEXT: ret
 }
 
 void store8_lane(signed char *p, i8x16 v) {
   __builtin_wasm_store8_lane(p, v, 0);

 }
 
 f64x2 wasm_promote_low_f32x4_f64x2(f32x4 x) {
   return __builtin_wasm_promote_low_f32x4_f64x2(x);
   // WEBASSEMBLY: call <2 x double> @llvm.wasm.promote.low(<4 x float> %x)
   // WEBASSEMBLY: ret
 }
 
-i32x4 load32_zero(int *p) {
+i32x4 load32_zero(const int *p) {
   return __builtin_wasm_load32_zero(p);
   // WEBASSEMBLY: call <4 x i32> @llvm.wasm.load32.zero(i32* %p)
   // WEBASSEMBLY: ret
 }
 
-i64x2 load64_zero(long long *p) {
+i64x2 load64_zero(const long long *p) {
   return __builtin_wasm_load64_zero(p);
   // WEBASSEMBLY: call <2 x i64> @llvm.wasm.load64.zero(i64* %p)
   // WEBASSEMBLY: ret
 }
 
 i8x16 swizzle_i8x16(i8x16 x, i8x16 y) {
   return __builtin_wasm_swizzle_i8x16(x, y);
   // WEBASSEMBLY: call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y)

clang/test/Headers/wasm.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --force-update
 // REQUIRES: webassembly-registered-target, asserts
 
-// RUN: %clang %s -O2 -emit-llvm -S -o - -target wasm32-unknown-unknown -msimd128 | FileCheck %s
+// RUN: %clang %s -O2 -emit-llvm -S -o - -target wasm32-unknown-unknown -msimd128 -Wcast-qual -Werror | FileCheck %s
 
 #include <wasm_simd128.h>
 
 // CHECK-LABEL: @test_v128_load(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__V_I:%.*]] = bitcast i8* [[MEM:%.*]] to <4 x i32>*
 // CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[__V_I]], align 1, !tbaa [[TBAA2:![0-9]+]]
 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]

 
 // CHECK-LABEL: @test_v128_load8_lane(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x i32> [[VEC:%.*]] to <16 x i8>
 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i8> @llvm.wasm.load8.lane(i8* [[PTR:%.*]], <16 x i8> [[TMP0]], i32 15)
 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 //
-v128_t test_v128_load8_lane(uint8_t *ptr, v128_t vec) {
+v128_t test_v128_load8_lane(const uint8_t *ptr, v128_t vec) {
   return wasm_v128_load8_lane(ptr, vec, 15);
 }
 
 // CHECK-LABEL: @test_v128_load16_lane(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x i32> [[VEC:%.*]] to <8 x i16>
 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i16> @llvm.wasm.load16.lane(i16* [[PTR:%.*]], <8 x i16> [[TMP0]], i32 7)
 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to <4 x i32>
 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 //
-v128_t test_v128_load16_lane(uint16_t *ptr, v128_t vec) {
+v128_t test_v128_load16_lane(const uint16_t *ptr, v128_t vec) {
   return wasm_v128_load16_lane(ptr, vec, 7);
 }
 
 // CHECK-LABEL: @test_v128_load32_lane(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <4 x i32> @llvm.wasm.load32.lane(i32* [[PTR:%.*]], <4 x i32> [[VEC:%.*]], i32 3)
 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
 //
-v128_t test_v128_load32_lane(uint32_t *ptr, v128_t vec) {
+v128_t test_v128_load32_lane(const uint32_t *ptr, v128_t vec) {
   return wasm_v128_load32_lane(ptr, vec, 3);
 }
 
 // CHECK-LABEL: @test_v128_load64_lane(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x i32> [[VEC:%.*]] to <2 x i64>
 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x i64> @llvm.wasm.load64.lane(i64* [[PTR:%.*]], <2 x i64> [[TMP0]], i32 1)
 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x i32>
 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 //
-v128_t test_v128_load64_lane(uint64_t *ptr, v128_t vec) {
+v128_t test_v128_load64_lane(const uint64_t *ptr, v128_t vec) {
   return wasm_v128_load64_lane(ptr, vec, 1);
 }
 
 // CHECK-LABEL: @test_v128_store(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__V_I:%.*]] = bitcast i8* [[MEM:%.*]] to <4 x i32>*
 // CHECK-NEXT:    store <4 x i32> [[A:%.*]], <4 x i32>* [[__V_I]], align 1, !tbaa [[TBAA2]]
 // CHECK-NEXT:    ret void