[AMDGPU][MC][NFC] Removed extra spaces

[dp]

Summary

Fixed bugs 49646, 49647.

llvm/lib/Target/AMDGPU/DSInstructions.td

 let SubtargetPredicate = HasDSAddTid in {
 def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;
 }
 
 } // End mayLoad = 0
 
 let SubtargetPredicate = isGFX90APlus in {
   defm DS_ADD_F64     : DS_1A1D_NORET_mc_gfx9<"ds_add_f64", VReg_64>;
-  defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64 ", VReg_64, "ds_add_f64">;
+  defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64", VReg_64, "ds_add_f64">;
 } // End SubtargetPredicate = isGFX90APlus
 
 defm DS_MSKOR_B32     : DS_1A2D_NORET_mc<"ds_mskor_b32">;
 defm DS_CMPST_B32     : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
 defm DS_CMPST_F32     : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
 
 defm DS_ADD_U64       : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
 defm DS_SUB_U64       : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

if (((DstIdx >= 0 &&
     if (AMDGPU::isGFX10Plus(STI)) {
       O << "/* row_bcast is not supported starting from GFX10 */";
       return;
     }
     O << "row_bcast:31";
   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
     if (AMDGPU::isGFX90A(STI)) {
-      O << " row_newbcast:";
+      O << "row_newbcast:";
     } else if (AMDGPU::isGFX10Plus(STI)) {
       O << "row_share:";
     } else {
       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
            "than GFX90A/GFX10 */";
       return;
     }
     printU4ImmDecOperand(MI, OpNo, O);