[AMDGPU] Check for all meta instrs in GCNRegBankReassign

[rampitec]

Summary

It used to work correctly even with a KILL, but there is
no reason to consider meta instructions since they do not
create real HW uses.

[arsenm]

If it doesn't make an observable difference, there's no real reason to add the extra check?

[rampitec]

In D100135#2677755, @arsenm wrote:

If it doesn't make an observable difference, there's no real reason to add the extra check?

There is a difference though. In the last test with KILL %1, %0 before the patch %1 would be reassigned to v3 since v1 and v5 have bank conflict. After the patch it will remain in v5 as assigned which leaves more room for other reassignments. This is a fake conflict. Plus we do not need to spend any time on the false coflicts.

llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

 }
 
 std::pair<unsigned, unsigned>
 GCNRegBankReassign::analyzeInst(const MachineInstr &MI, Register Reg,
                                 unsigned SubReg, int Bank) {
   unsigned StallCycles = 0;
   unsigned UsedBanks = 0;
 
-  if (MI.isDebugValue())
+  if (MI.isMetaInstruction())
     return std::make_pair(StallCycles, UsedBanks);
 
   if (!(Mode & RM_SGPR) &&
       MI.getDesc().TSFlags & (SIInstrFlags::SMRD | SIInstrFlags::SALU))
     return std::make_pair(StallCycles, UsedBanks);
 
   RegsUsed.reset();
   OperandMasks.clear();

llvm/test/CodeGen/AMDGPU/regbank-reassign.mir

bb.0:
     %12 = IMPLICIT_DEF
     %13 = IMPLICIT_DEF
     %14 = IMPLICIT_DEF
     %15 = IMPLICIT_DEF
     %3 = V_ADD_F64_e64 0, %0.sub2_sub3:vreg_128, 0, %1:vreg_64, 0, 0, implicit $mode, implicit $exec
     %4 = V_ADD_F64_e64 0, %0.sub0_sub1:vreg_128, 0, %2:vreg_64, 0, 0, implicit $mode, implicit $exec
     S_ENDPGM 0
 ...
+
+# GCN-LABEL: dbg_value_v1_v5{{$}}
+# GCN: renamable $vgpr1 = IMPLICIT_DEF
+# GCN: renamable $vgpr5 = IMPLICIT_DEF
+---
+name:            dbg_value_v1_v5
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '$vgpr1' }
+  - { id: 1, class: vgpr_32, preferred-register: '$vgpr5' }
+  - { id: 2, class: vgpr_32 }
+body: |
+  bb.0:
+    %0 = IMPLICIT_DEF
+    %1 = IMPLICIT_DEF
+    DBG_VALUE debug-use %1, debug-use %0
+    S_ENDPGM 0, implicit %0, implicit %1
+...
+
+# GCN-LABEL: kill_v1_v5{{$}}
+# GCN: renamable $vgpr1 = IMPLICIT_DEF
+# GCN: renamable $vgpr5 = IMPLICIT_DEF
+# GCN: KILL killed renamable $vgpr5, killed renamable $vgpr1
+---
+name:            kill_v1_v5
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '$vgpr1' }
+  - { id: 1, class: vgpr_32, preferred-register: '$vgpr5' }
+  - { id: 2, class: vgpr_32 }
+body: |
+  bb.0:
+    %0 = IMPLICIT_DEF
+    %1 = IMPLICIT_DEF
+    KILL %1, %0
+    S_ENDPGM 0
+...