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[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
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Authored by craig.topper on Mon, Mar 22, 11:53 PM.

Details

Summary

The default legalization strategy is PromoteFloat which keeps
half in single precision format through multiple floating point
operations. Conversion to/from float is done at loads, stores,
bitcasts, and other places that care about the exact size being 16
bits.

This patches switches to the alternative method softPromoteHalf.
This aims to keep the type in 16-bit format between every operation.
So we promote to float and immediately round for any arithmetic
operation. This should be closer to the IR semantics since we
are rounding after each operation and not accumulating extra
precision across multiple operations. X86 is the only other
target that enables this today. See https://reviews.llvm.org/D73749

I had to update getRegisterTypeForCallingConv to force f16 to
use f32 when the F extension is enabled. This way we can still
pass it in the lower bits of an FPR for ilp32f and lp64f ABIs.
The softPromoteHalf would otherwise always give i16 as the
argument type.

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Event Timeline

craig.topper created this revision.Mon, Mar 22, 11:53 PM
craig.topper requested review of this revision.Mon, Mar 22, 11:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptMon, Mar 22, 11:53 PM
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LGTM. Waiting for the consent of others.

asb accepted this revision.Thu, Apr 1, 3:46 AM

Let's mention it in the community call today just in case anyone has strong differing opinions, but this lowering strategy makes much more intuitive sense to me.

This revision is now accepted and ready to land.Thu, Apr 1, 3:46 AM

General code gen behavior change is look good to me.

frasercrmck accepted this revision.Thu, Apr 1, 8:53 AM

Indeed. And it is also good to have a second in-tree target test this strategy.

This revision was landed with ongoing or failed builds.Thu, Apr 1, 12:42 PM
This revision was automatically updated to reflect the committed changes.