[llvm][AArch64][SVE] Lower fixed length vector fabs

[peterwaller-arm]

Summary

Seemingly striaghtforward.

[bsmith]

LGTM

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
   setOperationAction(ISD::ADD, VT, Custom);
   setOperationAction(ISD::AND, VT, Custom);
   setOperationAction(ISD::ANY_EXTEND, VT, Custom);
   setOperationAction(ISD::BITREVERSE, VT, Custom);
   setOperationAction(ISD::BSWAP, VT, Custom);
   setOperationAction(ISD::CTLZ, VT, Custom);
   setOperationAction(ISD::CTPOP, VT, Custom);
   setOperationAction(ISD::CTTZ, VT, Custom);
+  setOperationAction(ISD::FABS, VT, Custom);
   setOperationAction(ISD::FADD, VT, Custom);
   setOperationAction(ISD::FCEIL, VT, Custom);
   setOperationAction(ISD::FDIV, VT, Custom);
   setOperationAction(ISD::FFLOOR, VT, Custom);
   setOperationAction(ISD::FMA, VT, Custom);
   setOperationAction(ISD::FMAXIMUM, VT, Custom);
   setOperationAction(ISD::FMAXNUM, VT, Custom);
   setOperationAction(ISD::FMINIMUM, VT, Custom);

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll

 ; CHECK: ret
   %op1 = load <32 x double>, <32 x double>* %a
   %op2 = load <32 x double>, <32 x double>* %b
   %res = fsub <32 x double> %op1, %op2
   store <32 x double> %res, <32 x double>* %a
   ret void
 }
 
+;
+; FABS
+;
+
+; Don't use SVE for 64-bit vectors.
+define <4 x half> @fabs_v4f16(<4 x half> %op) #0 {
+; CHECK-LABEL: fabs_v4f16:
+; CHECK: fabs v0.4h, v0.4h
+; CHECK: ret
+  %res = call <4 x half> @llvm.fabs.v4f16(<4 x half> %op)
+  ret <4 x half> %res
+}
+
+; Don't use SVE for 128-bit vectors.
+define <8 x half> @fabs_v8f16(<8 x half> %op) #0 {
+; CHECK-LABEL: fabs_v8f16:
+; CHECK: fabs v0.8h, v0.8h
+; CHECK: ret
+  %res = call <8 x half> @llvm.fabs.v8f16(<8 x half> %op)
+  ret <8 x half> %res
+}
+
+define void @fabs_v16f16(<16 x half>* %a) #0 {
+; CHECK-LABEL: fabs_v16f16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
+; CHECK: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; CHECK: st1h { [[RES]].h }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <16 x half>, <16 x half>* %a
+  %res = call <16 x half> @llvm.fabs.v16f16(<16 x half> %op)
+  store <16 x half> %res, <16 x half>* %a
+  ret void
+}
+
+define void @fabs_v32f16(<32 x half>* %a) #0 {
+; CHECK-LABEL: fabs_v32f16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
+; CHECK: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; CHECK: st1h { [[RES]].h }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <32 x half>, <32 x half>* %a
+  %res = call <32 x half> @llvm.fabs.v32f16(<32 x half> %op)
+  store <32 x half> %res, <32 x half>* %a
+  ret void
+}
+
+define void @fabs_v64f16(<64 x half>* %a) #0 {
+; CHECK-LABEL: fabs_v64f16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
+; CHECK: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; CHECK: st1h { [[RES]].h }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <64 x half>, <64 x half>* %a
+  %res = call <64 x half> @llvm.fabs.v64f16(<64 x half> %op)
+  store <64 x half> %res, <64 x half>* %a
+  ret void
+}
+
+define void @fabs_v128f16(<128 x half>* %a) #0 {
+; CHECK-LABEL: fabs_v128f16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
+; CHECK: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; CHECK: st1h { [[RES]].h }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <128 x half>, <128 x half>* %a
+  %res = call <128 x half> @llvm.fabs.v128f16(<128 x half> %op)
+  store <128 x half> %res, <128 x half>* %a
+  ret void
+}
+
+; Don't use SVE for 64-bit vectors.
+define <2 x float> @fabs_v2f32(<2 x float> %op) #0 {
+; CHECK-LABEL: fabs_v2f32:
+; CHECK: fabs v0.2s, v0.2s
+; CHECK: ret
+  %res = call <2 x float> @llvm.fabs.v2f32(<2 x float> %op)
+  ret <2 x float> %res
+}
+
+; Don't use SVE for 128-bit vectors.
+define <4 x float> @fabs_v4f32(<4 x float> %op) #0 {
+; CHECK-LABEL: fabs_v4f32:
+; CHECK: fabs v0.4s, v0.4s
+; CHECK: ret
+  %res = call <4 x float> @llvm.fabs.v4f32(<4 x float> %op)
+  ret <4 x float> %res
+}
+
+define void @fabs_v8f32(<8 x float>* %a) #0 {
+; CHECK-LABEL: fabs_v8f32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
+; CHECK: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <8 x float>, <8 x float>* %a
+  %res = call <8 x float> @llvm.fabs.v8f32(<8 x float> %op)
+  store <8 x float> %res, <8 x float>* %a
+  ret void
+}
+
+define void @fabs_v16f32(<16 x float>* %a) #0 {
+; CHECK-LABEL: fabs_v16f32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
+; CHECK: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <16 x float>, <16 x float>* %a
+  %res = call <16 x float> @llvm.fabs.v16f32(<16 x float> %op)
+  store <16 x float> %res, <16 x float>* %a
+  ret void
+}
+
+define void @fabs_v32f32(<32 x float>* %a) #0 {
+; CHECK-LABEL: fabs_v32f32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
+; CHECK: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <32 x float>, <32 x float>* %a
+  %res = call <32 x float> @llvm.fabs.v32f32(<32 x float> %op)
+  store <32 x float> %res, <32 x float>* %a
+  ret void
+}
+
+define void @fabs_v64f32(<64 x float>* %a) #0 {
+; CHECK-LABEL: fabs_v64f32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
+; CHECK: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <64 x float>, <64 x float>* %a
+  %res = call <64 x float> @llvm.fabs.v64f32(<64 x float> %op)
+  store <64 x float> %res, <64 x float>* %a
+  ret void
+}
+
+; Don't use SVE for 64-bit vectors.
+define <1 x double> @fabs_v1f64(<1 x double> %op) #0 {
+; CHECK-LABEL: fabs_v1f64:
+; CHECK: fabs d0, d0
+; CHECK: ret
+  %res = call <1 x double> @llvm.fabs.v1f64(<1 x double> %op)
+  ret <1 x double> %res
+}
+
+; Don't use SVE for 128-bit vectors.
+define <2 x double> @fabs_v2f64(<2 x double> %op) #0 {
+; CHECK-LABEL: fabs_v2f64:
+; CHECK: fabs v0.2d, v0.2d
+; CHECK: ret
+  %res = call <2 x double> @llvm.fabs.v2f64(<2 x double> %op)
+  ret <2 x double> %res
+}
+
+define void @fabs_v4f64(<4 x double>* %a) #0 {
+; CHECK-LABEL: fabs_v4f64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
+; CHECK: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <4 x double>, <4 x double>* %a
+  %res = call <4 x double> @llvm.fabs.v4f64(<4 x double> %op)
+  store <4 x double> %res, <4 x double>* %a
+  ret void
+}
+
+define void @fabs_v8f64(<8 x double>* %a) #0 {
+; CHECK-LABEL: fabs_v8f64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
+; CHECK: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <8 x double>, <8 x double>* %a
+  %res = call <8 x double> @llvm.fabs.v8f64(<8 x double> %op)
+  store <8 x double> %res, <8 x double>* %a
+  ret void
+}
+
+define void @fabs_v16f64(<16 x double>* %a) #0 {
+; CHECK-LABEL: fabs_v16f64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
+; CHECK: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <16 x double>, <16 x double>* %a
+  %res = call <16 x double> @llvm.fabs.v16f64(<16 x double> %op)
+  store <16 x double> %res, <16 x double>* %a
+  ret void
+}
+
+define void @fabs_v32f64(<32 x double>* %a) #0 {
+; CHECK-LABEL: fabs_v32f64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
+; CHECK: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; CHECK: fabs [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
+; CHECK: ret
+  %op = load <32 x double>, <32 x double>* %a
+  %res = call <32 x double> @llvm.fabs.v32f64(<32 x double> %op)
+  store <32 x double> %res, <32 x double>* %a
+  ret void
+}
+
 attributes #0 = { "target-features"="+sve" }
 
 declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)
 declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
 declare <16 x half> @llvm.fma.v16f16(<16 x half>, <16 x half>, <16 x half>)
 declare <32 x half> @llvm.fma.v32f16(<32 x half>, <32 x half>, <32 x half>)
 declare <64 x half> @llvm.fma.v64f16(<64 x half>, <64 x half>, <64 x half>)
 declare <128 x half> @llvm.fma.v128f16(<128 x half>, <128 x half>, <128 x half>)

 declare <32 x float> @llvm.sqrt.v32f32(<32 x float>)
 declare <64 x float> @llvm.sqrt.v64f32(<64 x float>)
 declare <1 x double> @llvm.sqrt.v1f64(<1 x double>)
 declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)
 declare <4 x double> @llvm.sqrt.v4f64(<4 x double>)
 declare <8 x double> @llvm.sqrt.v8f64(<8 x double>)
 declare <16 x double> @llvm.sqrt.v16f64(<16 x double>)
 declare <32 x double> @llvm.sqrt.v32f64(<32 x double>)
+
+declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
+declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
+declare <16 x half> @llvm.fabs.v16f16(<16 x half>)
+declare <32 x half> @llvm.fabs.v32f16(<32 x half>)
+declare <64 x half> @llvm.fabs.v64f16(<64 x half>)
+declare <128 x half> @llvm.fabs.v128f16(<128 x half>)
+declare <2 x float> @llvm.fabs.v2f32(<2 x float>)
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
+declare <8 x float> @llvm.fabs.v8f32(<8 x float>)
+declare <16 x float> @llvm.fabs.v16f32(<16 x float>)
+declare <32 x float> @llvm.fabs.v32f32(<32 x float>)
+declare <64 x float> @llvm.fabs.v64f32(<64 x float>)
+declare <1 x double> @llvm.fabs.v1f64(<1 x double>)
+declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
+declare <4 x double> @llvm.fabs.v4f64(<4 x double>)
+declare <8 x double> @llvm.fabs.v8f64(<8 x double>)
+declare <16 x double> @llvm.fabs.v16f64(<16 x double>)
+declare <32 x double> @llvm.fabs.v32f64(<32 x double>)