- User Since
- Sep 12 2013, 6:57 AM (396 w, 6 d)
The fact that the DestructiveBinary case in this needs to insert extra MOV's to make up for what is essentially poor register allocation choices, is less than ideal. I'm abandoning this in favour of a proper solution at a later date that will depend on D88595.
Fri, Apr 16
- Rename ISD nodes to match common names
- Preserve some alphabetical ordering
- Fix 2048 vector width tests
- Update fixed width tests to test vector widths smaller than the given value
- Allow generation of SVE mulh instructions for neon sized i64 vectors
- Add test to check divide expansion that can now happen
- Add minsize attribute to some SVE divide tests to prevent divide expansion from happening
Thu, Apr 15
Wed, Apr 14
- Use attribute in tests in favour of -mattr on run line
Tue, Apr 13
- Add missing test
- Tidy up comment
Mon, Apr 12
Thu, Apr 1
Wed, Mar 31
- Add extra tests that explicitly check the calling convention used
- Use sext for predicate mask extension, rather than anyext
Tue, Mar 30
- Fixed incorrect parameter in tests
- Remove superfluous call to LowerFixedLengthVectorSelectToSVE
Mon, Mar 29
Fri, Mar 26
Thu, Mar 25
- Remove unfinished case for SELECT_CC, this isn't needed currently for SVE, can be added later if/when needed.
- Tidy up code in VectorLegalizer::ExpandSETCC.
- Fix bogus test names.
Wed, Mar 24
Mar 22 2021
- Fixed failures in PPC/RISCV tests due to slightly different codegen.
- Use getBoolConstant instead of manually constructing true/false values.
Mar 19 2021
Mar 17 2021
Mar 16 2021
- Remove SDTFPRoundEvenOp as it's not a correct mirror of SDTFPRoundOp since that is not for ISD::FROUND.
- Fix comments in include/llvm/Target/TargetSelectionDAG.td for SDTFPRoundOp and SDTFPExtendOp.
Mar 15 2021
- Prevent vscale_range(0,0) from crashing and instead don't add the attribute
- Improve CHECK lines in arm-sve-vector-bits-vscale-range.c test
- Test vscale_range(0,0) case and move some tests around
- Add AutoUpgrade code to convert aarch64.neon.frintn to roundeven
- Add test for above AutoUpgrade
- Fix test failure in named-vector-shuffles-sve.ll
Why is this patch only changing int_aarch64_neon_frintn and not int_aarch64_sve_frintn?
Is there a particular reason to do so?
Mar 12 2021
- State what lack of vscale_range attribute means in LangRef
- Minor formatting change
Mar 11 2021
- Split reg+reg tests from reg+imm tests
- Add more reg+reg tests to cover all patterns
Mar 10 2021
- Simplify new addressing mode tests
Given this approach has other downsides (namely reserving x29 all the time for SVE), I think instead of doing this I'll revert the previous patch this fixes, and wait until we have a better approach for this.
Mar 5 2021
Mar 3 2021
- Remove LICM vscale intrinsic changes
- Update tests to disable LSR to check vscale folding.
Mar 2 2021
- Fix new test that appeared after rebase.
Mar 1 2021
- Always explicitly reserve x29 when building for SVE
- Add comments to indicate the fact that this is a temporary change
- Add early bailout when not building for SVE
Feb 22 2021
Feb 18 2021
Feb 15 2021
- Reverse order of dependant patches, pulling half tests from D96599
- Add missing half tests
- Reverse order of dependant patches, moving all SVE tests into D96424
- Update tests in line with changes to D96424
- Regenerate tests with update_llc_test_checks.py
- Restructure patterns to use a multiclass
- Remove duplicated patterns
- Add missing patterns for more f16 types
Feb 12 2021
- Add some more FNMLA patterns that are required when things get combined slightly differently
- Only return true in generateFMAsInMachineCombiner when the types in question are scalable, and not always when SVE is present.
- Move generateFMAsInMachineCombiner into AArch64TargetLowering
- Replace use of -fp-contract=fast in tests with fast flag on instructions
- Pull out FP16 combining into a separate patch
Feb 11 2021
Feb 10 2021
Jan 29 2021
Jan 28 2021
Committed as rG42635856ed3c. (Forgot to add differential tag in commit message).
Jan 26 2021
Jan 21 2021
- Remove duplicate tests
- Some code cleanups as per review comments
Jan 19 2021
Resigning as reviewer to remove needs changes flag
Jan 11 2021
Jan 7 2021
After much discussion I'm actually incorrect in this assertion, as I mistakenly thought that the ptrue's were ending up being passed straight into the load rather than through the existing svbool convertions. That said this case with (%4, %5 and %7 made not redundant) does now produce worse codegen with this pass:
I'm not sure this patch is correct as it's not taking into account how the predicates are used, for example in following case your patch replaces the ptrue_b32() predicate of the %5 8 x i16 load with a ptrue_b16(), which changes the behaviour.
Jan 5 2021
Jan 4 2021
- Add comments to brk testcase to note what is being tested
Dec 18 2020
- Add missing tests for BRK* cases
- Improve misleading comment