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paulwalker-arm (Paul Walker)
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Nov 24 2016, 5:21 AM (228 w, 6 d)

Recent Activity

Today

paulwalker-arm added a comment to D100107: [AArch64][SVE] Combine add and index_vector.
Wed, Apr 14, 2:58 AM · Restricted Project

Tue, Apr 6

paulwalker-arm added inline comments to D99699: [AArch64][SVE] Lowering sve.dot to DOT node.
Tue, Apr 6, 4:48 AM · Restricted Project

Thu, Apr 1

paulwalker-arm accepted D99418: [AArch64][SVE] Improve codegen for select nodes with fixed types.
Thu, Apr 1, 6:44 AM · Restricted Project
paulwalker-arm added inline comments to D99699: [AArch64][SVE] Lowering sve.dot to DOT node.
Thu, Apr 1, 4:00 AM · Restricted Project

Wed, Mar 31

paulwalker-arm added a reviewer for D99657: [AArch64][SVE] SVE functions should use the SVE calling convention for fast calls: sdesmalen.
Wed, Mar 31, 5:53 AM · Restricted Project
paulwalker-arm added inline comments to D99418: [AArch64][SVE] Improve codegen for select nodes with fixed types.
Wed, Mar 31, 2:53 AM · Restricted Project
paulwalker-arm accepted D99584: [AArch64][SVE] Remove redundant PTEST of MATCH/NMATCH results.
Wed, Mar 31, 2:41 AM · Restricted Project

Tue, Mar 30

paulwalker-arm added a comment to D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.

I'm still struggling with how best to represent STEPVECTOR's scale operand. The patch as it currently stands is probably good enough but I do wonder how long we'll get by without needing to implement PromoteIntOp_STEP_VECTOR. I also wonder if we can take a similar approach as done for INSERT_SUBVECTOR's index operand.

Hey. Sorry to raise a closed thread but this exact issue is making it difficult to support STEP_VECTOR on RISC-V. On RV32 we don't have legal i64 but do have legal i64 vectors. So we're hitting an assert during visitStepVector where we try and create a nxvXi64 STEP_VECTOR with an i32 operand. Are you aware of anything that stops us from changing the requirements to be an integer pointer type? It might limit optimizations but we can always not perform DAG combines if it's not safe to do so?

Tue, Mar 30, 7:59 AM · Restricted Project
paulwalker-arm added inline comments to D99418: [AArch64][SVE] Improve codegen for select nodes with fixed types.
Tue, Mar 30, 2:32 AM · Restricted Project

Mon, Mar 29

paulwalker-arm added a comment to D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).

Just wanted to add that the patch summary no longer matches the intent of the patch.

Mon, Mar 29, 7:48 AM · Restricted Project
paulwalker-arm accepted D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).
Mon, Mar 29, 7:45 AM · Restricted Project
paulwalker-arm accepted D99502: [InstructionCost] Don't conflate Invalid costs with Unknown costs..

I agree, InstructionCost::Invalid is solving a specific problem which is different to "Did not bother computing a real cost".

Mon, Mar 29, 7:30 AM · Restricted Project
paulwalker-arm accepted D98939: [SelectionDAG][AArch64][SVE] Perform SETCC condition legalization in LegalizeVectorOps.
Mon, Mar 29, 7:22 AM · Restricted Project
paulwalker-arm accepted D98625: [AArch64][SVE] Lower fixed length EXTRACT_VECTOR_ELT.
Mon, Mar 29, 7:08 AM · Restricted Project
paulwalker-arm accepted D99412: [AArch64][SVEIntrinsicOpts] Optimize tbl+dup into dup+extractelement.
Mon, Mar 29, 5:08 AM · Restricted Project
paulwalker-arm added inline comments to D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).
Mon, Mar 29, 4:43 AM · Restricted Project
paulwalker-arm added inline comments to D99412: [AArch64][SVEIntrinsicOpts] Optimize tbl+dup into dup+extractelement.
Mon, Mar 29, 4:20 AM · Restricted Project

Fri, Mar 26

paulwalker-arm added a comment to D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).

Excuse me, I am new to LLVM/backend, one question is: What does "stock LLVM IR" mean(refer to) in above comment?

Fri, Mar 26, 4:39 AM · Restricted Project
paulwalker-arm added inline comments to D99412: [AArch64][SVEIntrinsicOpts] Optimize tbl+dup into dup+extractelement.
Fri, Mar 26, 4:31 AM · Restricted Project

Thu, Mar 25

paulwalker-arm added inline comments to D98625: [AArch64][SVE] Lower fixed length EXTRACT_VECTOR_ELT.
Thu, Mar 25, 6:04 AM · Restricted Project
paulwalker-arm accepted D98856: Always emit error for wrong interfaces to scalable vectors, unless cmdline flag is passed..
Thu, Mar 25, 5:30 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).

OK, I understand you point. splat_vector(extract_vector_elt(vec, idx)) looks ok for me, and why you prefer do it in in SVEIntrinsicOpts.cpp ? what about do this in performdagcombine with AArch64TBL node?

The reason i prefer to handle in performdagcombine is that what we want to match is AArch64tbl ( ... splat_vector(..., constant)) rather than sve.tbl + sve.dupx. Since shufflevector can also convert to splat_vector.

Thu, Mar 25, 5:12 AM · Restricted Project
paulwalker-arm added a comment to D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).

I'm not saying all the pieces will come for free but this feels like an intrinsic optimisation problem rather than an instruction selection one. What about extending SVEIntrinsicOpts.cpp to convert the pattern to a stock splat_vector(extract_vector_elt(vec, idx)) and then letting the code generator decide how best to lower the LLVM way of doing things. This'll mean we solve the problem once for ACLE and auto-vectorisation.

Actually, it is an isel issue, The svdup_lane in title is just where I find this issue.
1), there is no intrinsic direct map to dup (index) instruction, while vector_extract may lower with dup (index), it is not enough. 2) svdup_lane acle intrinsic generates as sve.dup.x + sve.tbl in llvm ir, and covert to AArch64tbl ( ... splat_vector(..., constant)) , then lower to AArch64tbl ( ... DUP(..., imm)). This is the pattern this patch try to match.

Thu, Mar 25, 4:16 AM · Restricted Project
paulwalker-arm added a comment to D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).

I'm not saying all the pieces will come for free but this feels like an intrinsic optimisation problem rather than an instruction selection one. What about extending SVEIntrinsicOpts.cpp to convert the pattern to a stock splat_vector(extract_vector_elt(vec, idx)) and then letting the code generator decide how best to lower the LLVM way of doing things. This'll mean we solve the problem once for ACLE and auto-vectorisation.

Thu, Mar 25, 3:35 AM · Restricted Project

Mon, Mar 22

paulwalker-arm added inline comments to D98625: [AArch64][SVE] Lower fixed length EXTRACT_VECTOR_ELT.
Mon, Mar 22, 4:47 AM · Restricted Project

Fri, Mar 19

paulwalker-arm accepted D98874: [TTI] Return a TypeSize from getRegisterBitWidth..
Fri, Mar 19, 9:57 AM · Restricted Project
paulwalker-arm added inline comments to D98856: Always emit error for wrong interfaces to scalable vectors, unless cmdline flag is passed..
Fri, Mar 19, 9:42 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.

A couple of niggles but otherwise looks good to me.

Fri, Mar 19, 8:57 AM · Restricted Project

Thu, Mar 18

paulwalker-arm added inline comments to D98874: [TTI] Return a TypeSize from getRegisterBitWidth..
Thu, Mar 18, 9:49 AM · Restricted Project

Wed, Mar 17

paulwalker-arm added inline comments to D98509: [LV] Calculate max feasible scalable VF..
Wed, Mar 17, 3:19 AM · Restricted Project

Tue, Mar 16

paulwalker-arm accepted D98487: [AArch64][SVE/NEON] Add support for FROUNDEVEN for both NEON and fixed length SVE.

Mainly focused on the SVE side of things, which looks good to me.

Tue, Mar 16, 9:42 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.

I'm still struggling with how best to represent STEPVECTOR's scale operand. The patch as it currently stands is probably good enough but I do wonder how long we'll get by without needing to implement PromoteIntOp_STEP_VECTOR. I also wonder if we can take a similar approach as done for INSERT_SUBVECTOR's index operand.

Tue, Mar 16, 9:20 AM · Restricted Project

Mar 15 2021

paulwalker-arm accepted D98030: [IR] Add vscale_range IR function attribute.
Mar 15 2021, 11:46 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D98030: [IR] Add vscale_range IR function attribute.
Mar 15 2021, 6:45 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D97382: NFC: Migrate PartialInlining to work on InstructionCost.
Mar 15 2021, 5:25 AM · Restricted Project
paulwalker-arm added a comment to D98487: [AArch64][SVE/NEON] Add support for FROUNDEVEN for both NEON and fixed length SVE.

Why is this patch only changing int_aarch64_neon_frintn and not int_aarch64_sve_frintn?
Is there a particular reason to do so?

Things are done slightly differently for SVE in this regard, in principal yes, we could emit roundeven instead of frintn from the ACLE intrinsic, however all of the other ACLE intrinsics also emit SVE specific LLVM intrinsics rather than the arch-indep nodes. This patch doesn't change that in order to stay consistent, if we did want to change that it should be done as a separate patch that changes all of them.

Mar 15 2021, 4:00 AM · Restricted Project, Restricted Project

Mar 14 2021

paulwalker-arm added inline comments to D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.
Mar 14 2021, 4:04 AM · Restricted Project
paulwalker-arm accepted D95677: [AArch64][SVE] Add unpredicated ld1/st1 patterns for reg+reg addressing modes.
Mar 14 2021, 3:51 AM · Restricted Project

Mar 11 2021

paulwalker-arm added inline comments to D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.
Mar 11 2021, 2:02 AM · Restricted Project

Mar 10 2021

paulwalker-arm accepted D98348: [AArch64][SVE] Add fixed/scalable lowering of FMAXIMUM/FMINIMUM ISD nodes.
Mar 10 2021, 8:32 AM · Restricted Project
paulwalker-arm added a comment to D95677: [AArch64][SVE] Add unpredicated ld1/st1 patterns for reg+reg addressing modes.

Sorry I didn't mention this as part of my previous review but there should really be a test for each isel pattern. These do exist for the imm variants, it is just they were added to spillfill-sve.ll instead of sve-ld1-addressing-mode-reg-imm.ll. Given the name of the existing test file and the quantity of the new tests perhaps it is worth creating sve-ld1-addressing-mode-reg-reg.ll?

Mar 10 2021, 8:15 AM · Restricted Project
paulwalker-arm added inline comments to D95677: [AArch64][SVE] Add unpredicated ld1/st1 patterns for reg+reg addressing modes.
Mar 10 2021, 4:32 AM · Restricted Project
paulwalker-arm added inline comments to D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.
Mar 10 2021, 3:03 AM · Restricted Project

Mar 9 2021

paulwalker-arm added a comment to D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.

I'm still working through the patch but here's what I've got for now.

Mar 9 2021, 11:02 AM · Restricted Project

Mar 5 2021

paulwalker-arm added a comment to D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.

If the ISD node is going to get an argument for the step, why not let the new intrinsic have this same argument?

Mar 5 2021, 4:55 AM · Restricted Project
paulwalker-arm added inline comments to D98030: [IR] Add vscale_range IR function attribute.
Mar 5 2021, 4:46 AM · Restricted Project, Restricted Project

Mar 2 2021

paulwalker-arm accepted D97466: NFC: Change getUserCost to return InstructionCost.
Mar 2 2021, 3:59 PM · Restricted Project

Feb 25 2021

paulwalker-arm added inline comments to D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.
Feb 25 2021, 10:44 AM · Restricted Project
paulwalker-arm added inline comments to D97466: NFC: Change getUserCost to return InstructionCost.
Feb 25 2021, 9:41 AM · Restricted Project
paulwalker-arm resigned from D85977: [release][docs] Update contributions to LLVM 11 for SVE..
Feb 25 2021, 9:28 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D97471: [SVE] Fix LoopVectorizer test scalalable-call.ll.
Feb 25 2021, 9:27 AM · Restricted Project

Feb 24 2021

paulwalker-arm added a comment to D97276: [CodeGen] Canonicalise adds/subs of i1 vectors using XOR.

Why is this in getNode() rather than DAGCombine? https://github.com/llvm/llvm-project/commit/6f5a805bbbed5d0cdaaf67846dffa7f044afb407 for example does something very similar in DAGCombine. What's the guideline for correct placement here?

Feb 24 2021, 3:50 AM · Restricted Project
paulwalker-arm accepted D97276: [CodeGen] Canonicalise adds/subs of i1 vectors using XOR.

Not sure of the value of the "ILLEGAL" tests given they're actually testing we can type legalise ISD::XOR, which I'm presuming is already well tested. That said it's nothing I cannot live with.

Feb 24 2021, 2:53 AM · Restricted Project

Feb 22 2021

paulwalker-arm added inline comments to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.
Feb 22 2021, 3:27 AM · Restricted Project

Feb 19 2021

paulwalker-arm added inline comments to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.
Feb 19 2021, 11:08 AM · Restricted Project

Feb 17 2021

paulwalker-arm accepted D96852: [clang][SVE] Use __inline__ instead of inline in arm_sve.h.
Feb 17 2021, 9:36 AM · Restricted Project
paulwalker-arm added a comment to D96852: [clang][SVE] Use __inline__ instead of inline in arm_sve.h.

One observation is that for arm_neon.h __inline__ is used. So perhaps we can just do likewise and we'll also be consistent across the two ACLE headers?

Feb 17 2021, 6:30 AM · Restricted Project
paulwalker-arm added a comment to D96852: [clang][SVE] Use __inline__ instead of inline in arm_sve.h.

Speaking to @DavidTruby about this, it appears that this fix is insufficient -- inline has important semantic meaning in C++ that means that we can't simply omit the keyword here.

The inline keyword bypasses the one-definition rule. If we have a function defined in a header that isn't marked inline, and you include that header in two different source files, then your program is ill formed because it contains 2 definitions of that function. So we have to keep it for C++.

Feb 17 2021, 6:17 AM · Restricted Project
paulwalker-arm accepted D96849: [SVE][CodeGen] Expand SVE MULH[SU] and [SU]MUL_LOHI nodes.
Feb 17 2021, 5:29 AM · Restricted Project
paulwalker-arm accepted D96852: [clang][SVE] Use __inline__ instead of inline in arm_sve.h.
Feb 17 2021, 4:24 AM · Restricted Project

Feb 16 2021

paulwalker-arm accepted D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD.

Given the extensive testing within sve-fp-combine.ll I do wonder why sve-fma-dagcombine.ll is required, but otherwise the patch looks good.

Feb 16 2021, 10:47 AM · Restricted Project

Feb 15 2021

paulwalker-arm accepted D96700: [llvm][Aarch64][SVE] Remove extra fmov instruction with certain literals.
Feb 15 2021, 6:41 AM · Restricted Project
paulwalker-arm added inline comments to D96700: [llvm][Aarch64][SVE] Remove extra fmov instruction with certain literals.
Feb 15 2021, 6:18 AM · Restricted Project
paulwalker-arm requested changes to D96700: [llvm][Aarch64][SVE] Remove extra fmov instruction with certain literals.
Feb 15 2021, 6:11 AM · Restricted Project
paulwalker-arm accepted D96700: [llvm][Aarch64][SVE] Remove extra fmov instruction with certain literals.

Patch looks good to me. I'll leave it up to you whether you want to extend the patch to cover f16/f64 cases or defer until needed.

Feb 15 2021, 4:46 AM · Restricted Project
paulwalker-arm added inline comments to D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD.
Feb 15 2021, 3:31 AM · Restricted Project
paulwalker-arm added inline comments to D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD.
Feb 15 2021, 3:20 AM · Restricted Project

Feb 12 2021

paulwalker-arm accepted D94883: [CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse.

One minor issue that can be fixed when merging.

Feb 12 2021, 3:36 AM · Restricted Project

Feb 5 2021

paulwalker-arm accepted D95967: [DAGCombiner][SVE] Fix invalid use of getVectorNumElements() in visitSRA..
Feb 5 2021, 3:24 AM · Restricted Project

Feb 4 2021

paulwalker-arm added inline comments to D95967: [DAGCombiner][SVE] Fix invalid use of getVectorNumElements() in visitSRA..
Feb 4 2021, 3:34 AM · Restricted Project

Jan 27 2021

paulwalker-arm added inline comments to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.
Jan 27 2021, 4:04 AM · Restricted Project

Jan 26 2021

paulwalker-arm added a comment to D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.
<A x Elt> llvm.experimental.vector.extract.elements(<B x Elt> %invec, i32 index, i32 stride)
Jan 26 2021, 3:22 AM · Restricted Project

Jan 24 2021

paulwalker-arm added a comment to D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.

For now I'll just cover the IR side of things as the ISD node discussion raises different points and there's nothing to say they need to match.

Jan 24 2021, 4:08 AM · Restricted Project
paulwalker-arm added a comment to D94883: [CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse.

Taking a step back, are there plans to use the intrinsics for fixed vectors?

Jan 24 2021, 3:39 AM · Restricted Project

Jan 22 2021

paulwalker-arm added a comment to D94883: [CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse.

Mirroring my comments for D94708: if the intrinsics needs to support fixed vectors, it would be good to have some tests for platforms other than AArch64 and also support in GlobalISel, which is the default on AArch64 with -O0 IIRC (or do the transform to shuffles as an IR transform).

Hi @fhahn, I agree with your point about -O0, but I'm not sure why we need tests for other platforms? Carol has an extensive set of tests for both fixed width and scalable vectors. The lowering is identical for fixed width vectors regardless of the target so all it would be testing is the different codegen of vector shuffles.

Jan 22 2021, 3:25 AM · Restricted Project

Jan 20 2021

paulwalker-arm added inline comments to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.
Jan 20 2021, 12:50 PM · Restricted Project

Jan 16 2021

paulwalker-arm added inline comments to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.
Jan 16 2021, 4:18 AM · Restricted Project
paulwalker-arm added a comment to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.

In D94444, @paulwalker-arm proposed a more generic extract vector intrinsic that accepts an index and stride. Now I'm wondering if we should just have a generic scalable shuffle vector intrinsic to handle all these operations under one intrinsic.

That idea doesn't need to hold up this Diff, but it might be something to consider...

Jan 16 2021, 4:08 AM · Restricted Project

Jan 15 2021

paulwalker-arm committed rG2b8db40c9218: [SVE] Restrict the usage of REINTERPRET_CAST. (authored by paulwalker-arm).
[SVE] Restrict the usage of REINTERPRET_CAST.
Jan 15 2021, 3:34 AM
paulwalker-arm closed D94593: [SVE] Restrict the usage of REINTERPRET_CAST..
Jan 15 2021, 3:34 AM · Restricted Project

Jan 14 2021

paulwalker-arm added a comment to D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.

A bit of a flyby review as I'm still on holidays but to my mind many of the restrictions being proposed for the new intrinsic seem purely down to the design decision of splitting the input vector across two operands. I understand this is how the underlying instructions work for SVE but that does not seem like a good enough reason to compromise the IR.

Jan 14 2021, 3:36 AM · Restricted Project

Jan 13 2021

paulwalker-arm added reviewers for D94593: [SVE] Restrict the usage of REINTERPRET_CAST.: kmclaughlin, david-arm, c-rhodes.
Jan 13 2021, 5:26 AM · Restricted Project
paulwalker-arm requested review of D94593: [SVE] Restrict the usage of REINTERPRET_CAST..
Jan 13 2021, 5:09 AM · Restricted Project

Jan 7 2021

paulwalker-arm accepted D94160: [AArch64][SVE] Add lowering for llvm abs intrinsic.

Thanks @david-arm . FYI the CHECK-DAGs within sve-fixed-length-int-arith.ll don't need to be DAGs but I'm going to restructure these tests anyway so there's no point changing them.

Jan 7 2021, 2:00 AM · Restricted Project
paulwalker-arm added a comment to D94193: [SVE] Unpacked scalable floating point ZIP/UZP/TRN.

Please can you add entries for nxv2f16 as well? That way all the legal fp types are covered.

Jan 7 2021, 1:51 AM · Restricted Project
paulwalker-arm added inline comments to D94069: [NFC][InstructionCost]Migrate VectorCombine.cpp to use InstructionCost.
Jan 7 2021, 1:40 AM · Restricted Project

Jan 6 2021

paulwalker-arm added a comment to D94160: [AArch64][SVE] Add lowering for llvm abs intrinsic.

I'm just keeping things ticking over. It doesn't have to be this patch, I just did wanted to know if it's something I can take off my TODO list. If you're support eager then FABS also requires fixed length support :)

Jan 6 2021, 3:49 AM · Restricted Project
paulwalker-arm accepted D94160: [AArch64][SVE] Add lowering for llvm abs intrinsic.

Do you plan to add support for fixed length vectors?

Jan 6 2021, 3:12 AM · Restricted Project

Jan 5 2021

paulwalker-arm committed rGeba6deab22b5: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations. (authored by paulwalker-arm).
[SVE] Lower vector CTLZ, CTPOP and CTTZ operations.
Jan 5 2021, 2:57 AM
paulwalker-arm closed D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations..
Jan 5 2021, 2:57 AM · Restricted Project
paulwalker-arm added a comment to D91834: [SelectionDAG] Use TypeSize for the stack offset..

As before I still believe there should be a test to protect this fix as presumably you're doing it for a reason.

Jan 5 2021, 2:29 AM · Restricted Project

Dec 27 2020

paulwalker-arm accepted D93825: [AArch64] Fix legalization of i128 ctpop without neon.
Dec 27 2020, 2:24 AM · Restricted Project
paulwalker-arm added inline comments to D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations..
Dec 27 2020, 2:17 AM · Restricted Project

Dec 22 2020

paulwalker-arm committed rGbe85b3e4324b: Fix some misnamed variables in sve-fixed-length-int-minmax.ll. (authored by paulwalker-arm).
Fix some misnamed variables in sve-fixed-length-int-minmax.ll.
Dec 22 2020, 9:12 AM
paulwalker-arm committed rG8eec7294fea8: [SVE] Lower vector BITREVERSE and BSWAP operations. (authored by paulwalker-arm).
[SVE] Lower vector BITREVERSE and BSWAP operations.
Dec 22 2020, 8:51 AM
paulwalker-arm closed D93606: [SVE] Lower vector BITREVERSE and BSWAP operations..
Dec 22 2020, 8:51 AM · Restricted Project

Dec 21 2020

paulwalker-arm updated the diff for D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations..

Fixed incorrect variable naming within ctlz_v64i8, ctpop_v64i8, cttz_v64i8.

Dec 21 2020, 8:23 AM · Restricted Project
paulwalker-arm updated the diff for D93606: [SVE] Lower vector BITREVERSE and BSWAP operations..

Fixed incorrect variable naming with bitreverse_v64i8 test.
Made test function names consistent.

Dec 21 2020, 8:15 AM · Restricted Project

Dec 20 2020

paulwalker-arm added reviewers for D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations.: cameron.mcinally, david-arm, kmclaughlin.
Dec 20 2020, 5:09 PM · Restricted Project
paulwalker-arm added reviewers for D93606: [SVE] Lower vector BITREVERSE and BSWAP operations.: cameron.mcinally, david-arm, kmclaughlin.
Dec 20 2020, 5:09 PM · Restricted Project