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paulwalker-arm (Paul Walker)
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Nov 24 2016, 5:21 AM (204 w, 3 d)

Recent Activity

Yesterday

paulwalker-arm abandoned D89950: [SVE] Implement extractelement of i1 from scalable vectors..
Sat, Oct 24, 10:11 AM · Restricted Project
paulwalker-arm added a reviewer for D90093: [SVE] Move INT_TO_FP i1 promotion into custom lowering.: kmclaughlin.

I've created this patch so as to be consistent with D87651.

Sat, Oct 24, 3:36 AM · Restricted Project
paulwalker-arm requested review of D90093: [SVE] Move INT_TO_FP i1 promotion into custom lowering..
Sat, Oct 24, 3:32 AM · Restricted Project

Fri, Oct 23

paulwalker-arm accepted D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

With this patch[1] landed I believe operation legalisation is now a solved problem for SVE (well for fixed length vectors). I think it's worth tackling the type legalisation side of things rather than overcomplicating shouldExpandReduction. Of course that's easy for me to say given it's your time :) but you've already done part of the work based on the older patch.

Fri, Oct 23, 11:53 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

@cameron.mcinally: I'm sure you know this but just in case it saves some time I can confirm you will not hit the splitting code until after you relax shouldExpandReduction. So I think your current patch is complete so it really comes down to whether adding the support this way round (i.e. only allow legal types for SVE, then allow all types and implement the legalisation) is acceptable to @nikic .

Fri, Oct 23, 9:29 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

@paulwalker-arm There is no need to implement any target-specific support. The legalization outcome will be a simple chain of extracts and fadd/fmuls. It does not need to generate good code, just not assert for any VTs.

Fri, Oct 23, 8:51 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

@nikic Why does wanting to implement VECREDUCE_SEQ_FADD for SVE necessitate having to implement full support for NEON (AArch64 and Arm)?

Fri, Oct 23, 8:22 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

The new tests would be broken without the legalisation changes, so I'm assuming that those are enough coverage. Maybe I'm missing something though...

Fri, Oct 23, 7:50 AM · Restricted Project
paulwalker-arm added inline comments to D89382: [SVE][CodeGen] Lower scalable integer vector reductions.
Fri, Oct 23, 5:12 AM · Restricted Project
paulwalker-arm accepted D87651: [AArch64][SVE] Implement extractelement of i1 vectors..

I just don't buy this argument. You're saying that we must force all target's to perform custom lowering for promotable illegal operations on i1 vectors because somebody in the future might try to "fix" LegalizeDAG when they should implement custom lowering for extend/truncate operations. This is the situation Target/AArch64 is in and we never considered "fixing" LegalizeDAG so I don't see why others wouldn't just follow our example.

Fri, Oct 23, 4:31 AM · Restricted Project

Thu, Oct 22

paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Sorry @cameron.mcinally I've not had much time for code reviews this week although will take proper look tomorrow. I have a question though. You've added extra legalisation support but I don't see any explicit tests (or at least ones with matching check lines) for it. Is this something you need for this patch? (I'm guessing sve-fixed-length-fp-reduce.ll's stock NEON run line triggers the cases?) If so then there really should be a neon specific test file that verifies the widening and scalarisation changes as the NEON run line for the "fixed-length" tests is more about ensuring no SVE instructions slip through.

Thu, Oct 22, 9:37 AM · Restricted Project
paulwalker-arm added a comment to D87651: [AArch64][SVE] Implement extractelement of i1 vectors..

Perhaps I'm missing something but I've created D89950 to show what I mentioned in my previous comment. To me it's preferable to have this as target independent code as it seems a common enough solution. I know it results in "Pomote" having multiple meanings but that boat has sailed because different nodes have already chosen different meanings and I think it's pretty clear from the old and new VTs what's being asked for.

Thu, Oct 22, 4:26 AM · Restricted Project
paulwalker-arm requested review of D89950: [SVE] Implement extractelement of i1 from scalable vectors..
Thu, Oct 22, 4:17 AM · Restricted Project

Tue, Oct 20

paulwalker-arm added inline comments to D89382: [SVE][CodeGen] Lower scalable integer vector reductions.
Tue, Oct 20, 3:44 PM · Restricted Project

Fri, Oct 16

paulwalker-arm accepted D88654: [SVE][CodeGen] Replace uses of TypeSize comparison operators with calls to isKnownXY.
Fri, Oct 16, 4:42 AM · Restricted Project

Thu, Oct 15

paulwalker-arm added a comment to D88654: [SVE][CodeGen] Replace uses of TypeSize comparison operators with calls to isKnownXY.

I guess most of my comments relate to minimising direct uses of TypeSize.

Thu, Oct 15, 8:49 AM · Restricted Project
paulwalker-arm added inline comments to D89382: [SVE][CodeGen] Lower scalable integer vector reductions.
Thu, Oct 15, 6:10 AM · Restricted Project

Wed, Oct 14

paulwalker-arm accepted D89263: [SVE] Lower fixed length VECREDUCE_FADD operation.

Not lowering to SVE for v2f## MVTs makes sense for now but as before when we have proper support for v#i1 our hands will be tied.

Wed, Oct 14, 4:27 AM · Restricted Project

Tue, Oct 13

paulwalker-arm committed rG981b31c282ea: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0" (authored by paulwalker-arm).
[SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0"
Tue, Oct 13, 2:55 AM
paulwalker-arm closed D89235: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0".
Tue, Oct 13, 2:55 AM · Restricted Project

Mon, Oct 12

paulwalker-arm added a comment to D89246: [SVE] Remove aarch64_sve_vector_pcs attribute.

I think we should keep this because it gives us the possibility to attach it to functions where the function signature wouldn't use it otherwise.

Mon, Oct 12, 9:22 AM · Restricted Project
paulwalker-arm added a comment to D89235: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0".

Looking at the testing I think there are some holes regarding general vector inserts, but I'll investigate that under a different patch.

Mon, Oct 12, 4:48 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Are you planning to add support for the normal VECREDUCE_FADD? I ask because that's likely to see more initial use upstream than the SEQ variant.

Mon, Oct 12, 4:47 AM · Restricted Project
paulwalker-arm added reviewers for D89235: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0": cameron.mcinally, david-arm, kmclaughlin.
Mon, Oct 12, 4:41 AM · Restricted Project
paulwalker-arm requested review of D89235: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0".
Mon, Oct 12, 4:40 AM · Restricted Project

Thu, Oct 8

paulwalker-arm accepted D88974: [SVE] Lower fixed length VECREDUCE_XOR operation.
Thu, Oct 8, 4:18 AM · Restricted Project

Tue, Oct 6

paulwalker-arm committed rG8bb702a8ad30: [SVE] Lower fixed length vector floating point rounding operations. (authored by paulwalker-arm).
[SVE] Lower fixed length vector floating point rounding operations.
Tue, Oct 6, 2:57 AM
paulwalker-arm committed rG27f3d51b4ef9: [SVE] Lower fixed length vector fneg and fsqrt operations. (authored by paulwalker-arm).
[SVE] Lower fixed length vector fneg and fsqrt operations.
Tue, Oct 6, 2:57 AM
paulwalker-arm closed D88683: [SVE] Lower fixed length vector fneg and fsqrt operations..
Tue, Oct 6, 2:57 AM · Restricted Project
paulwalker-arm closed D88671: [SVE] Lower fixed length vector floating point rounding operations..
Tue, Oct 6, 2:57 AM · Restricted Project
paulwalker-arm accepted D88847: [SVE] Lower fixed length VECREDUCE_OR operation.
Tue, Oct 6, 2:46 AM · Restricted Project

Mon, Oct 5

paulwalker-arm added a comment to D88707: [SVE] Lower fixed length VECREDUCE_AND operation.

Committed. It looks like the legalisations seem reasonable. Something like:

; VBITS_EQ_256-DAG: and [[AND:z[0-9]+]].d, [[LO]].d, [[HI]].d
; VBITS_EQ_256-DAG: andv h[[REDUCE:[0-9]+]], [[PG]], [[AND]].h

How are the legalisation tests usually handled? Are they done once for a class of instructions? Or should I go back to add CHECKs for the other reductions too? @kmclaughlin

Mon, Oct 5, 9:47 AM · Restricted Project
paulwalker-arm accepted D88707: [SVE] Lower fixed length VECREDUCE_AND operation.
Mon, Oct 5, 4:56 AM · Restricted Project

Fri, Oct 2

paulwalker-arm added a comment to D88707: [SVE] Lower fixed length VECREDUCE_AND operation.

Re: OverrideNEON: I wouldn't get too hung up on this. The original intention was me trying to reduce the chances of going down broken code paths and also not surprise people with a complete change of code generation output (a.k.a Operation "get something that's usable quickly"). Once wide vector support is driven by function attributes and we start adding proper v#i1 support, we'll be forced to breakaway from NEON and OverrideNEON will become a distant memory.

Fri, Oct 2, 5:29 AM · Restricted Project

Thu, Oct 1

paulwalker-arm accepted D88679: [AArch64][SVE] Add lowering for llvm fabs.
Thu, Oct 1, 10:50 AM · Restricted Project
paulwalker-arm added reviewers for D88683: [SVE] Lower fixed length vector fneg and fsqrt operations.: cameron.mcinally, david-arm, kmclaughlin.
Thu, Oct 1, 10:44 AM · Restricted Project
paulwalker-arm requested review of D88683: [SVE] Lower fixed length vector fneg and fsqrt operations..
Thu, Oct 1, 10:43 AM · Restricted Project
paulwalker-arm added reviewers for D88671: [SVE] Lower fixed length vector floating point rounding operations.: cameron.mcinally, david-arm, sdesmalen.

Pretty much by the number but note that I've omitted ISD::FROUNDEVEN because support for that is already lacking for NEON.

Thu, Oct 1, 9:20 AM · Restricted Project
paulwalker-arm requested review of D88671: [SVE] Lower fixed length vector floating point rounding operations..
Thu, Oct 1, 9:18 AM · Restricted Project
paulwalker-arm committed rG8931c3d68276: [NFC] Iterate across an explicit list of scalable MVTs when driving… (authored by paulwalker-arm).
[NFC] Iterate across an explicit list of scalable MVTs when driving…
Thu, Oct 1, 2:25 AM
paulwalker-arm closed D88552: [NFC] Iterate across an explicit list of scalable MVTs when driving setOperationAction..
Thu, Oct 1, 2:25 AM · Restricted Project

Wed, Sep 30

paulwalker-arm updated the diff for D88552: [NFC] Iterate across an explicit list of scalable MVTs when driving setOperationAction..

Don't suggest promotion for 'vscale x 16' lane floating point operations.

Wed, Sep 30, 6:17 AM · Restricted Project
paulwalker-arm added reviewers for D88552: [NFC] Iterate across an explicit list of scalable MVTs when driving setOperationAction.: efriedma, sdesmalen, david-arm, kmclaughlin.
Wed, Sep 30, 3:58 AM · Restricted Project
paulwalker-arm requested review of D88552: [NFC] Iterate across an explicit list of scalable MVTs when driving setOperationAction..
Wed, Sep 30, 3:56 AM · Restricted Project

Tue, Sep 29

paulwalker-arm accepted D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.

@cameron.mcinally No worries, I clearly didn't do the best job reviewing that patch either.

Tue, Sep 29, 9:45 AM · Restricted Project
paulwalker-arm added inline comments to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.
Tue, Sep 29, 9:03 AM · Restricted Project
paulwalker-arm added inline comments to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.
Tue, Sep 29, 3:50 AM · Restricted Project
paulwalker-arm added a comment to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.

Also, while I have everyone's attention, there are a number of unhandled vector reduction intrinsics with SVE support. Do we want to add lowerings for those? E.g. ANDV.

Tue, Sep 29, 3:05 AM · Restricted Project
paulwalker-arm accepted D88321: [SVE][CodeGen] Lower scalable fp_extend & fp_round operations.

FP_ROUND's extra operand is a tad inconvenient but that's not your fault and you're following the naming rules for _MERGE_PASSTHRU so this LGTM. I'll note there's no illegal to illegal test for fptrunc like there is for fpext but then I don't know what those tests are verifying that's not already covered by the illegal<->legal tests.

Tue, Sep 29, 2:46 AM · Restricted Project

Mon, Sep 28

paulwalker-arm added a comment to D88317: [SVE] Lower fixed length VECREDUCE_[UMAX|UMIN] to Scalable.

Or, if @kmclaughlin would like, I can add the Scalable lowerings while I'm here. Assuming you don't have downstream changes prepared already...

Mon, Sep 28, 7:50 AM · Restricted Project
paulwalker-arm accepted D88317: [SVE] Lower fixed length VECREDUCE_[UMAX|UMIN] to Scalable.

Just a heads up that @kmclaughlin is starting to look at legalisation/lowering for scalable vector types. From an operation legalisation point of view you've done most of the plumbing so hopefully any toe treading will be minimal.

Mon, Sep 28, 4:28 AM · Restricted Project

Sep 25 2020

paulwalker-arm accepted D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.

Formatting issues aside this LGTM.

Sep 25 2020, 11:06 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D88321: [SVE][CodeGen] Lower scalable fp_extend & fp_round operations.
Sep 25 2020, 10:59 AM · Restricted Project
paulwalker-arm accepted D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.

LGTM assuming the potential compiler warning is removed.

Sep 25 2020, 6:24 AM · Restricted Project
paulwalker-arm added inline comments to D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.
Sep 25 2020, 3:42 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.

@david-arm The main priority is to remove the operator overloads so if universally using divideCoefficientBy pleases the most people then let's just do that.

Sep 25 2020, 3:41 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D88259: [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable.

Other than a quibble related to singleton DAG checks this patch LGTM.

Sep 25 2020, 2:51 AM · Restricted Project

Sep 24 2020

paulwalker-arm added inline comments to D88259: [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable.
Sep 24 2020, 6:21 PM · Restricted Project
paulwalker-arm added inline comments to D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.
Sep 24 2020, 4:16 PM · Restricted Project
paulwalker-arm added inline comments to D88259: [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable.
Sep 24 2020, 4:05 PM · Restricted Project
paulwalker-arm added a comment to D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.

I think the precedent has already been set as VectorType and ValueType already deem doubling and halving to be special enough to have explicit operations, albeit they save more effort that what's being saved here. Personally I just think

ElementCount.halve()

is more meaningful/readable than

assert(ElementCount.isKnownMultiple(2));
ElementCount.coefficientDiv(2);

Whereas ElementCount * 2 is already meaningful enough.

Sep 24 2020, 9:39 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D88186: [AArch64][SVE] Drop "argmemonly" from gather/scatter with vector base..
Sep 24 2020, 4:10 AM · Restricted Project

Sep 23 2020

paulwalker-arm added inline comments to D88098: [SVE] Add new isKnownXX comparison functions to TypeSize.
Sep 23 2020, 9:04 AM · Restricted Project
paulwalker-arm added a comment to D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.

LGTM

Alternatively, we could make CONCAT_VECTOR "legal", and lower it using an isel pattern. But I'm not sure that's actually an improvement.

Sep 23 2020, 5:37 AM · Restricted Project
paulwalker-arm added a comment to D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.

I'm not a great fan of the coefficientDiv name but once in I doubt I'll give it a second thought. That said, because by far the most common usage is coefficientDiv(2), whose intent is clearly to knowingly split something into two equal parts I'm wondering if adding a halve() utility function will keep the main usage short and meaningful and then there's even less reason to care about the name of coefficientDiv.

Sep 23 2020, 5:06 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D88098: [SVE] Add new isKnownXX comparison functions to TypeSize.

My preference would be to follow the clang-format advice for TypeSize.h.

Sep 23 2020, 4:06 AM · Restricted Project
paulwalker-arm accepted D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.
Sep 23 2020, 3:41 AM · Restricted Project
paulwalker-arm accepted D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.
Sep 23 2020, 2:22 AM · Restricted Project

Sep 22 2020

paulwalker-arm added inline comments to D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.
Sep 22 2020, 3:16 AM · Restricted Project
paulwalker-arm accepted D88032: [AArch64][SVE] Add lowering for llvm frecpx.
Sep 22 2020, 3:02 AM · Restricted Project
paulwalker-arm added inline comments to D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.
Sep 22 2020, 3:00 AM · Restricted Project

Sep 21 2020

paulwalker-arm committed rGf3fa954b5b19: [SVE] Change definition of reduction ISD nodes to have an SVE vector result… (authored by paulwalker-arm).
[SVE] Change definition of reduction ISD nodes to have an SVE vector result…
Sep 21 2020, 5:23 AM
paulwalker-arm closed D87843: [SVE] Change definition of reduction ISD nodes to have an SVE vector result type..
Sep 21 2020, 5:23 AM · Restricted Project
paulwalker-arm committed rG6457455248d5: [SVE] Use NEON for extract_vector_elt when the index is in range. (authored by paulwalker-arm).
[SVE] Use NEON for extract_vector_elt when the index is in range.
Sep 21 2020, 5:16 AM
paulwalker-arm closed D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..
Sep 21 2020, 5:15 AM · Restricted Project

Sep 18 2020

paulwalker-arm added inline comments to D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..
Sep 18 2020, 9:43 AM · Restricted Project
paulwalker-arm updated the diff for D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..

Replaced custom selection with isel patterns. Since we're going the isel route I figures I may was well add the missing patterns for unpacked floating point types.

Sep 18 2020, 9:29 AM · Restricted Project

Sep 17 2020

paulwalker-arm updated the diff for D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..

Remove block that is incorrectly reporting unpacked and predicate EXTRACT_VECTOR_ELT as legal.

Sep 17 2020, 12:30 PM · Restricted Project
paulwalker-arm added inline comments to D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..
Sep 17 2020, 12:26 PM · Restricted Project
paulwalker-arm added a comment to D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.

D87843 fixes the issue. Its dependence on D87842 is purely to maintain current code quality.

Sep 17 2020, 10:30 AM · Restricted Project
paulwalker-arm added reviewers for D87842: [SVE] Use NEON for extract_vector_elt when the index is in range.: kmclaughlin, david-arm.
Sep 17 2020, 10:27 AM · Restricted Project
paulwalker-arm added reviewers for D87843: [SVE] Change definition of reduction ISD nodes to have an SVE vector result type.: cameron.mcinally, sdesmalen, c-rhodes.
Sep 17 2020, 10:27 AM · Restricted Project
paulwalker-arm requested review of D87843: [SVE] Change definition of reduction ISD nodes to have an SVE vector result type..
Sep 17 2020, 10:25 AM · Restricted Project
paulwalker-arm requested review of D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..
Sep 17 2020, 10:23 AM · Restricted Project
paulwalker-arm added a comment to D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.

Oh, I hadn't realised we are handling reduction in this way upstream (although it does match an old design we had downstream). This is certainly not the expected behaviour so I'll get it fixed. The expectation is for the SVE reduction ISD nodes to reflect the underlying instructions behaviour, which is they set the whole vector register. The reason for this is that we don't want the element extraction to be done during isel because it introduces needless vpr-gpr transitions and there are also use cases that make use of the implicit zeroing of the upper lanes.

Sep 17 2020, 3:31 AM · Restricted Project

Sep 16 2020

paulwalker-arm added a comment to D87232: [SVE][CodeGen] Lower floating point -> integer conversions.

Oh and the commit message should reference the lowering of FP_TO_SINT/FP_TO_UINT.

Sep 16 2020, 8:28 AM · Restricted Project
paulwalker-arm accepted D87232: [SVE][CodeGen] Lower floating point -> integer conversions.

LGTM assuming adding the missing tests don't throw up anything unexpected.

Sep 16 2020, 8:27 AM · Restricted Project
paulwalker-arm added inline comments to D87651: [AArch64][SVE] Implement extractelement of i1 vectors..
Sep 16 2020, 2:55 AM · Restricted Project

Sep 15 2020

paulwalker-arm added inline comments to D87707: [AArch64][SVE] Add lowering for llvm fsqrt.
Sep 15 2020, 10:21 AM · Restricted Project
paulwalker-arm accepted D87707: [AArch64][SVE] Add lowering for llvm fsqrt.

@paulwalker-arm: I couldn't find out the corresponding ISD Node for FRECPX.

Sep 15 2020, 10:20 AM · Restricted Project
paulwalker-arm added inline comments to D87651: [AArch64][SVE] Implement extractelement of i1 vectors..
Sep 15 2020, 3:17 AM · Restricted Project

Sep 10 2020

paulwalker-arm added inline comments to D87232: [SVE][CodeGen] Lower floating point -> integer conversions.
Sep 10 2020, 2:41 PM · Restricted Project
paulwalker-arm added inline comments to D87232: [SVE][CodeGen] Lower floating point -> integer conversions.
Sep 10 2020, 12:35 PM · Restricted Project

Sep 9 2020

paulwalker-arm accepted D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors.

Looks good assuming the new test doesn't throw up any surprises.

Sep 9 2020, 5:39 AM · Restricted Project

Sep 8 2020

paulwalker-arm added a comment to D86078: [AArch64] Improved lowering for saturating float to int..

I'm afraid some of my comments are probably conflicting. I would have experimented a little to understand better how things work, but I'm guessing the patch is based on other work because I couldn't some of the affected functions/nodes.

Sep 8 2020, 7:27 AM · Restricted Project

Sep 7 2020

paulwalker-arm added a comment to D86078: [AArch64] Improved lowering for saturating float to int..

Sorry I had hoped to look at this patch properly today but that hasn't worked out. I've got a general comment below as I think it would be nicer to abstract the NativeSaturation into a TLI hook that other targets can implement when useful to them.

Sep 7 2020, 10:46 AM · Restricted Project
paulwalker-arm added inline comments to D87232: [SVE][CodeGen] Lower floating point -> integer conversions.
Sep 7 2020, 6:55 AM · Restricted Project
paulwalker-arm added inline comments to D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors.
Sep 7 2020, 5:51 AM · Restricted Project

Sep 3 2020

paulwalker-arm accepted D86793: [AArch64][SVE] Add lowering for rounding operations.

Other than adding the missing test before landing that patch, this LGTM.

Sep 3 2020, 8:25 AM · Restricted Project

Sep 2 2020

paulwalker-arm abandoned D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2]..

With the exception of VSELECT lowering, which is being worked under D85364, everything else is available in master.

Sep 2 2020, 4:22 AM · Restricted Project, Restricted Project