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[RISCV] Implement vsoxseg/vsuxseg intrinsics.
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Authored by HsiangKai on Jan 18 2021, 7:25 PM.

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Summary

Define vsoxseg/vsuxseg intrinsics and pseudo instructions. Lower vsoxseg/vsuxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

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Event Timeline

HsiangKai created this revision.Jan 18 2021, 7:25 PM
HsiangKai requested review of this revision.Jan 18 2021, 7:25 PM
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HsiangKai updated this revision to Diff 317753.Jan 19 2021, 7:03 PM

Add test cases for rv32. It does not contain all combinations for vsxseg due to the revision will be too large to upload.

craig.topper added inline comments.Jan 20 2021, 9:47 PM
llvm/include/llvm/IR/IntrinsicsRISCV.td
1056

Make this a FIXME or TODO

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
3095

Make this a FIXME or TODO

HsiangKai updated this revision to Diff 318199.Jan 21 2021, 7:29 AM
HsiangKai marked 2 inline comments as done.
This revision is now accepted and ready to land.Jan 21 2021, 10:29 AM
HsiangKai updated this revision to Diff 318392.Jan 21 2021, 6:48 PM
HsiangKai retitled this revision from [RISCV] Implement vsxseg intrinsics. to [RISCV] Implement vsoxseg/vsuxseg intrinsics..
HsiangKai edited the summary of this revision. (Show Details)
  • Update to v1.0.

Put test cases to D95194, D95195, D95196, and D95197.

This revision was landed with ongoing or failed builds.Jan 22 2021, 4:56 PM
This revision was automatically updated to reflect the committed changes.