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[RISCV] Implement vloxseg/vluxseg intrinsics.
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Authored by HsiangKai on Jan 18 2021, 3:04 AM.

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Summary

Define vloxseg/vluxseg intrinsics and pseudo instructions. Lower vloxseg/vluxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

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Event Timeline

HsiangKai created this revision.Jan 18 2021, 3:04 AM
HsiangKai requested review of this revision.Jan 18 2021, 3:04 AM
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HsiangKai updated this revision to Diff 317752.Jan 19 2021, 7:00 PM

Add test cases for rv32. It does not contain all combinations of vlxseg due to the revision will be too large to upload.

craig.topper added inline comments.Jan 20 2021, 8:00 PM
llvm/include/llvm/IR/IntrinsicsRISCV.td
546

index->indexed

553

index->indexed

1028

Make this a FIXME or TODO

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
3035

Make this a FIXME or TODO

Does this need earlyclobber? The spec says "For vector indexed segment loads, the destination vector register groups cannot overlap the source vector register group (specified by vs2), else an illegal instruction exception is raised."

HsiangKai updated this revision to Diff 318198.Jan 21 2021, 7:28 AM
HsiangKai marked 4 inline comments as done.
craig.topper added inline comments.Jan 21 2021, 10:26 AM
llvm/test/CodeGen/RISCV/rvv/vlxseg-rv32.ll
12 ↗(On Diff #318198)

This violates "For vector indexed segment loads, the destination vector register groups cannot overlap the source vector register group (specified by vs2), else an illegal instruction exception is raised." right?

HsiangKai updated this revision to Diff 318385.Jan 21 2021, 6:42 PM
HsiangKai retitled this revision from [RISCV] Implement vlxseg intrinsics. to [RISCV] Implement vloxseg/vluxseg intrinsics..
HsiangKai edited the summary of this revision. (Show Details)
This revision is now accepted and ready to land.Jan 22 2021, 10:02 AM
This revision was automatically updated to reflect the committed changes.