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[AMDGPU] Fix FP/BP spills when MUBUF constant offset exceeded
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Authored by kerbowa on Aug 11 2020, 12:51 PM.

Details

Summary

If we need a scratch register for the spill don't use the same scratch
register that is being used for the MBUF offset.

Diff Detail

Event Timeline

kerbowa created this revision.Aug 11 2020, 12:51 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 11 2020, 12:51 PM
kerbowa requested review of this revision.Aug 11 2020, 12:51 PM
arsenm added inline comments.Aug 11 2020, 12:56 PM
llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
559

Can you add a comment explaining the point of the test?

llvm/test/CodeGen/AMDGPU/stack-realign.ll
258

Typo avaialbe

282

You can shrink the register list with amdgpu-waves-per-eu to restrict the number of registers

kerbowa updated this revision to Diff 285426.Aug 13 2020, 10:52 AM

As discussed offline with Mahesha, this and https://reviews.llvm.org/D85767 are fixing the same issue, we decided I would take the fix forward.

kerbowa updated this revision to Diff 285432.Aug 13 2020, 11:08 AM

Fix typo.

arsenm accepted this revision.Aug 13 2020, 1:06 PM

LGTM with test nit. We should probably consider just walking LivePhysRegs over the newly inserted instructions to avoid this kind of issue in the future

llvm/test/CodeGen/AMDGPU/stack-realign.ll
332

I would like to eventually eliminate amdgpu-num-vgpr, so expressing the closest in terms of amdgpu-waves-per-eu is somewhat preferable

This revision is now accepted and ready to land.Aug 13 2020, 1:06 PM