Page MenuHomePhabricator

[WIP][RISCV][GlobalISel] Legalize types for ALU operations
Needs ReviewPublic

Authored by lewis-revill on Mar 18 2020, 4:35 AM.



This patch legalizes ALU operations according to operations supported natively by RISC-V. This includes necessary lowering for sign extend and zero extend operations on smaller types, allowing single word operations where supported on RV64, and split operations on double XLen types where appropriate. Libcalls are utilized where hardware does not support an operation and/or type (specifically for M-extension operations).

Diff Detail

Event Timeline

lewis-revill created this revision.Mar 18 2020, 4:35 AM

Fix copy/paste mistakes in check lines

lewis-revill edited the summary of this revision. (Show Details)

Add XLenLLT, take into account M extension.

Joe added a comment.Mar 20 2020, 7:29 AM

What about G_OR and G_XOR? Is there a reason why they're not listed?

Support AND/OR/XOR.

Joe added a comment.Apr 8 2020, 6:04 AM

LGTM, but probably wait for someone more experienced to upvote :)

arsenm added a subscriber: arsenm.Apr 8 2020, 7:00 AM
arsenm added inline comments.

returning false here is entirely pointless, you can just delete this


You don't need the IR section here

Removed unnecessary line

lewis-revill marked an inline comment as done.Apr 10 2020, 1:14 AM
lewis-revill added inline comments.

I didn't realise this, though I'm considering leaving it for consistency with tests in other backends? Also I am going to look into using the update_mir_test_checks tool instead.

Use utils/

lewis-revill edited the summary of this revision. (Show Details)

Expand patch to correctly cover more methods of types being legalized - IE: single word instructions on RV64, split operations (add with carry etc.) and libcalls up to s128.

lewis-revill added inline comments.Apr 16 2020, 9:15 AM

Currently RISC-V defines signext_inreg as legal when we know that the inner type is i32. However with GlobalISel there is no way to retrieve the inner type to define legality, as the action of G_SEXT_INREG is determined by an immediate operand.

I was currently in the process of rewriting these patches to properly handle single word operations on RV64, of which ADDW, SUBW and MULW rely on pattern matching an i32 to i64 signext_inreg of the corresponding operation. Though since we cannot allow the G_SEXT_INREG to survive correctly I feel the only option for now may be to directly select these instructions at the legalization stage.

Add testing for shifts. Include a version of handling single word operations on RV64 involving directly lowering to the final opcode.

Tweak test order

Add target flags to calls in tests.

lenary resigned from this revision.Jan 14 2021, 10:10 AM
rkruppe removed a subscriber: rkruppe.Jan 14 2021, 10:19 AM