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[AArch64] Lower vector trunc using tbl.
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Authored by fhahn on Sep 8 2022, 7:52 AM.

Details

Summary

Similar to using tbl to lower vector ZExts, tbl4 can be used to lower
vector truncates.

The initial version support i32->i8 conversions.

Depends on D120571

Diff Detail

Event Timeline

fhahn created this revision.Sep 8 2022, 7:52 AM
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fhahn requested review of this revision.Sep 8 2022, 7:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 8 2022, 7:52 AM
t.p.northover added inline comments.Sep 15 2022, 2:57 AM
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
13216–13217

Further to our big-endian discussion, I think this bitcast will put the least significant byte into elements 3, 7, 11, 15. So the for loop below should account for that.

13289

Shouldn't this be part of the patch that adds the code above?

13292

Destination type wrong.

fhahn updated this revision to Diff 460402.Sep 15 2022, 7:28 AM
fhahn marked an inline comment as done.

Thanks Tim, I updated the code to account for big-endian targets by adjusting the mask as suggested offline.

fhahn marked 2 inline comments as done.Sep 15 2022, 7:30 AM
fhahn added inline comments.
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
13216–13217

Thanks, I adjusted the loop below to use Idx+3 for the mask to account for that on big-endian.

13289

Yes, moved to D133494.

13292

Thanks, should be fixed!

t.p.northover accepted this revision.Sep 16 2022, 1:25 AM

Thanks Florian, think this one looks good now.

This revision is now accepted and ready to land.Sep 16 2022, 1:25 AM
This revision was landed with ongoing or failed builds.Sep 16 2022, 4:43 AM
This revision was automatically updated to reflect the committed changes.
fhahn marked 2 inline comments as done.