Add a LLT variant of allowsMemoryAccess. This is the same as the DAGCombiner check.
Add a testcase that shows that when we have strict-align, the combine only fires when the resulting load will be aligned.

Fri, Jan 15, 4:25 PM · Restricted Project

paquette committed rGcc90d41945f6: [MIPatternMatch] Add m_OneNonDBGUse (authored by paquette).

[MIPatternMatch] Add m_OneNonDBGUse

Fri, Jan 15, 10:19 AM

paquette closed D94705: [MIPatternMatch] Add m_OneNonDBGUse.

Fri, Jan 15, 10:19 AM · Restricted Project

Thu, Jan 14

paquette accepted D94701: [AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions..

LGTM

Thu, Jan 14, 12:19 PM · Restricted Project

paquette accepted D94702: [AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP..

LGTM

Thu, Jan 14, 12:15 PM · Restricted Project

paquette updated the diff for D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

Use m_OneNonDBGUse (D94705)

Thu, Jan 14, 12:12 PM · Restricted Project

paquette requested review of D94705: [MIPatternMatch] Add m_OneNonDBGUse.

Thu, Jan 14, 12:05 PM · Restricted Project

paquette added a comment to D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

In D94350#2496310, @aemerson wrote:

We also need to check for the strict-align function attribute before we generate wider loads.

Thu, Jan 14, 12:02 PM · Restricted Project

paquette added a comment to D94641: [AArch64][GlobalISel] Use wzr/xzr for FP stores of zero.

In D94641#2498944, @aemerson wrote:

It it possible to extend the existing combine in prelegalizer combiner to handle this too? Or will that cause us to still miss some cases?

Thu, Jan 14, 11:36 AM · Restricted Project

paquette added a comment to D94641: [AArch64][GlobalISel] Use wzr/xzr for FP stores of zero.

A better, more general solution might be to move some of the G_FCONSTANT selection code into the legalizer or post-legalizer lowering. That might make some of the selection code which relies on seeing a G_FCONSTANT more difficult to get right though.

Thu, Jan 14, 10:04 AM · Restricted Project

paquette added a comment to D94641: [AArch64][GlobalISel] Use wzr/xzr for FP stores of zero.

In D94641#2497021, @aemerson wrote:

Why is this in lowering instead of combine?

Thu, Jan 14, 9:52 AM · Restricted Project

Wed, Jan 13

paquette requested review of D94641: [AArch64][GlobalISel] Use wzr/xzr for FP stores of zero.

Wed, Jan 13, 4:26 PM · Restricted Project

paquette added inline comments to D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

Wed, Jan 13, 11:27 AM · Restricted Project

Tue, Jan 12

paquette updated the diff for D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

Fix a bug in isPredecessor exposed by this patch and add a testcase for it. It wasn't able to handle the case where DefMI is the first instruction in the block.

Tue, Jan 12, 3:28 PM · Restricted Project

paquette committed rGddcb0aae8b0d: [MIPatternMatch] Add matcher for G_PTR_ADD (authored by paquette).

[MIPatternMatch] Add matcher for G_PTR_ADD

Tue, Jan 12, 3:23 PM

paquette closed D94348: [MIPatternMatch] Add matcher for G_PTR_ADD.

Tue, Jan 12, 3:23 PM · Restricted Project

paquette added a comment to D94350: [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load.

In D94350#2494066, @aemerson wrote:

In D94350#2493991, @paquette wrote:

Avg regs/missed combine is the number of registers in RegsToVisit when the combine misses

Does this metric count the misses where there were no registers?