Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

[dsanders]

Summary

This is the first patch in the series to migrate Triple's (which are ambiguous)
to TargetTuple's (which aren't).

For the moment, TargetTuple simply passes all requests to the Triple object it
holds. Once it has replaced Triple, it will start to implement the interface in
a more suitable way.

This change makes some changes to the public C++ API. In particular,
InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer()
now take TargetTuples instead of Triples. The other public C++ API's have
been left as-is for the moment to reduce patch size.
Clang and other in-tree tools will be updated with a trivial patch when
this is committed.

[rengolin]

Hi Daniel,

I have only looked at the header and implementation of TargetTuple, and I have a few comments on comments. :)

I'll continue looking at the other changes in due time.

cheers,
--renato

include/llvm/ADT/TargetTuple.h

39 ↗

(On Diff #29111)

I absolutely agree!

65 ↗

(On Diff #29111)

This has to go soon. Please add a FIXME to make sure we merge this into arm/armeb.

87 ↗

(On Diff #29111)

These enums will become authoritative once Triple is gone.

Even if we don't remove Triple forever, it must use these, and not its own, anyway.

210 ↗

(On Diff #29111)

I don't think we should encourage people re-writing the constructor, or it would be a nightmare to investigate issues.

One could use the default constructor and set ABI to 32-bits later, which would be a simpler patch to keep for both vendor and community.

284 ↗

(On Diff #29111)

why two?

lib/Support/TargetTuple.cpp

16 ↗

(On Diff #29111)

// FIXME: These should go as soon as Triple is dead

Just to be sure people don't come here and say "OMG! WTF?".

[rengolin]

Phew! Ok, looks ok to me, with the comments.

About the Tuple+CPU+Features (and others), unless you're planning to do that move in this streak, I think it'd be best to keep a small FIXME comment to use CPU/Features/Options in the Tuple itself.

include/llvm/Support/TargetRegistry.h

119 ↗

(On Diff #29111)

I think this one deserves a FIXME. CPU should be already uniquely identifiable in the tuple.

351 ↗

(On Diff #29111)

Same here. I'd expect (in the future) something like this:

TargetTuple Tuple (Triple(TT)); // Triple for now, TT directly later
Tuple.setCPU(CPU);
Tuple.setFeatures(Features);
return MCSubtargetInfoCtorFn(Tuple);

[dsanders]

include/llvm/ADT/TargetTuple.h

87 ↗

(On Diff #29111)

Ok, I'll drop the FIXME for these but keep the one for ArchType for now.

210 ↗

(On Diff #29111)

This is trying to account for configure-option ambiguity in the GNU triples. For GCC, it's fairly common for distributors to change the meanings of triples using options like --with-arch, --with-cpu, --with-abi, etc. There are some target-specific options such as --with-mode to select ARM/Thumb by default and --with-nan for MIPS NAN encoding selection. I'm not sure about other targets but the MIPS options are in very common use and is likely to get more common in the near future as we try to push towards IEEE754(2008) being the conventional floating point standard on our target (we're still on 1985 for the majority of software).

The thinking behind this comment is that that distributors need to do this kind of thing to make LLVM's GNU triples consistent with the rest of their distribution. We can therefore save ourselves a fair bit of pain by nominating the right place to do it. The advantage, is that LLVM (and related tools) can be made to have the same Triple meaning as the rest of the distribution. The downside is that, as you say, it makes investigating issues more difficult on distributions that do change it since they'll have a different default TargetTuple for the same Triple. TargetTuples are still unique and authoratative so we can compensate for this by using the tuple to investigate issues, effectively bypassing any customizations the distributor made in this constructor. Frontends may need to add command line options to allow TargetTuple's (or we could claim an unused subset of the triple strings) but that should be easy. We don't need to do the same thing for backends/LTO since we'll need the TargetTuple to be serialized in the LLVM-IR to avoid information loss anyway.

284 ↗

(On Diff #29111)

At the moment, its just to preserve Triple's interface which had both. I've been rewriting instances of .getTriple() to .str() as I notice them. At some point, I'd like to rewrite the remainder and delete getTriple().

Triple::getTriple() is fairly common, but it's also the least clear of the two. The name sounds like it ought to return 'this' :-)

lib/Support/TargetTuple.cpp

16 ↗

(On Diff #29111)

Sure, I've paraphrased a bit in the update (which I'll post shortly) since it's really about replacing the Triple member (GnuTT).

[dsanders]

About the Tuple+CPU+Features (and others), unless you're planning to do that move in this streak, I think it'd be best to keep a small FIXME comment to use CPU/Features/Options in the Tuple itself.

I'm not planning to merge CPU name and Features into the TargetTuple in this series, but I probably should do this at some point. I'll add some FIXME's for now

include/llvm/Support/TargetRegistry.h

119 ↗

(On Diff #29111)

CPU should be already uniquely identifiable in the tuple.

I don't think that's true at the moment since Triples/TargetTuples lack the variety of values that the CPU name has. For example, -mcpu=pentium would cause CPU to be 'pentium' but the Triple/TargetTuple doesn't know about this string.

Are you thinking of the SubArch field that ARM and Kalimba use?

[echristo]

Wait, can you give a rundown of what your TargetTuple is doing etc? Maybe a
mail to the list? This seems weird.

Thanks!

-eric

[rengolin]

In D10969#200483, @echristo wrote:

Wait, can you give a rundown of what your TargetTuple is doing etc? Maybe a
mail to the list? This seems weird.

Hi Eric,

This is an old project (5+ years) that is finally realising, and had many threads in the list (maybe not with "TargetTuple" in it). Daniel is working towards that goal for some good weeks now, but if you feel we need another round, I think we better have it. I want everyone to be on the same boat as we thread these dangerous waters.

Maybe Daniel would be a better person to write up a summary of the changes so far and the plan for the future, as I was more focused on the TargetParser changes.

cheers,
--renato

include/llvm/ADT/TargetTuple.h

210 ↗

(On Diff #29111)

Fair enough.

284 ↗

(On Diff #29111)

Ok.

[dsanders]

Ok, I'll post a write up of the problem(s) with GNU Triples and the planned solution in the morning.

[echristo]

Excellent. Thanks Daniel!

-eric

[dsanders]

Added/removed FIXME comments

[dsanders]

@echristo: Have you had chance to read the "The Trouble with Triples" thread? Do you still have concerns?

include/llvm/ADT/TargetTuple.h

210 ↗

(On Diff #29111)

I've left the paragraph about patching the constructor in for the moment but I've added a fixme indicating that it will be replaced by CMake/config-files asap. Is that ok for this patch?

[dsanders]

Refreshed patch and ping.
Removed paragraph about patching the TargetTuple constructor.

@echristo: Did the 'The Trouble with Triples' thread resolve everything for you?
I'm a bit stuck at the moment since without further comments I have no obvious
course of action to make progress with this patch series.

[dsanders]

Ping

It's been three weeks since I posted the explanation on LLVMdev and Eric hasn't said whether the thread satisfied him or not. I'm not sure what to do at this point since this patch appears to be blocked on the "Could you explain? This seems weird" comment but I don't seem to have any means of unblocking it beyond what I've already done.
The patch series queued behind this is difficult to maintain so I'd greatly appreciate advice on how I can unblock this.

[rengolin]

Have you tried pinging Eric on IRC? That usually helps a lot.

[dsanders]

Not yet. I haven't used IRC for a very long time (>10 years) but I can get it set up and try that.

[echristo]

I'm here, just been very busy. I'll get to it today.

-eric

[dsanders]

Thanks.

---

From: Eric Christopher [[e-mail]]
Sent: 28 July 2015 16:37
To: Daniel Sanders; [e-mail]
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: Re: [PATCH] D10969: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

I'm here, just been very busy. I'll get to it today.

-eric

[dsanders]

Refresh patch

[dsanders]

Refresh and ping.

[dsanders]

This project has stalled for a while so to try to get things moving again: The llvmdev thread goes into more detail but the major goals of the project this patch is part of include:

• Fix the incorrect assumption that GNU triples describe a single specific target.
• Allow vendors/distributions to configure the triple meanings to suit their target. Different vendors/distributions often have conflicting meanings for the same triple and the meanings change over time
• Minimize the amount of LLVM that needs to be aware of GNU triple ambiguity (same triple but different meaning).
• Minimize the amount of LLVM that needs to be aware of GNU triple aliases (different triple but same meaning).
• Minimize the occasions where the GNU triple is parsed.

ARM and Mips are the main beneficiaries of this since our respective toolchain histories have made our GNU triples a big mess of ambiguity and inconsistency. However, other architectures (including X86) also share these problems to varying degrees.

The high level plan that was discussed in the 'The Trouble With Triples' thread was:

1. Replace any remaining std::string's and StringRef's containing GNU triples with Triple objects.
2. Split the llvm::Triple class into llvm::Triple and llvm::TargetTuple classes. Both are identical in implementation and almost identical in interface at this stage.
3. Gradually replace Triples with TargetTuples until the C APIs and the LLVM-IR are the only place inside LLVM where Triples are still used.
4. Change the implementation of TargetTuple to whatever is convenient for LLVM's internals and decide on a serialization.
5. Replace serialized Triples with serialized TargetTuples in LLVM-IR. a. Maintain backwards compatibility with IR using triples, at least for a while.
6. Add TargetTuple support to the C API. Exact API is t.b.d.
7. Have the API users mutate the TargetTuple appropriately.

Step 5 was a little controversial on that thread, but it's not a significant change to the plan to keep the GNU triple around for LLVM-IR's purposes.

This patch is step 2 and the first piece of step 3. My current branch has ~90% of step 3 complete and can be found at https://github.com/dsandersimgtec/llvm/tree/triple-trouble if you'd like to peek at some of the patches that will follow this one.

[rengolin]

Hi Daniel,

For what it is, the patch looks good to me.

It's a big mechanical patch that implements a Tuple wrapper to Triple and change all places that used to use Triples. I don't expect it to clean up anything, since for now we're just moving things alone, but would be good to make Triple use the Tuple enums before deprecating it, so that you can remove a lot of code inserted by this patch.

If people feel uncomfortable with so much being added spuriously, maybe you could have a go at doing that change now. But I don't think it's strictly necessary and will leave at your discretion. We need to move this thing forward as it has taken too long and too much of the ARM and MIPS architectural support depends on this.

Not that this could change anything anywhere else, but It'd be good to have other back-end owners to agree, since this is a big change. I believe most people are copied in this review, anyway, and had time enough to care.

[echristo]

I'm sorry for all the delays, I'm trying to get back to this and haven't forgotten it (or the other thread). My apologies.

-eric

[dsanders]

Thanks Renato.

I don't expect it to clean up anything, since for now we're just moving things alone, but would be good to make Triple use the Tuple enums before deprecating it, so that you can remove a lot of code inserted by this patch.

We'd want to bring back separate enums eventually (see below) but if deferring that piece helps get the overall patch series moving then I don't mind doing that.

The reason for separating the enums is that it's desirable for Triple and TargetTuple to have different sets of values, particularly for ARM and Mips. By the end of the project, Triple's values should be focused on representing the triple, and TargetTuple's values should be focused on representing the target. For example, it's correct for mipsel-linux-gnu that Triple::getArch() returns Triple::mipsel. However, it's also desirable that TargetTuple::getArch() return TargetTuple::mips and TargetTuple::getEndian() return TargetTuple::LittleEndian. To put it another way, Triple's enum are more-or-less numeric representations of the input string, whereas TargetTuple's enums are representations of the intended target.

I don't know the ARM triples but here's an example based on what I've seen in your target parser work: Triple::getArch() should return Triple::armv7 for armv7-linux-gnu, while TargetTuple::getArch() would return TargetTuple::arm, and TargetTuple::getSubArch() would return TargetTuple::v7. Does that agree with your understanding of ARM triples?

From Eric's comment:

I'm sorry for all the delays, I'm trying to get back to this and haven't forgotten it (or the other thread). My apologies.

I don't want to pressure you as I know you're busy but could you be a little more specific than that? My biggest worry is that the issues this project resolves are blocking our toolchain products and while the schedule for some of those feels like a long time, I'm also concious of the fact that sorting these issues out is a multi-month project.

[rengolin]

In D10969#243155, @dsanders wrote:

The reason for separating the enums is that it's desirable for Triple and TargetTuple to have different sets of values, particularly for ARM and Mips. By the end of the project, Triple's values should be focused on representing the triple, and TargetTuple's values should be focused on representing the target. For example, it's correct for mipsel-linux-gnu that Triple::getArch() returns Triple::mipsel. However, it's also desirable that TargetTuple::getArch() return TargetTuple::mips and TargetTuple::getEndian() return TargetTuple::LittleEndian. To put it another way, Triple's enum are more-or-less numeric representations of the input string, whereas TargetTuple's enums are representations of the intended target.

You're absolutely right, and that's why I ended up creating my own enums in the TargetParser.

I don't know the ARM triples but here's an example based on what I've seen in your target parser work: Triple::getArch() should return Triple::armv7 for armv7-linux-gnu, while TargetTuple::getArch() would return TargetTuple::arm, and TargetTuple::getSubArch() would return TargetTuple::v7. Does that agree with your understanding of ARM triples?

Yes. Moreover, the sub-arch should be an identifier for a set of default features + allowed features, that can be enabled/disabled via other flags. The fact that the mapping between CPU and Arch is not injectve nor surjective makes the meaning of arch and subarch very subjective. :)

[dsanders]

(apologies if this double-posts, it seems Phabricator just died)

I've committed this (along with the trivial clang patch) in r247683 on the grounds that I have Renato's LGTM and I don't have any pending review comments. It doesn't seem reasonable to continue to wait for Eric with no indication of when he might be able to take a look at it. For the record, I've been waiting since July and my request last week for an indication as to when he might find time has not been replied to. Of course, post-commit review comments are still welcome and I'm happy to follow up on them.

[echristo]

I started a reply yesterday actually and I'm sorry I didn't finish it.
Briefly I don't think this is the right direction and I don't think you've
explained why this is the right direction. The serialization that you have
planned is insufficient and doesn't take into account portability, I don't
like the idea of using global metadata for it and you haven't explained why
this is acceptable. I actually was spending a non-trivial amount of time
trying to design a way for this to work along side the assembler and main
compiler (which I don't think you've bothered to try to do)

Please revert this immediately.

-eric

[dsanders]

I started a reply yesterday actually and I'm sorry I didn't finish it.

Briefly I don't think this is the right direction and I don't think you've explained why this is the right direction.

The serialization that you have planned is insufficient and doesn't take into account portability

I don't like the idea of using global metadata for it and you haven't explained why this is acceptable

---

From: Eric Christopher [[e-mail]]
Sent: 15 September 2015 16:56
To: Daniel Sanders; [e-mail]; [e-mail]
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: Re: [PATCH] D10969: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

I started a reply yesterday actually and I'm sorry I didn't finish it. Briefly I don't think this is the right direction and I don't think you've explained why this is the right direction. The serialization that you have planned is insufficient and doesn't take into account portability, I don't like the idea of using global metadata for it and you haven't explained why this is acceptable. I actually was spending a non-trivial amount of time trying to design a way for this to work along side the assembler and main compiler (which I don't think you've bothered to try to do)

Please revert this immediately.

-eric

[dsanders]

Sorry, I accidentally hit Ctrl+Enter. My next email will contain a reply :-)

---

From: Daniel Sanders
Sent: 15 September 2015 17:05
To: Eric Christopher; [e-mail]; [e-mail]
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: RE: [PATCH] D10969: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

I started a reply yesterday actually and I'm sorry I didn't finish it.

Briefly I don't think this is the right direction and I don't think you've explained why this is the right direction.

The serialization that you have planned is insufficient and doesn't take into account portability

I don't like the idea of using global metadata for it and you haven't explained why this is acceptable

---

From: Eric Christopher [[e-mail]]
Sent: 15 September 2015 16:56
To: Daniel Sanders; [e-mail]; [e-mail]
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: Re: [PATCH] D10969: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

I started a reply yesterday actually and I'm sorry I didn't finish it. Briefly I don't think this is the right direction and I don't think you've explained why this is the right direction. The serialization that you have planned is insufficient and doesn't take into account portability, I don't like the idea of using global metadata for it and you haven't explained why this is acceptable. I actually was spending a non-trivial amount of time trying to design a way for this to work along side the assembler and main compiler (which I don't think you've bothered to try to do)

Please revert this immediately.

-eric

[echristo]

I've replied in a different thread with what I see is the design that needs
to happen here.

-eric

[echristo]

BTW I do agree that it's completely unreasonable how long it's taken me on
this. I do truly apologize, it was only when looking at the recent patch
dealing with ABIInfo that you approved that I realized what you're trying
to deal with in this and how it's interacting with everything else. It's
absolutely needed so let's discuss and move this forward.

-eric

[dsanders]

Thanks for the reply. We should hold the main conversation in the llvmdev thread but to briefly reply here.

Briefly I don't think this is the right direction and I don't think you've explained why this is the right direction.

Do you at least accept that Triples are not usable as a way to describe the target? and that they are ambiguous and inconsistent in their meanings?

The serialization that you have planned is insufficient and doesn't take into account portability

The exact serialization doesn't matter too much so long as there's room to grow it. Both my original string representation and the metadata approach that was later proposed have this capability.

I don't like the idea of using global metadata for it and you haven't explained why this is acceptable

FWIW, my original proposal was a 'target tuple' statement to match the 'target triple' one we have today. Whatever serialization approach we choose doesn't significantly change the overall direction and has no effect on the current phase of the project. There's no need to block the early phases of the project on small details of the later phases.

I actually was spending a non-trivial amount of time trying to design a way for this to work along side the assembler and main compiler (which I don't think you've bothered to try to do)

What makes you say I haven't bothered to design a way to work with the assembler and the main compiler? That's one of the core concepts driving the work and working compatibly with other toolchains is the objective.

---

From: Eric Christopher [[e-mail]]
Sent: 15 September 2015 16:56
To: Daniel Sanders; [e-mail]; [e-mail]
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: Re: [PATCH] D10969: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

I started a reply yesterday actually and I'm sorry I didn't finish it. Briefly I don't think this is the right direction and I don't think you've explained why this is the right direction. The serialization that you have planned is insufficient and doesn't take into account portability, I don't like the idea of using global metadata for it and you haven't explained why this is acceptable. I actually was spending a non-trivial amount of time trying to design a way for this to work along side the assembler and main compiler (which I don't think you've bothered to try to do)

Please revert this immediately.

-eric

[dsanders]

BTW I do agree that it's completely unreasonable how long it's taken me on this. I do truly apologize, ...

Thanks. I appreciate that.

---

From: Eric Christopher [[e-mail]]
Sent: 15 September 2015 17:27
To: Daniel Sanders; [e-mail]; [e-mail]
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: Re: [PATCH] D10969: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

BTW I do agree that it's completely unreasonable how long it's taken me on this. I do truly apologize, it was only when looking at the recent patch dealing with ABIInfo that you approved that I realized what you're trying to deal with in this and how it's interacting with everything else. It's absolutely needed so let's discuss and move this forward.

-eric

[dsanders]

Briefly I don't think this is the right direction and I don't think you've explained why this is the right direction.

Do you at least accept that Triples are not usable as a way to describe the target? and that they are ambiguous and inconsistent in their meanings?

I think that they're insufficient to fully describe a target given command line options that can change defaults is a better way of putting it.

Ok, so we've got some agreement on this point. Most of the thinking follows on from here.

I would say that the Triples are insufficient as a starting point too but we can follow that thread on the llvm-dev thread.

I don't like the idea of using global metadata for it and you haven't explained why this is acceptable

FWIW, my original proposal was a 'target tuple' statement to match the 'target triple' one we have today.
Whatever serialization approach we choose doesn't significantly change the overall direction and has no
effect on the current phase of the project. There's no need to block the early phases of the project on small
details of the later phases.

Sure, as long as the general direction seems good. IR level serialization of things is ... touchy and I'd like to
make sure that we get something there that we're going to be happy with long term given the stability
guarantees. It's easier to define things on the side that can change rather than make a mistake at the IR level
in a way that's not easy to upgrade. (Which we'll also need for any triple change as well).

Fair enough. I was expecting the IR change to be the first major debate on the implementation detail. My current patch series stops just before it for this reason.

I actually was spending a non-trivial amount of time trying to design a way for this to work along side the assembler and main compiler (which I don't think you've bothered to try to do)

What makes you say I haven't bothered to design a way to work with the assembler and the main compiler?
That's one of the core concepts driving the work and working compatibly with other toolchains is the objective.

I think it's trying to solve a problem in the assembler interfaces, but from the wrong tack. I hope I explained it in one of my followups.

Yes, but not only that. It's trying to solve several big issues simultaneously since they have a common origin point even though the causes are different.

---

From: Eric Christopher [[e-mail]]
Sent: 15 September 2015 17:35
To: Daniel Sanders; [e-mail]; [e-mail]
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: Re: [PATCH] D10969: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

cfe/trunk/lib/Parse/ParseStmtAsm.cpp

StmtResult Parser::ParseMicrosoftAsmStatement(SourceLocation AsmLoc) {
   std::unique_ptr<llvm::MCAsmParser> Parser(
       createMCAsmParser(TempSrcMgr, Ctx, *Str.get(), *MAI));
 
   // FIXME: init MCOptions from sanitizer flags here.
   llvm::MCTargetOptions MCOptions;
   std::unique_ptr<llvm::MCTargetAsmParser> TargetParser(
       TheTarget->createMCAsmParser(*STI, *Parser, *MII, MCOptions));
 
-  std::unique_ptr<llvm::MCInstPrinter> IP(
-      TheTarget->createMCInstPrinter(llvm::Triple(TT), 1, *MAI, *MII, *MRI));
+  std::unique_ptr<llvm::MCInstPrinter> IP(TheTarget->createMCInstPrinter(
+      llvm::TargetTuple(llvm::Triple(TT)), 1, *MAI, *MII, *MRI));
 
   // Change to the Intel dialect.
   Parser->setAssemblerDialect(1);
   Parser->setTargetParser(*TargetParser.get());
   Parser->setParsingInlineAsm(true);
   TargetParser->setParsingInlineAsm(true);
 
   ClangAsmParserCallback Callback(*this, AsmLoc, AsmString, AsmToks,

cfe/trunk/tools/driver/cc1as_main.cpp

std::unique_ptr<MCSubtargetInfo> STI(
       TheTarget->createMCSubtargetInfo(Opts.Triple, Opts.CPU, FS));
 
   raw_pwrite_stream *Out = FDOS.get();
   std::unique_ptr<buffer_ostream> BOS;
 
   // FIXME: There is a bit of code duplication with addPassesToEmitFile.
   if (Opts.OutputType == AssemblerInvocation::FT_Asm) {
     MCInstPrinter *IP = TheTarget->createMCInstPrinter(
-        llvm::Triple(Opts.Triple), Opts.OutputAsmVariant, *MAI, *MCII, *MRI);
+        llvm::TargetTuple(llvm::Triple(Opts.Triple)), Opts.OutputAsmVariant,
+        *MAI, *MCII, *MRI);
     MCCodeEmitter *CE = nullptr;
     MCAsmBackend *MAB = nullptr;
     if (Opts.ShowEncoding) {
       CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
       MAB = TheTarget->createMCAsmBackend(*MRI, Opts.Triple, Opts.CPU);
     }
     auto FOut = llvm::make_unique<formatted_raw_ostream>(*Out);
     Str.reset(TheTarget->createAsmStreamer(
         Ctx, std::move(FOut), /*asmverbose*/ true,
         /*useDwarfDirectory*/ true, IP, CE, MAB, Opts.ShowInst));
   } else if (Opts.OutputType == AssemblerInvocation::FT_Null) {
     Str.reset(createNullStreamer(Ctx));
   } else {
     assert(Opts.OutputType == AssemblerInvocation::FT_Obj &&
            "Invalid file type!");
     if (!FDOS->supportsSeeking()) {
       BOS = make_unique<buffer_ostream>(*FDOS);
       Out = BOS.get();
     }
 
     MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
     MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, Opts.Triple,
                                                       Opts.CPU);
-    Triple T(Opts.Triple);
-    Str.reset(TheTarget->createMCObjectStreamer(T, Ctx, *MAB, *Out, CE, *STI,
-                                                Opts.RelaxAll,
-                                                /*DWARFMustBeAtTheEnd*/ true));
+    Triple TT(Opts.Triple);
+    Str.reset(TheTarget->createMCObjectStreamer(
+        llvm::TargetTuple(TT), Ctx, *MAB, *Out, CE, *STI, Opts.RelaxAll,
     Str.get()->InitSections(Opts.NoExecStack);
   }
 
   bool Failed = false;
 
   std::unique_ptr<MCAsmParser> Parser(
       createMCAsmParser(SrcMgr, Ctx, *Str.get(), *MAI));
 

llvm/trunk/include/llvm/ADT/TargetTuple.h

+//===-- llvm/ADT/TargetTuple.h - Target tuple class -------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// @file
+/// This file contains the definitions for TargetTuples which describe the
+/// target in a unique unambiguous way. This is in contrast to the GNU triples
+/// handled by the Triple class which are more of a guideline than a
+/// description and whose meaning can be overridden by vendors and distributors.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_ADT_TARGETTUPLE_H
+#define LLVM_ADT_TARGETTUPLE_H
+
+#include "llvm/ADT/Twine.h"
+#include "llvm/ADT/Triple.h"
+
+// Some system headers or GCC predefined macros conflict with identifiers in
+// this file.  Undefine them here.
+#undef NetBSD
+#undef mips
+#undef sparc
+
+namespace llvm {
+
+/// TargetTuple is currently a proxy for Triple but will become an unambiguous,
+/// authoratitive, and mutable counterpart to the GNU triples handled by Triple.
+class TargetTuple {
+public:
+  // FIXME: Don't duplicate Triple::ArchType. It's worth mentioning that these
+  //        these values don't have to match Triple::ArchType. For example, it
+  //        would be fairly sensible to have a single 'mips' architecture and
+  //        distinguish endianness and ABI elsewhere.
+  enum ArchType {
+    UnknownArch,
+
+    arm,        // ARM (little endian): arm, armv.*, xscale
+    armeb,      // ARM (big endian): armeb
+    aarch64,    // AArch64 (little endian): aarch64
+    aarch64_be, // AArch64 (big endian): aarch64_be
+    bpfel,      // eBPF or extended BPF or 64-bit BPF (little endian)
+    bpfeb,      // eBPF or extended BPF or 64-bit BPF (big endian)
+    hexagon,    // Hexagon: hexagon
+    mips,       // MIPS: mips, mipsallegrex
+    mipsel,     // MIPSEL: mipsel, mipsallegrexel
+    mips64,     // MIPS64: mips64
+    mips64el,   // MIPS64EL: mips64el
+    msp430,     // MSP430: msp430
+    ppc,        // PPC: powerpc
+    ppc64,      // PPC64: powerpc64, ppu
+    ppc64le,    // PPC64LE: powerpc64le
+    r600,       // R600: AMD GPUs HD2XXX - HD6XXX
+    amdgcn,     // AMDGCN: AMD GCN GPUs
+    sparc,      // Sparc: sparc
+    sparcv9,    // Sparcv9: Sparcv9
+    sparcel,    // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
+    systemz,    // SystemZ: s390x
+    tce,        // TCE (http://tce.cs.tut.fi/): tce
+                // FIXME: thumb/thumbeb will be merged into arm/armeb soon.
+    thumb,      // Thumb (little endian): thumb, thumbv.*
+    thumbeb,    // Thumb (big endian): thumbeb
+    x86,        // X86: i[3-9]86
+    x86_64,     // X86-64: amd64, x86_64
+    xcore,      // XCore: xcore
+    nvptx,      // NVPTX: 32-bit
+    nvptx64,    // NVPTX: 64-bit
+    le32,       // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)
+    le64,       // le64: generic little-endian 64-bit CPU (PNaCl / Emscripten)
+    amdil,      // AMDIL
+    amdil64,    // AMDIL with 64-bit pointers
+    hsail,      // AMD HSAIL
+    hsail64,    // AMD HSAIL with 64-bit pointers
+    spir,       // SPIR: standard portable IR for OpenCL 32-bit version
+    spir64,     // SPIR: standard portable IR for OpenCL 64-bit version
+    kalimba,    // Kalimba: generic kalimba
+    shave,      // SHAVE: Movidius vector VLIW processors
+    wasm32,     // WebAssembly with 32-bit pointers
+    wasm64,     // WebAssembly with 64-bit pointers
+    LastArchType = wasm64
+  };
+
+  enum SubArchType {
+    NoSubArch,
+
+    ARMSubArch_v8_1a,
+    ARMSubArch_v8,
+    ARMSubArch_v7,
+    ARMSubArch_v7em,
+    ARMSubArch_v7m,
+    ARMSubArch_v7s,
+    ARMSubArch_v6,
+    ARMSubArch_v6m,
+    ARMSubArch_v6k,
+    ARMSubArch_v6t2,
+    ARMSubArch_v5,
+    ARMSubArch_v5te,
+    ARMSubArch_v4t,
+
+    KalimbaSubArch_v3,
+    KalimbaSubArch_v4,
+    KalimbaSubArch_v5
+  };
+
+  enum VendorType {
+    UnknownVendor,
+
+    Apple,
+    PC,
+    SCEI,
+    BGP,
+    BGQ,
+    Freescale,
+    IBM,
+    ImaginationTechnologies,
+    MipsTechnologies,
+    NVIDIA,
+    CSR,
+    Myriad,
+    LastVendorType = Myriad
+  };
+
+  enum OSType {
+    UnknownOS,
+
+    CloudABI,
+    Darwin,
+    DragonFly,
+    FreeBSD,
+    IOS,
+    KFreeBSD,
+    Linux,
+    Lv2, // PS3
+    MacOSX,
+    NetBSD,
+    OpenBSD,
+    Solaris,
+    Win32,
+    Haiku,
+    Minix,
+    RTEMS,
+    NaCl, // Native Client
+    CNK,  // BG/P Compute-Node Kernel
+    Bitrig,
+    AIX,
+    CUDA,   // NVIDIA CUDA
+    NVCL,   // NVIDIA OpenCL
+    AMDHSA, // AMD HSA Runtime
+    PS4,
+    LastOSType = PS4
+  };
+
+  enum EnvironmentType {
+    UnknownEnvironment,
+
+    GNU,
+    GNUEABI,
+    GNUEABIHF,
+    GNUX32,
+    CODE16,
+    EABI,
+    EABIHF,
+    Android,
+
+    MSVC,
+    Itanium,
+    Cygnus,
+    AMDOpenCL,
+    CoreCLR,
+    LastEnvironmentType = CoreCLR
+  };
+
+  enum ObjectFormatType {
+    UnknownObjectFormat,
+
+    COFF,
+    ELF,
+    MachO,
+  };
+
+public:
+  /// @name Constructors
+  /// @{
+
+  /// Default constructor leaves all fields unknown.
+  TargetTuple() : GnuTT() {}
+
+  /// Convert a GNU Triple to a TargetTuple.
+  ///
+  /// This conversion assumes that GNU Triple's have a specific defined meaning
+  /// which isn't strictly true. A single Triple can potentially have multiple
+  /// contradictory meanings depending on compiler options and configure-time
+  /// options. Despite this, Triple's do tend to have a 'usual' meaning, or
+  /// rather a default behaviour and this function selects it.
+  ///
+  /// When tool options affect the desired TargetTuple, the tool should obtain
+  /// the usual meaning of the GNU Triple using this constructor and then use
+  /// the mutator methods to apply the tool options.
+  explicit TargetTuple(const Triple &GnuTT) : GnuTT(GnuTT) {}
+
+  /// @}
+  /// @name Typed Component Access
+  /// @{
+
+  /// Get the parsed architecture type of this triple.
+  ArchType getArch() const;
+
+  /// get the parsed subarchitecture type for this triple.
+  SubArchType getSubArch() const;
+
+  /// Get the parsed vendor type of this triple.
+  VendorType getVendor() const;
+
+  /// Get the parsed operating system type of this triple.
+  OSType getOS() const;
+
+  /// Does this triple have the optional environment
+  /// (fourth) component?
+  bool hasEnvironment() const { return GnuTT.hasEnvironment(); }
+
+  /// Get the parsed environment type of this triple.
+  EnvironmentType getEnvironment() const;
+
+  /// Parse the version number from the OS name component of the
+  /// triple, if present.
+  ///
+  /// For example, "fooos1.2.3" would return (1, 2, 3).
+  ///
+  /// If an entry is not defined, it will be returned as 0.
+  void getEnvironmentVersion(unsigned &Major, unsigned &Minor,
+                             unsigned &Micro) const;
+
+  /// Get the object format for this triple.
+  ObjectFormatType getObjectFormat() const;
+
+  /// Parse the version number from the OS name component of the
+  /// triple, if present.
+  ///
+  /// For example, "fooos1.2.3" would return (1, 2, 3).
+  ///
+  /// If an entry is not defined, it will be returned as 0.
+  void getOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const {
+    return GnuTT.getOSVersion(Major, Minor, Micro);
+  }
+
+  /// Return just the major version number, this is
+  /// specialized because it is a common query.
+  unsigned getOSMajorVersion() const { return GnuTT.getOSMajorVersion(); }
+
+  /// Parse the version number as with getOSVersion and then
+  /// translate generic "darwin" versions to the corresponding OS X versions.
+  /// This may also be called with IOS triples but the OS X version number is
+  /// just set to a constant 10.4.0 in that case.  Returns true if successful.
+  bool getMacOSXVersion(unsigned &Major, unsigned &Minor,
+                        unsigned &Micro) const {
+    return GnuTT.getMacOSXVersion(Major, Minor, Micro);
+  }
+
+  /// Parse the version number as with getOSVersion.  This
+  /// should
+  /// only be called with IOS triples.
+  void getiOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const {
+    return GnuTT.getiOSVersion(Major, Minor, Micro);
+  }
+
+  /// @}
+  /// @name Direct Component Access
+  /// @{
+
+  const std::string &str() const { return GnuTT.str(); }
+
+  const std::string &getTriple() const { return GnuTT.str(); }
+
+  /// Get the architecture (first) component of the
+  /// triple.
+  StringRef getArchName() const { return GnuTT.getArchName(); }
+
+  /// Get the vendor (second) component of the triple.
+  StringRef getVendorName() const { return GnuTT.getVendorName(); }
+
+  /// Get the operating system (third) component of the
+  /// triple.
+  StringRef getOSName() const { return GnuTT.getOSName(); }
+
+  /// Get the optional environment (fourth)
+  /// component of the triple, or "" if empty.
+  StringRef getEnvironmentName() const { return GnuTT.getEnvironmentName(); }
+
+  /// Get the operating system and optional
+  /// environment components as a single string (separated by a '-'
+  /// if the environment component is present).
+  StringRef getOSAndEnvironmentName() const {
+    return GnuTT.getOSAndEnvironmentName();
+  }
+
+  /// @}
+  /// @name Convenience Predicates
+  /// @{
+
+  /// Test whether the architecture is 64-bit
+  ///
+  /// Note that this tests for 64-bit pointer width, and nothing else. Note
+  /// that we intentionally expose only three predicates, 64-bit, 32-bit, and
+  /// 16-bit. The inner details of pointer width for particular architectures
+  /// is not summed up in the triple, and so only a coarse grained predicate
+  /// system is provided.
+  bool isArch64Bit() const { return GnuTT.isArch64Bit(); }
+
+  /// Test whether the architecture is 32-bit
+  ///
+  /// Note that this tests for 32-bit pointer width, and nothing else.
+  bool isArch32Bit() const { return GnuTT.isArch32Bit(); }
+
+  /// Test whether the architecture is 16-bit
+  ///
+  /// Note that this tests for 16-bit pointer width, and nothing else.
+  bool isArch16Bit() const { return GnuTT.isArch16Bit(); }
+
+  /// Helper function for doing comparisons against version
+  /// numbers included in the target triple.
+  bool isOSVersionLT(unsigned Major, unsigned Minor = 0,
+                     unsigned Micro = 0) const {
+    return GnuTT.isOSVersionLT(Major, Minor, Micro);
+  }
+
+  bool isOSVersionLT(const Triple &Other) const {
+    return GnuTT.isOSVersionLT(Other);
+  }
+
+  /// Comparison function for checking OS X version
+  /// compatibility, which handles supporting skewed version numbering schemes
+  /// used by the "darwin" triples.
+  unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0,
+                             unsigned Micro = 0) const {
+    return GnuTT.isMacOSXVersionLT(Major, Minor, Micro);
+  }
+
+  /// Is this a Mac OS X triple. For legacy reasons, we support both
+  /// "darwin" and "osx" as OS X triples.
+  bool isMacOSX() const { return GnuTT.isMacOSX(); }
+
+  /// Is this an iOS triple.
+  bool isiOS() const { return GnuTT.isiOS(); }
+
+  /// Is this a "Darwin" OS (OS X or iOS).
+  bool isOSDarwin() const { return GnuTT.isOSDarwin(); }
+
+  bool isOSNetBSD() const { return GnuTT.isOSNetBSD(); }
+
+  bool isOSOpenBSD() const { return GnuTT.isOSOpenBSD(); }
+
+  bool isOSFreeBSD() const { return GnuTT.isOSFreeBSD(); }
+
+  bool isOSDragonFly() const { return GnuTT.isOSDragonFly(); }
+
+  bool isOSSolaris() const { return GnuTT.isOSSolaris(); }
+
+  bool isOSBitrig() const { return GnuTT.isOSBitrig(); }
+
+  bool isWindowsMSVCEnvironment() const {
+    return GnuTT.isWindowsMSVCEnvironment();
+  }
+
+  bool isKnownWindowsMSVCEnvironment() const {
+    return GnuTT.isKnownWindowsMSVCEnvironment();
+  }
+
+  bool isWindowsCoreCLREnvironment() const {
+    return GnuTT.isWindowsCoreCLREnvironment();
+  }
+
+  bool isWindowsItaniumEnvironment() const {
+    return GnuTT.isWindowsItaniumEnvironment();
+  }
+
+  bool isWindowsCygwinEnvironment() const {
+    return GnuTT.isWindowsCygwinEnvironment();
+  }
+
+  bool isWindowsGNUEnvironment() const {
+    return GnuTT.isWindowsGNUEnvironment();
+  }
+
+  /// Tests for either Cygwin or MinGW OS
+  bool isOSCygMing() const { return GnuTT.isOSCygMing(); }
+
+  /// Is this a "Windows" OS targeting a "MSVCRT.dll" environment.
+  bool isOSMSVCRT() const { return GnuTT.isOSMSVCRT(); }
+
+  /// Tests whether the OS is Windows.
+  bool isOSWindows() const { return GnuTT.isOSWindows(); }
+
+  /// Tests whether the OS is NaCl (Native Client)
+  bool isOSNaCl() const { return GnuTT.isOSNaCl(); }
+
+  /// Tests whether the OS is Linux.
+  bool isOSLinux() const { return GnuTT.isOSLinux(); }
+
+  /// Tests whether the OS uses the ELF binary format.
+  bool isOSBinFormatELF() const { return GnuTT.isOSBinFormatELF(); }
+
+  /// Tests whether the OS uses the COFF binary format.
+  bool isOSBinFormatCOFF() const { return GnuTT.isOSBinFormatCOFF(); }
+
+  /// Tests whether the environment is MachO.
+  bool isOSBinFormatMachO() const { return GnuTT.isOSBinFormatMachO(); }
+
+  /// Tests whether the target is the PS4 CPU
+  bool isPS4CPU() const { return GnuTT.isPS4CPU(); }
+
+  /// Tests whether the target is the PS4 platform
+  bool isPS4() const { return GnuTT.isPS4(); }
+
+  /// @}
+
+  // FIXME: Remove. This function exists to avoid having to migrate everything
+  //        at once.
+  const Triple &getTargetTriple() const { return GnuTT; }
+
+private:
+  Triple GnuTT;
+};
+
+} // End llvm namespace
+
+#endif

llvm/trunk/include/llvm/MC/MCELFObjectWriter.h

 //===-- llvm/MC/MCELFObjectWriter.h - ELF Object Writer ---------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCELFOBJECTWRITER_H
 #define LLVM_MC_MCELFOBJECTWRITER_H
 
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/Support/DataTypes.h"
 #include "llvm/Support/ELF.h"
 #include <vector>
 
 namespace llvm {
 class MCAssembler;
 class MCFixup;
 class MCFragment;

 
 protected:
 
   MCELFObjectTargetWriter(bool Is64Bit_, uint8_t OSABI_,
                           uint16_t EMachine_,  bool HasRelocationAddend,
                           bool IsN64=false);
 
 public:
-  static uint8_t getOSABI(Triple::OSType OSType) {
+  static uint8_t getOSABI(TargetTuple::OSType OSType) {
     switch (OSType) {
-      case Triple::CloudABI:
-        return ELF::ELFOSABI_CLOUDABI;
-      case Triple::PS4:
-      case Triple::FreeBSD:
-        return ELF::ELFOSABI_FREEBSD;
-      case Triple::Linux:
-        return ELF::ELFOSABI_LINUX;
-      default:
-        return ELF::ELFOSABI_NONE;
+    case TargetTuple::CloudABI:
+    case TargetTuple::PS4:
+    case TargetTuple::FreeBSD:
+    case TargetTuple::Linux:
     }
   }
 
   virtual ~MCELFObjectTargetWriter() {}
 
   virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
                                 bool IsPCRel) const = 0;
 

llvm/trunk/include/llvm/MC/MCSubtargetInfo.h

 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the subtarget options of a Target machine.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCSUBTARGETINFO_H
 #define LLVM_MC_MCSUBTARGETINFO_H
 
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include <string>
 
 namespace llvm {
 
 class StringRef;
 
 //===----------------------------------------------------------------------===//
 ///
 /// MCSubtargetInfo - Generic base class for all target subtargets.
 ///
 class MCSubtargetInfo {
-  Triple TargetTriple;                        // Target triple
-  std::string CPU; // CPU being targeted.
+  TargetTuple TheTargetTuple;                 // Target triple
+  std::string CPU;                            // CPU being targeted.
   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
-  ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
+  ArrayRef<SubtargetFeatureKV> ProcDesc;      // Processor descriptions
 
   // Scheduler machine model
   const SubtargetInfoKV *ProcSchedModels;
   const MCWriteProcResEntry *WriteProcResTable;
   const MCWriteLatencyEntry *WriteLatencyTable;
   const MCReadAdvanceEntry *ReadAdvanceTable;
   const MCSchedModel *CPUSchedModel;
 
   const InstrStage *Stages;            // Instruction itinerary stages
   const unsigned *OperandCycles;       // Itinerary operand cycles
   const unsigned *ForwardingPaths;     // Forwarding paths
   FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
 
   MCSubtargetInfo() = delete;
   MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
   MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
 
 public:
   MCSubtargetInfo(const MCSubtargetInfo &) = default;
-  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
+  MCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS,
                   ArrayRef<SubtargetFeatureKV> PF,
                   ArrayRef<SubtargetFeatureKV> PD,
                   const SubtargetInfoKV *ProcSched,
                   const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
                   const MCReadAdvanceEntry *RA, const InstrStage *IS,
                   const unsigned *OC, const unsigned *FP);
 
-  /// getTargetTriple - Return the target triple string.
-  const Triple &getTargetTriple() const { return TargetTriple; }
+  /// getTargetTuple - Return the target triple string.
+  const TargetTuple &getTargetTuple() const { return TheTargetTuple; }
 
   /// getCPU - Return the CPU string.
   StringRef getCPU() const {
     return CPU;
   }
 
   /// getFeatureBits - Return the feature bits.
   ///

llvm/trunk/include/llvm/Support/TargetRegistry.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_SUPPORT_TARGETREGISTRY_H
 #define LLVM_SUPPORT_TARGETREGISTRY_H
 
 #include "llvm-c/Disassembler.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/FormattedStream.h"
 #include <cassert>
 #include <memory>
 #include <string>
 
 namespace llvm {
 class AsmPrinter;

 MCStreamer *createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB,
                               raw_pwrite_stream &OS, MCCodeEmitter *CE,
                               bool RelaxAll);
 MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
                                 raw_pwrite_stream &OS, MCCodeEmitter *CE,
                                 bool RelaxAll, bool DWARFMustBeAtTheEnd,
                                 bool LabelSections = false);
 
-MCRelocationInfo *createMCRelocationInfo(const Triple &TT, MCContext &Ctx);
+MCRelocationInfo *createMCRelocationInfo(const TargetTuple &TT, MCContext &Ctx);
 
-MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
+MCSymbolizer *createMCSymbolizer(const TargetTuple &TT,
+                                 LLVMOpInfoCallback GetOpInfo,
                                  LLVMSymbolLookupCallback SymbolLookUp,
                                  void *DisInfo, MCContext *Ctx,
                                  std::unique_ptr<MCRelocationInfo> &&RelInfo);
 
 /// Target - Wrapper for Target specific information.
 ///
 /// For registration purposes, this is a POD type so that targets can be
 /// registered without the use of static constructors.
 ///
 /// Targets should implement a single global instance of this class (which
 /// will be zero initialized), and pass that instance to the TargetRegistry as
 /// part of their initialization.
 class Target {
 public:
   friend struct TargetRegistry;
 
   typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch);
 
   typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
-                                          const Triple &TT);
-  typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const Triple &TT,
+                                          const TargetTuple &TT);
+  typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const TargetTuple &TT,
                                                   Reloc::Model RM,
                                                   CodeModel::Model CM,
                                                   CodeGenOpt::Level OL);
   typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
   typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info);
-  typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const Triple &TT);
-  typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const Triple &TT,
+  typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const TargetTuple &TT);
+  // FIXME: CPU and Features should be merged into TargetTuple when possible.
+  typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const TargetTuple &TT,
                                                       StringRef CPU,
                                                       StringRef Features);
+  // FIXME: CPU and Features should be merged into TargetTuple when possible.
   typedef TargetMachine *(*TargetMachineCtorTy)(
-      const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
+      const Target &T, const TargetTuple &TT, StringRef CPU, StringRef Features,
       const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
       CodeGenOpt::Level OL);
   // If it weren't for layering issues (this header is in llvm/Support, but
   // depends on MC?) this should take the Streamer by value rather than rvalue
   // reference.
   typedef AsmPrinter *(*AsmPrinterCtorTy)(
       TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
+  // FIXME: CPU and Features should be merged into TargetTuple when possible.
   typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
                                               const MCRegisterInfo &MRI,
-                                              const Triple &TT, StringRef CPU);
+                                              const TargetTuple &TT,
+                                              StringRef CPU);
   typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
       MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
       const MCTargetOptions &Options);
   typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
                                                   const MCSubtargetInfo &STI,
                                                   MCContext &Ctx);
-  typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Triple &T,
+  typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const TargetTuple &T,
                                                 unsigned SyntaxVariant,
                                                 const MCAsmInfo &MAI,
                                                 const MCInstrInfo &MII,
                                                 const MCRegisterInfo &MRI);
   typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
                                                 const MCRegisterInfo &MRI,
                                                 MCContext &Ctx);
-  typedef MCStreamer *(*ELFStreamerCtorTy)(const Triple &T, MCContext &Ctx,
+  typedef MCStreamer *(*ELFStreamerCtorTy)(const TargetTuple &T, MCContext &Ctx,
                                            MCAsmBackend &TAB,
                                            raw_pwrite_stream &OS,
                                            MCCodeEmitter *Emitter,
                                            bool RelaxAll);
   typedef MCStreamer *(*MachOStreamerCtorTy)(MCContext &Ctx, MCAsmBackend &TAB,
                                              raw_pwrite_stream &OS,
                                              MCCodeEmitter *Emitter,
                                              bool RelaxAll,
                                              bool DWARFMustBeAtTheEnd);
   typedef MCStreamer *(*COFFStreamerCtorTy)(MCContext &Ctx, MCAsmBackend &TAB,
                                             raw_pwrite_stream &OS,
                                             MCCodeEmitter *Emitter,
                                             bool RelaxAll);
   typedef MCTargetStreamer *(*NullTargetStreamerCtorTy)(MCStreamer &S);
   typedef MCTargetStreamer *(*AsmTargetStreamerCtorTy)(
       MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint,
       bool IsVerboseAsm);
   typedef MCTargetStreamer *(*ObjectTargetStreamerCtorTy)(
       MCStreamer &S, const MCSubtargetInfo &STI);
-  typedef MCRelocationInfo *(*MCRelocationInfoCtorTy)(const Triple &TT,
+  typedef MCRelocationInfo *(*MCRelocationInfoCtorTy)(const TargetTuple &TT,
                                                       MCContext &Ctx);
   typedef MCSymbolizer *(*MCSymbolizerCtorTy)(
-      const Triple &TT, LLVMOpInfoCallback GetOpInfo,
+      const TargetTuple &TT, LLVMOpInfoCallback GetOpInfo,
       LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
       std::unique_ptr<MCRelocationInfo> &&RelInfo);
 
 private:
   /// Next - The next registered target in the linked list, maintained by the
   /// TargetRegistry.
   Target *Next;
 
public:
 
   /// @}
   /// @name Feature Constructors
   /// @{
 
   /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
   /// target triple.
   ///
-  /// \param TheTriple This argument is used to determine the target machine
+  /// \param TT This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
   /// either the target triple from the module, or the target triple of the
   /// host if that does not exist.
-  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
-                             StringRef TheTriple) const {
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) const {
     if (!MCAsmInfoCtorFn)
       return nullptr;
-    return MCAsmInfoCtorFn(MRI, Triple(TheTriple));
+    return MCAsmInfoCtorFn(MRI, TargetTuple(Triple(TT)));
   }
 
   /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
   ///
   MCCodeGenInfo *createMCCodeGenInfo(StringRef TT, Reloc::Model RM,
                                      CodeModel::Model CM,
                                      CodeGenOpt::Level OL) const {
     if (!MCCodeGenInfoCtorFn)
       return nullptr;
-    return MCCodeGenInfoCtorFn(Triple(TT), RM, CM, OL);
+    return MCCodeGenInfoCtorFn(TargetTuple(Triple(TT)), RM, CM, OL);
   }
 
   /// createMCInstrInfo - Create a MCInstrInfo implementation.
   ///
   MCInstrInfo *createMCInstrInfo() const {
     if (!MCInstrInfoCtorFn)
       return nullptr;
     return MCInstrInfoCtorFn();
   }
 
   /// createMCInstrAnalysis - Create a MCInstrAnalysis implementation.
   ///
   MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const {
     if (!MCInstrAnalysisCtorFn)
       return nullptr;
     return MCInstrAnalysisCtorFn(Info);
   }
 
   /// createMCRegInfo - Create a MCRegisterInfo implementation.
   ///
   MCRegisterInfo *createMCRegInfo(StringRef TT) const {
     if (!MCRegInfoCtorFn)
       return nullptr;
-    return MCRegInfoCtorFn(Triple(TT));
+    return MCRegInfoCtorFn(TargetTuple(Triple(TT)));
   }
 
   /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
   ///
-  /// \param TheTriple This argument is used to determine the target machine
+  /// \param TT This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
   /// either the target triple from the module, or the target triple of the
   /// host if that does not exist.
   /// \param CPU This specifies the name of the target CPU.
   /// \param Features This specifies the string representation of the
   /// additional target features.
-  MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU,
+  MCSubtargetInfo *createMCSubtargetInfo(StringRef TT, StringRef CPU,
                                          StringRef Features) const {
     if (!MCSubtargetInfoCtorFn)
       return nullptr;
-    return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features);
+    return MCSubtargetInfoCtorFn(TargetTuple(Triple(TT)), CPU, Features);
   }
 
   /// createTargetMachine - Create a target specific machine implementation
-  /// for the specified \p Triple.
+  /// for the specified \p TT.
   ///
   /// \param TT This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
   /// either the target triple from the module, or the target triple of the
   /// host if that does not exist.
   TargetMachine *
   createTargetMachine(StringRef TT, StringRef CPU, StringRef Features,
                       const TargetOptions &Options,
                       Reloc::Model RM = Reloc::Default,
                       CodeModel::Model CM = CodeModel::Default,
                       CodeGenOpt::Level OL = CodeGenOpt::Default) const {
     if (!TargetMachineCtorFn)
       return nullptr;
-    return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
-                               CM, OL);
+    return TargetMachineCtorFn(*this, TargetTuple(Triple(TT)), CPU, Features,
+                               Options, RM, CM, OL);
   }
 
   /// createMCAsmBackend - Create a target specific assembly parser.
   ///
-  /// \param TheTriple The target triple string.
-  MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
-                                   StringRef TheTriple, StringRef CPU) const {
+  /// \param TT The target triple string.
+  MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, StringRef TT,
+                                   StringRef CPU) const {
     if (!MCAsmBackendCtorFn)
       return nullptr;
-    return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU);
+    return MCAsmBackendCtorFn(*this, MRI, TargetTuple(Triple(TT)), CPU);
   }
 
   /// createMCAsmParser - Create a target specific assembly parser.
   ///
   /// \param Parser The target independent parser implementation to use for
   /// parsing and lexing.
   MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI,
                                        MCAsmParser &Parser,
public:
 
   MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI,
                                        MCContext &Ctx) const {
     if (!MCDisassemblerCtorFn)
       return nullptr;
     return MCDisassemblerCtorFn(*this, STI, Ctx);
   }
 
-  MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
+  MCInstPrinter *createMCInstPrinter(const TargetTuple &TT,
+                                     unsigned SyntaxVariant,
                                      const MCAsmInfo &MAI,
                                      const MCInstrInfo &MII,
                                      const MCRegisterInfo &MRI) const {
     if (!MCInstPrinterCtorFn)
       return nullptr;
-    return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MRI);
+    return MCInstPrinterCtorFn(TT, SyntaxVariant, MAI, MII, MRI);
   }
 
   /// createMCCodeEmitter - Create a target specific code emitter.
   MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
                                      const MCRegisterInfo &MRI,
                                      MCContext &Ctx) const {
     if (!MCCodeEmitterCtorFn)
       return nullptr;
     return MCCodeEmitterCtorFn(II, MRI, Ctx);
   }
 
   /// Create a target specific MCStreamer.
   ///
-  /// \param T The target triple.
+  /// \param TT The target triple.
   /// \param Ctx The target context.
   /// \param TAB The target assembler backend object. Takes ownership.
   /// \param OS The stream object.
   /// \param Emitter The target independent assembler object.Takes ownership.
   /// \param RelaxAll Relax all fixups?
-  MCStreamer *createMCObjectStreamer(const Triple &T, MCContext &Ctx,
+  MCStreamer *createMCObjectStreamer(const TargetTuple &TT, MCContext &Ctx,
                                      MCAsmBackend &TAB, raw_pwrite_stream &OS,
                                      MCCodeEmitter *Emitter,
                                      const MCSubtargetInfo &STI, bool RelaxAll,
                                      bool DWARFMustBeAtTheEnd) const {
     MCStreamer *S;
-    switch (T.getObjectFormat()) {
+    switch (TT.getObjectFormat()) {
     default:
       llvm_unreachable("Unknown object format");
-    case Triple::COFF:
-      assert(T.isOSWindows() && "only Windows COFF is supported");
+    case TargetTuple::COFF:
+      assert(TT.isOSWindows() && "only Windows COFF is supported");
       S = COFFStreamerCtorFn(Ctx, TAB, OS, Emitter, RelaxAll);
       break;
-    case Triple::MachO:
+    case TargetTuple::MachO:
       if (MachOStreamerCtorFn)
         S = MachOStreamerCtorFn(Ctx, TAB, OS, Emitter, RelaxAll,
                                 DWARFMustBeAtTheEnd);
       else
         S = createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
                                 DWARFMustBeAtTheEnd);
       break;
-    case Triple::ELF:
+    case TargetTuple::ELF:
       if (ELFStreamerCtorFn)
-        S = ELFStreamerCtorFn(T, Ctx, TAB, OS, Emitter, RelaxAll);
+        S = ELFStreamerCtorFn(TT, Ctx, TAB, OS, Emitter, RelaxAll);
       else
         S = createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
       break;
     }
     if (ObjectTargetStreamerCtorFn)
       ObjectTargetStreamerCtorFn(*S, STI);
     return S;
   }
public:
   /// createMCRelocationInfo - Create a target specific MCRelocationInfo.
   ///
   /// \param TT The target triple.
   /// \param Ctx The target context.
   MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx) const {
     MCRelocationInfoCtorTy Fn = MCRelocationInfoCtorFn
                                     ? MCRelocationInfoCtorFn
                                     : llvm::createMCRelocationInfo;
-    return Fn(Triple(TT), Ctx);
+    return Fn(TargetTuple(Triple(TT)), Ctx);
   }
 
   /// createMCSymbolizer - Create a target specific MCSymbolizer.
   ///
   /// \param TT The target triple.
   /// \param GetOpInfo The function to get the symbolic information for
   /// operands.
   /// \param SymbolLookUp The function to lookup a symbol name.
   /// \param DisInfo The pointer to the block of symbolic information for above
   /// call
   /// back.
   /// \param Ctx The target context.
   /// \param RelInfo The relocation information for this target. Takes
   /// ownership.
   MCSymbolizer *
   createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
                      LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo,
                      MCContext *Ctx,
                      std::unique_ptr<MCRelocationInfo> &&RelInfo) const {
     MCSymbolizerCtorTy Fn =
         MCSymbolizerCtorFn ? MCSymbolizerCtorFn : llvm::createMCSymbolizer;
-    return Fn(Triple(TT), GetOpInfo, SymbolLookUp, DisInfo, Ctx,
+    return Fn(TargetTuple(Triple(TT)), GetOpInfo, SymbolLookUp, DisInfo, Ctx,
               std::move(RelInfo));
   }
 
   /// @}
 };
 
 /// TargetRegistry - Generic interface to target specific features.
 struct TargetRegistry {
struct TargetRegistry {
 
   /// @name Registry Access
   /// @{
 
   static iterator_range<iterator> targets();
 
   /// lookupTarget - Lookup a target based on a target triple.
   ///
-  /// \param Triple - The triple to use for finding a target.
+  /// \param TT - The triple to use for finding a target.
   /// \param Error - On failure, an error string describing why no target was
   /// found.
-  static const Target *lookupTarget(const std::string &Triple,
-                                    std::string &Error);
+  static const Target *lookupTarget(const std::string &TT, std::string &Error);
 
   /// lookupTarget - Lookup a target based on an architecture name
   /// and a target triple.  If the architecture name is non-empty,
   /// then the lookup is done by architecture.  Otherwise, the target
   /// triple is used.
   ///
   /// \param ArchName - The architecture to use for finding a target.
-  /// \param TheTriple - The triple to use for finding a target.  The
+  /// \param TT - The triple to use for finding a target.  The
   /// triple is updated with canonical architecture name if a lookup
   /// by architecture is done.
   /// \param Error - On failure, an error string describing why no target was
   /// found.
-  static const Target *lookupTarget(const std::string &ArchName,
-                                    Triple &TheTriple, std::string &Error);
+  static const Target *lookupTarget(const std::string &ArchName, Triple &TT,
+                                    std::string &Error);
 
   /// @}
   /// @name Target Registration
   /// @{
 
   /// RegisterTarget - Register the given target. Attempts to register a
   /// target which has already been registered will be ignored.
   ///

 /// }
 template <class MCAsmInfoImpl> struct RegisterMCAsmInfo {
   RegisterMCAsmInfo(Target &T) {
     TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
   }
 
 private:
   static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/,
-                              const Triple &TT) {
-    return new MCAsmInfoImpl(TT);
+                              const TargetTuple &TT) {
+    return new MCAsmInfoImpl(TargetTuple(TT));
   }
 };
 
 /// RegisterMCAsmInfoFn - Helper template for registering a target assembly info
 /// implementation.  This invokes the specified function to do the
 /// construction.  Usage:
 ///
 /// extern "C" void LLVMInitializeFooTarget() {

 ///   RegisterMCCodeGenInfo<FooMCCodeGenInfo> X(TheFooTarget);
 /// }
 template <class MCCodeGenInfoImpl> struct RegisterMCCodeGenInfo {
   RegisterMCCodeGenInfo(Target &T) {
     TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
   }
 
 private:
-  static MCCodeGenInfo *Allocator(const Triple & /*TT*/, Reloc::Model /*RM*/,
-                                  CodeModel::Model /*CM*/,
+  static MCCodeGenInfo *Allocator(const TargetTuple & /*TT*/,
+                                  Reloc::Model /*RM*/, CodeModel::Model /*CM*/,
                                   CodeGenOpt::Level /*OL*/) {
     return new MCCodeGenInfoImpl();
   }
 };
 
 /// RegisterMCCodeGenInfoFn - Helper template for registering a target codegen
 /// info implementation.  This invokes the specified function to do the
 /// construction.  Usage:

 ///   RegisterMCRegInfo<FooMCRegInfo> X(TheFooTarget);
 /// }
 template <class MCRegisterInfoImpl> struct RegisterMCRegInfo {
   RegisterMCRegInfo(Target &T) {
     TargetRegistry::RegisterMCRegInfo(T, &Allocator);
   }
 
 private:
-  static MCRegisterInfo *Allocator(const Triple & /*TT*/) {
+  static MCRegisterInfo *Allocator(const TargetTuple & /*TT*/) {
     return new MCRegisterInfoImpl();
   }
 };
 
 /// RegisterMCRegInfoFn - Helper template for registering a target register
 /// info implementation.  This invokes the specified function to do the
 /// construction.  Usage:
 ///

 ///   RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
 /// }
 template <class MCSubtargetInfoImpl> struct RegisterMCSubtargetInfo {
   RegisterMCSubtargetInfo(Target &T) {
     TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
   }
 
 private:
-  static MCSubtargetInfo *Allocator(const Triple & /*TT*/, StringRef /*CPU*/,
-                                    StringRef /*FS*/) {
+  static MCSubtargetInfo *Allocator(const TargetTuple & /*TT*/,
+                                    StringRef /*CPU*/, StringRef /*FS*/) {
     return new MCSubtargetInfoImpl();
   }
 };
 
 /// RegisterMCSubtargetInfoFn - Helper template for registering a target
 /// subtarget info implementation.  This invokes the specified function to
 /// do the construction.  Usage:
 ///

 ///   RegisterTargetMachine<FooTargetMachine> X(TheFooTarget);
 /// }
 template <class TargetMachineImpl> struct RegisterTargetMachine {
   RegisterTargetMachine(Target &T) {
     TargetRegistry::RegisterTargetMachine(T, &Allocator);
   }
 
 private:
-  static TargetMachine *Allocator(const Target &T, const Triple &TT,
+  static TargetMachine *Allocator(const Target &T, const TargetTuple &TT,
                                   StringRef CPU, StringRef FS,
                                   const TargetOptions &Options, Reloc::Model RM,
                                   CodeModel::Model CM, CodeGenOpt::Level OL) {
-    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
+    return new TargetMachineImpl(T, TT.getTargetTriple(), CPU, FS, Options, RM,
+                                 CM, OL);
   }
 };
 
 /// RegisterMCAsmBackend - Helper template for registering a target specific
 /// assembler backend. Usage:
 ///
 /// extern "C" void LLVMInitializeFooMCAsmBackend() {
 ///   extern Target TheFooTarget;
 ///   RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
 /// }
 template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
   RegisterMCAsmBackend(Target &T) {
     TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
   }
 
 private:
   static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,
-                                 const Triple &TheTriple, StringRef CPU) {
-    return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
+                                 const TargetTuple &TT, StringRef CPU) {
+    return new MCAsmBackendImpl(T, MRI, TT, CPU);
   }
 };
 
 /// RegisterMCAsmParser - Helper template for registering a target specific
 /// assembly parser, for use in the target machine initialization
 /// function. Usage:
 ///
 /// extern "C" void LLVMInitializeFooMCAsmParser() {

llvm/trunk/include/llvm/Target/TargetMachine.h

 // This file defines the TargetMachine and LLVMTargetMachine classes.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TARGET_TARGETMACHINE_H
 #define LLVM_TARGET_TARGETMACHINE_H
 
 #include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Target/TargetOptions.h"
 #include <cassert>
 #include <string>
 

 public:
   mutable TargetOptions Options;
 
   virtual ~TargetMachine();
 
   const Target &getTarget() const { return TheTarget; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
+  // FIXME: Return a reference once we store a TargetTuple
+  const TargetTuple getTargetTuple() const { return TargetTuple(TargetTriple); }
   StringRef getTargetCPU() const { return TargetCPU; }
   StringRef getTargetFeatureString() const { return TargetFS; }
 
   /// Virtual method implemented by subclasses that returns a reference to that
   /// target's TargetSubtargetInfo-derived member variable.
   virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const {
     return nullptr;
   }

llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h

 /// be exposed through a TargetSubtargetInfo-derived class.
 ///
 class TargetSubtargetInfo : public MCSubtargetInfo {
   TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
   void operator=(const TargetSubtargetInfo &) = delete;
   TargetSubtargetInfo() = delete;
 
 protected: // Can only create subclasses...
-  TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
+  TargetSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS,
                       ArrayRef<SubtargetFeatureKV> PF,
                       ArrayRef<SubtargetFeatureKV> PD,
                       const SubtargetInfoKV *ProcSched,
                       const MCWriteProcResEntry *WPR,
                       const MCWriteLatencyEntry *WL,
                       const MCReadAdvanceEntry *RA, const InstrStage *IS,
                       const unsigned *OC, const unsigned *FP);
 

llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp

bool LLVMTargetMachine::addPassesToEmitFile(
   const MCRegisterInfo &MRI = *getMCRegisterInfo();
   const MCInstrInfo &MII = *getMCInstrInfo();
 
   std::unique_ptr<MCStreamer> AsmStreamer;
 
   switch (FileType) {
   case CGFT_AssemblyFile: {
     MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter(
-        getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
+        getTargetTuple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
 
     // Create a code emitter if asked to show the encoding.
     MCCodeEmitter *MCE = nullptr;
     if (Options.MCOptions.ShowMCEncoding)
       MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
 
     MCAsmBackend *MAB =
         getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
case CGFT_ObjectFile: {
     MCAsmBackend *MAB =
         getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
     if (!MCE || !MAB)
       return true;
 
     // Don't waste memory on names of temp labels.
     Context->setUseNamesOnTempLabels(false);
 
-    Triple T(getTargetTriple().str());
+    TargetTuple T(Triple(getTargetTriple().str()));
     AsmStreamer.reset(getTarget().createMCObjectStreamer(
         T, *Context, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
         /*DWARFMustBeAtTheEnd*/ true));
     break;
   }
   case CGFT_Null:
     // The Null output is intended for use for performance analysis and testing,
     // not real users.
bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
   const MCRegisterInfo &MRI = *getMCRegisterInfo();
   MCCodeEmitter *MCE =
       getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
   MCAsmBackend *MAB =
       getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU);
   if (!MCE || !MAB)
     return true;
 
-  const Triple &T = getTargetTriple();
+  const TargetTuple &TT = getTargetTuple();
   const MCSubtargetInfo &STI = *getMCSubtargetInfo();
   std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer(
-      T, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
+      TT, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
       /*DWARFMustBeAtTheEnd*/ true));
 
   // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
   FunctionPass *Printer =
       getTarget().createAsmPrinter(*this, std::move(AsmStreamer));
   if (!Printer)
     return true;
 
   PM.add(Printer);
 
   return false; // success!
 }

llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp

LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU,
 
   std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
       TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx, std::move(RelInfo)));
   DisAsm->setSymbolizer(std::move(Symbolizer));
 
   // Set up the instruction printer.
   int AsmPrinterVariant = MAI->getAssemblerDialect();
   MCInstPrinter *IP = TheTarget->createMCInstPrinter(
-      Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI);
+      TargetTuple(Triple(TT)), AsmPrinterVariant, *MAI, *MII, *MRI);
   if (!IP)
     return nullptr;
 
   LLVMDisasmContext *DC =
       new LLVMDisasmContext(TT, DisInfo, TagType, GetOpInfo, SymbolLookUp,
                             TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
   if (!DC)
     return nullptr;
if (Options & LLVMDisassembler_Option_AsmPrinterVariant){
       LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
       // Try to set up the new instruction printer.
       const MCAsmInfo *MAI = DC->getAsmInfo();
       const MCInstrInfo *MII = DC->getInstrInfo();
       const MCRegisterInfo *MRI = DC->getRegisterInfo();
       int AsmPrinterVariant = MAI->getAssemblerDialect();
       AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
       MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
-          Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
+          TargetTuple(Triple(DC->getTripleName())), AsmPrinterVariant, *MAI,
+          *MII, *MRI);
       if (IP) {
         DC->setIP(IP);
         DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
         Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
       }
   }
   if (Options & LLVMDisassembler_Option_SetInstrComments) {
     LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;

llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp

 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cstring>
 
 using namespace llvm;
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 }
 
 // This function tries to add a symbolic operand in place of the immediate
 // Value in the MCInst. The immediate Value has had any PC adjustment made by
 // the caller. If the instruction is a branch instruction then IsBranch is true,
 // else false. If the getOpInfo() function was set as part of the
 // setupForSymbolicDisassembly() call then that function is called to get any
 // symbolic information at the Address for this instruction. If that returns
else if(ReferenceType ==
       cStream << "Objc selector ref: " << ReferenceName;
     else if(ReferenceType ==
             LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref)
       cStream << "Objc class ref: " << ReferenceName;
   }
 }
 
 namespace llvm {
-MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
+MCSymbolizer *createMCSymbolizer(const TargetTuple &TT,
+                                 LLVMOpInfoCallback GetOpInfo,
                                  LLVMSymbolLookupCallback SymbolLookUp,
                                  void *DisInfo, MCContext *Ctx,
                                  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
   assert(Ctx && "No MCContext given for symbolic disassembly");
 
   return new MCExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
                                   SymbolLookUp, DisInfo);
 }
 }

llvm/trunk/lib/MC/MCDisassembler/MCRelocationInfo.cpp

 const MCExpr *
 MCRelocationInfo::createExprForCAPIVariantKind(const MCExpr *SubExpr,
                                                unsigned VariantKind) {
   if (VariantKind != LLVMDisassembler_VariantKind_None)
     return nullptr;
   return SubExpr;
 }
 
-MCRelocationInfo *llvm::createMCRelocationInfo(const Triple &TT,
+MCRelocationInfo *llvm::createMCRelocationInfo(const TargetTuple &TT,
                                                MCContext &Ctx) {
   return new MCRelocationInfo(Ctx);
 }

llvm/trunk/lib/MC/MCSubtargetInfo.cpp

 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 
 using namespace llvm;
 
 static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
else
     CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
 }
 
 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU) {
   FeatureBits = getFeatures(CPU, "", ProcDesc, ProcFeatures);
 }
 
 MCSubtargetInfo::MCSubtargetInfo(
-    const Triple &TT, StringRef C, StringRef FS,
+    const TargetTuple &TT, StringRef C, StringRef FS,
     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
     const InstrStage *IS, const unsigned *OC, const unsigned *FP)
-    : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
+    : TheTargetTuple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
       ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
       ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
   InitMCProcessorInfo(CPU, FS);
 }
 
 /// ToggleFeature - Toggle a feature and returns the re-computed feature
 /// bits. This version does not change the implied bits.
 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {

llvm/trunk/lib/Support/CMakeLists.txt

add_llvm_library(LLVMSupport
   StreamingMemoryObject.cpp
   StringExtras.cpp
   StringMap.cpp
   StringPool.cpp
   StringSaver.cpp
   StringRef.cpp
   SystemUtils.cpp
   TargetParser.cpp
+  TargetTuple.cpp
   Timer.cpp
   ToolOutputFile.cpp
   Triple.cpp
   Twine.cpp
   Unicode.cpp
   YAMLParser.cpp
   YAMLTraits.cpp
   raw_os_ostream.cpp

llvm/trunk/lib/Support/TargetTuple.cpp

+//===--- TargetTuple.cpp - Target tuple class -----------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/TargetTuple.h"
+#include "llvm/Support/TargetParser.h"
+
+using namespace llvm;
+
+// FIXME: These should be removed as soon as the Triple member is replaced.
+static TargetTuple::ArchType
+convertTripleArchToTupleArch(Triple::ArchType Arch) {
+  switch (Arch) {
+  case Triple::UnknownArch:
+    return TargetTuple::UnknownArch;
+  case Triple::arm:
+    return TargetTuple::arm;
+  case Triple::armeb:
+    return TargetTuple::armeb;
+  case Triple::aarch64:
+    return TargetTuple::aarch64;
+  case Triple::aarch64_be:
+    return TargetTuple::aarch64_be;
+  case Triple::bpfel:
+    return TargetTuple::bpfel;
+  case Triple::bpfeb:
+    return TargetTuple::bpfeb;
+  case Triple::hexagon:
+    return TargetTuple::hexagon;
+  case Triple::mips:
+    return TargetTuple::mips;
+  case Triple::mipsel:
+    return TargetTuple::mipsel;
+  case Triple::mips64:
+    return TargetTuple::mips64;
+  case Triple::mips64el:
+    return TargetTuple::mips64el;
+  case Triple::msp430:
+    return TargetTuple::msp430;
+  case Triple::ppc:
+    return TargetTuple::ppc;
+  case Triple::ppc64:
+    return TargetTuple::ppc64;
+  case Triple::ppc64le:
+    return TargetTuple::ppc64le;
+  case Triple::r600:
+    return TargetTuple::r600;
+  case Triple::amdgcn:
+    return TargetTuple::amdgcn;
+  case Triple::sparc:
+    return TargetTuple::sparc;
+  case Triple::sparcv9:
+    return TargetTuple::sparcv9;
+  case Triple::sparcel:
+    return TargetTuple::sparcel;
+  case Triple::systemz:
+    return TargetTuple::systemz;
+  case Triple::tce:
+    return TargetTuple::tce;
+  case Triple::thumb:
+    return TargetTuple::thumb;
+  case Triple::thumbeb:
+    return TargetTuple::thumbeb;
+  case Triple::x86:
+    return TargetTuple::x86;
+  case Triple::x86_64:
+    return TargetTuple::x86_64;
+  case Triple::xcore:
+    return TargetTuple::xcore;
+  case Triple::nvptx:
+    return TargetTuple::nvptx;
+  case Triple::nvptx64:
+    return TargetTuple::nvptx64;
+  case Triple::le32:
+    return TargetTuple::le32;
+  case Triple::le64:
+    return TargetTuple::le64;
+  case Triple::amdil:
+    return TargetTuple::amdil;
+  case Triple::amdil64:
+    return TargetTuple::amdil64;
+  case Triple::hsail:
+    return TargetTuple::hsail;
+  case Triple::hsail64:
+    return TargetTuple::hsail64;
+  case Triple::spir:
+    return TargetTuple::spir;
+  case Triple::spir64:
+    return TargetTuple::spir64;
+  case Triple::kalimba:
+    return TargetTuple::kalimba;
+  case Triple::shave:
+    return TargetTuple::shave;
+  case Triple::wasm32:
+    return TargetTuple::wasm32;
+  case Triple::wasm64:
+    return TargetTuple::wasm64;
+  }
+  llvm_unreachable("Unmapped architecture.");
+}
+
+// FIXME: These should be removed as soon as the Triple member is replaced.
+static TargetTuple::SubArchType
+convertTripleSubArchToTupleSubArch(Triple::SubArchType SubArch) {
+  switch (SubArch) {
+  case Triple::NoSubArch:
+    return TargetTuple::NoSubArch;
+  case Triple::ARMSubArch_v8_1a:
+    return TargetTuple::ARMSubArch_v8_1a;
+  case Triple::ARMSubArch_v8:
+    return TargetTuple::ARMSubArch_v8;
+  case Triple::ARMSubArch_v7:
+    return TargetTuple::ARMSubArch_v7;
+  case Triple::ARMSubArch_v7em:
+    return TargetTuple::ARMSubArch_v7em;
+  case Triple::ARMSubArch_v7m:
+    return TargetTuple::ARMSubArch_v7m;
+  case Triple::ARMSubArch_v7s:
+    return TargetTuple::ARMSubArch_v7s;
+  case Triple::ARMSubArch_v6:
+    return TargetTuple::ARMSubArch_v6;
+  case Triple::ARMSubArch_v6m:
+    return TargetTuple::ARMSubArch_v6m;
+  case Triple::ARMSubArch_v6k:
+    return TargetTuple::ARMSubArch_v6k;
+  case Triple::ARMSubArch_v6t2:
+    return TargetTuple::ARMSubArch_v6t2;
+  case Triple::ARMSubArch_v5:
+    return TargetTuple::ARMSubArch_v5;
+  case Triple::ARMSubArch_v5te:
+    return TargetTuple::ARMSubArch_v5te;
+  case Triple::ARMSubArch_v4t:
+    return TargetTuple::ARMSubArch_v4t;
+  case Triple::KalimbaSubArch_v3:
+    return TargetTuple::KalimbaSubArch_v3;
+  case Triple::KalimbaSubArch_v4:
+    return TargetTuple::KalimbaSubArch_v4;
+  case Triple::KalimbaSubArch_v5:
+    return TargetTuple::KalimbaSubArch_v5;
+  }
+  llvm_unreachable("Unmapped subarchitecture.");
+}
+
+// FIXME: These should be removed as soon as the Triple member is replaced.
+static TargetTuple::VendorType
+convertTripleVendorToTupleVendor(Triple::VendorType Vendor) {
+  switch (Vendor) {
+  case Triple::UnknownVendor:
+    return TargetTuple::UnknownVendor;
+  case Triple::Apple:
+    return TargetTuple::Apple;
+  case Triple::PC:
+    return TargetTuple::PC;
+  case Triple::SCEI:
+    return TargetTuple::SCEI;
+  case Triple::BGP:
+    return TargetTuple::BGP;
+  case Triple::BGQ:
+    return TargetTuple::BGQ;
+  case Triple::Freescale:
+    return TargetTuple::Freescale;
+  case Triple::IBM:
+    return TargetTuple::IBM;
+  case Triple::ImaginationTechnologies:
+    return TargetTuple::ImaginationTechnologies;
+  case Triple::MipsTechnologies:
+    return TargetTuple::MipsTechnologies;
+  case Triple::NVIDIA:
+    return TargetTuple::NVIDIA;
+  case Triple::CSR:
+    return TargetTuple::CSR;
+  case Triple::Myriad:
+    return TargetTuple::Myriad;
+  }
+  llvm_unreachable("Unmapped vendor.");
+}
+
+// FIXME: These should be removed as soon as the Triple member is replaced.
+static TargetTuple::OSType convertTripleOSToTupleOS(Triple::OSType OS) {
+  switch (OS) {
+  case Triple::UnknownOS:
+    return TargetTuple::UnknownOS;
+  case Triple::CloudABI:
+    return TargetTuple::CloudABI;
+  case Triple::Darwin:
+    return TargetTuple::Darwin;
+  case Triple::DragonFly:
+    return TargetTuple::DragonFly;
+  case Triple::FreeBSD:
+    return TargetTuple::FreeBSD;
+  case Triple::IOS:
+    return TargetTuple::IOS;
+  case Triple::KFreeBSD:
+    return TargetTuple::KFreeBSD;
+  case Triple::Linux:
+    return TargetTuple::Linux;
+  case Triple::Lv2:
+    return TargetTuple::Lv2;
+  case Triple::MacOSX:
+    return TargetTuple::MacOSX;
+  case Triple::NetBSD:
+    return TargetTuple::NetBSD;
+  case Triple::OpenBSD:
+    return TargetTuple::OpenBSD;
+  case Triple::Solaris:
+    return TargetTuple::Solaris;
+  case Triple::Win32:
+    return TargetTuple::Win32;
+  case Triple::Haiku:
+    return TargetTuple::Haiku;
+  case Triple::Minix:
+    return TargetTuple::Minix;
+  case Triple::RTEMS:
+    return TargetTuple::RTEMS;
+  case Triple::NaCl:
+    return TargetTuple::NaCl;
+  case Triple::CNK:
+    return TargetTuple::CNK;
+  case Triple::Bitrig:
+    return TargetTuple::Bitrig;
+  case Triple::AIX:
+    return TargetTuple::AIX;
+  case Triple::CUDA:
+    return TargetTuple::CUDA;
+  case Triple::NVCL:
+    return TargetTuple::NVCL;
+  case Triple::AMDHSA:
+    return TargetTuple::AMDHSA;
+  case Triple::PS4:
+    return TargetTuple::PS4;
+  }
+  llvm_unreachable("Unmapped OS.");
+}
+
+// FIXME: These should be removed as soon as the Triple member is replaced.
+static TargetTuple::EnvironmentType
+convertTripleEnvToTupleEnv(Triple::EnvironmentType Env) {
+  switch (Env) {
+  case Triple::UnknownEnvironment:
+    return TargetTuple::UnknownEnvironment;
+  case Triple::GNU:
+    return TargetTuple::GNU;
+  case Triple::GNUEABI:
+    return TargetTuple::GNUEABI;
+  case Triple::GNUEABIHF:
+    return TargetTuple::GNUEABIHF;
+  case Triple::GNUX32:
+    return TargetTuple::GNUX32;
+  case Triple::CODE16:
+    return TargetTuple::CODE16;
+  case Triple::EABI:
+    return TargetTuple::EABI;
+  case Triple::EABIHF:
+    return TargetTuple::EABIHF;
+  case Triple::Android:
+    return TargetTuple::Android;
+  case Triple::MSVC:
+    return TargetTuple::MSVC;
+  case Triple::Itanium:
+    return TargetTuple::Itanium;
+  case Triple::Cygnus:
+    return TargetTuple::Cygnus;
+  case Triple::AMDOpenCL:
+    return TargetTuple::AMDOpenCL;
+  case Triple::CoreCLR:
+    return TargetTuple::CoreCLR;
+  }
+  llvm_unreachable("Unmapped Environment.");
+}
+
+// FIXME: These should be removed as soon as the Triple member is replaced.
+static TargetTuple::ObjectFormatType
+convertTripleObjFmtToTupleObjFmt(Triple::ObjectFormatType ObjFmt) {
+  switch (ObjFmt) {
+  case Triple::UnknownObjectFormat:
+    return TargetTuple::UnknownObjectFormat;
+  case Triple::COFF:
+    return TargetTuple::COFF;
+  case Triple::ELF:
+    return TargetTuple::ELF;
+  case Triple::MachO:
+    return TargetTuple::MachO;
+  }
+  llvm_unreachable("Unmapped Object Format.");
+}
+
+TargetTuple::ArchType TargetTuple::getArch() const {
+  return convertTripleArchToTupleArch(GnuTT.getArch());
+}
+
+TargetTuple::SubArchType TargetTuple::getSubArch() const {
+  return convertTripleSubArchToTupleSubArch(GnuTT.getSubArch());
+}
+
+TargetTuple::VendorType TargetTuple::getVendor() const {
+  return convertTripleVendorToTupleVendor(GnuTT.getVendor());
+}
+
+TargetTuple::OSType TargetTuple::getOS() const {
+  return convertTripleOSToTupleOS(GnuTT.getOS());
+}
+
+TargetTuple::EnvironmentType TargetTuple::getEnvironment() const {
+  return convertTripleEnvToTupleEnv(GnuTT.getEnvironment());
+}
+
+TargetTuple::ObjectFormatType TargetTuple::getObjectFormat() const {
+  return convertTripleObjFmtToTupleObjFmt(GnuTT.getObjectFormat());
+}

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
 
 #include "AArch64FrameLowering.h"
 #include "AArch64ISelLowering.h"
 #include "AArch64InstrInfo.h"
 #include "AArch64RegisterInfo.h"
 #include "AArch64SelectionDAGInfo.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 #include <string>
 
 #define GET_SUBTARGETINFO_HEADER
 #include "AArch64GenSubtargetInfo.inc"
 
 namespace llvm {
public:
   const AArch64TargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
   const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const AArch64RegisterInfo *getRegisterInfo() const override {
     return &getInstrInfo()->getRegisterInfo();
   }
   const Triple &getTargetTriple() const { return TargetTriple; }
+  // FIXME: Return a references once our member is a TargetTuple.
+  const TargetTuple getTargetTuple() const { return TargetTuple(TargetTriple); }
   bool enableMachineScheduler() const override { return true; }
   bool enablePostRAScheduler() const override {
     return isCortexA53() || isCortexA57();
   }
 
   bool hasV8_1aOps() const { return HasV8_1aOps; }
 
   bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
 
   ParseSubtargetFeatures(CPUString, FS);
   return *this;
 }
 
 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
                                    const TargetMachine &TM, bool LittleEndian)
-    : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
+    : AArch64GenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others),
       HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false),
       HasCRC(false), HasPerfMon(false), HasZeroCycleRegMove(false),
       HasZeroCycleZeroing(false), StrictAlign(false), ReserveX18(false),
       IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
       TLInfo(TM, *this) {}
 
 /// ClassifyGlobalReference - Find the target operand flags that describe

llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
   // Encoded as a small-endian 32-bit word in the stream.
   uint32_t Insn =
       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
 
   // Calling the auto-generated decoder function.
   return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
 }
 
-static MCSymbolizer *
-createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
-                                LLVMSymbolLookupCallback SymbolLookUp,
-                                void *DisInfo, MCContext *Ctx,
-                                std::unique_ptr<MCRelocationInfo> &&RelInfo) {
+static MCSymbolizer *createAArch64ExternalSymbolizer(
+    const TargetTuple &TT, LLVMOpInfoCallback GetOpInfo,
+    LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
   return new llvm::AArch64ExternalSymbolizer(*Ctx, move(RelInfo), GetOpInfo,
                                              SymbolLookUp, DisInfo);
 }
 
 extern "C" void LLVMInitializeAArch64Disassembler() {
   TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
                                          createAArch64Disassembler);
   TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64.h"
 #include "AArch64RegisterInfo.h"
 #include "MCTargetDesc/AArch64FixupKinds.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCValue.h"
if (isByteSwappedFixup(Fixup.getValue()))
       Value = ByteSwap_32(unsigned(Value));
   }
   AArch64AsmBackend::applyFixup (Fixup, Data, DataSize, Value, IsPCRel);
 }
 }
 
 MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
                                               const MCRegisterInfo &MRI,
-                                              const Triple &TheTriple,
+                                              const TargetTuple &TT,
                                               StringRef CPU) {
-  if (TheTriple.isOSBinFormatMachO())
+  if (TT.isOSBinFormatMachO())
     return new DarwinAArch64AsmBackend(T, MRI);
 
-  assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target");
-  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
+  assert(TT.isOSBinFormatELF() && "Expect either MachO or ELF target");
+  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true);
 }
 
 MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
                                               const MCRegisterInfo &MRI,
-                                              const Triple &TheTriple,
+                                              const TargetTuple &TT,
                                               StringRef CPU) {
-  assert(TheTriple.isOSBinFormatELF() &&
+  assert(TT.isOSBinFormatELF() &&
          "Big endian is only supported for ELF targets!");
-  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
+  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   return new ELFAArch64AsmBackend(T, OSABI,
                                   /*IsLittleEndian=*/false);
 }

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp

 // regions of data and code.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64TargetStreamer.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCExpr.h"
MCELFStreamer *createAArch64ELFStreamer(MCContext &Context, MCAsmBackend &TAB,
   AArch64ELFStreamer *S = new AArch64ELFStreamer(Context, TAB, OS, Emitter);
   if (RelaxAll)
     S->getAssembler().setRelaxAll(true);
   return S;
 }
 
 MCTargetStreamer *
 createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
-  const Triple &TT = STI.getTargetTriple();
+  const TargetTuple &TT = STI.getTargetTuple();
   if (TT.isOSBinFormatELF())
     return new AArch64TargetELFStreamer(S);
   return nullptr;
 }
 }

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h

 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
 class MCStreamer;
 class Target;
-class Triple;
+class TargetTuple;
 
 struct AArch64MCAsmInfoDarwin : public MCAsmInfoDarwin {
   explicit AArch64MCAsmInfoDarwin();
   const MCExpr *
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
 };
 
 struct AArch64MCAsmInfoELF : public MCAsmInfoELF {
-  explicit AArch64MCAsmInfoELF(const Triple &T);
+  explicit AArch64MCAsmInfoELF(const TargetTuple &TT);
 };
 
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp

 //===-- AArch64MCAsmInfo.cpp - AArch64 asm properties ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the AArch64MCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
 enum AsmWriterVariantTy {
   Default = -1,
const MCExpr *AArch64MCAsmInfoDarwin::getExprForPersonalitySymbol(
   const MCExpr *Res =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_GOT, Context);
   MCSymbol *PCSym = Context.createTempSymbol();
   Streamer.EmitLabel(PCSym);
   const MCExpr *PC = MCSymbolRefExpr::create(PCSym, Context);
   return MCBinaryExpr::createSub(Res, PC, Context);
 }
 
-AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) {
-  if (T.getArch() == Triple::aarch64_be)
+AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const TargetTuple &T) {
+  if (T.getArch() == TargetTuple::aarch64_be)
     IsLittleEndian = false;
 
   // We prefer NEON instructions to be printed in the short form.
   AssemblerDialect = AsmWriterVariant == Default ? 0 : AsmWriterVariant;
 
   PointerSize = 8;
 
   // ".comm align is in bytes but .align is pow-2."

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

 class MCInstPrinter;
 class MCRegisterInfo;
 class MCObjectWriter;
 class MCStreamer;
 class MCSubtargetInfo;
 class MCTargetStreamer;
 class StringRef;
 class Target;
-class Triple;
+class TargetTuple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheAArch64leTarget;
 extern Target TheAArch64beTarget;
 extern Target TheARM64Target;
 
 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
                                           const MCRegisterInfo &MRI,
                                           MCContext &Ctx);
 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const Triple &TT, StringRef CPU);
+                                        const TargetTuple &TT, StringRef CPU);
 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const Triple &TT, StringRef CPU);
+                                        const TargetTuple &TT, StringRef CPU);
 
 MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
                                              uint8_t OSABI,
                                              bool IsLittleEndian);
 
 MCObjectWriter *createAArch64MachObjectWriter(raw_pwrite_stream &OS,
                                               uint32_t CPUType,
                                               uint32_t CPUSubtype);

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

 #include "AArch64GenRegisterInfo.inc"
 
 static MCInstrInfo *createAArch64MCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitAArch64MCInstrInfo(X);
   return X;
 }
 
-static MCSubtargetInfo *
-createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+static MCSubtargetInfo *createAArch64MCSubtargetInfo(const TargetTuple &TT,
+                                                     StringRef CPU,
+                                                     StringRef FS) {
   if (CPU.empty())
     CPU = "generic";
 
   return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
+static MCRegisterInfo *createAArch64MCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitAArch64MCRegisterInfo(X, AArch64::LR);
   return X;
 }
 
 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TheTriple) {
+                                         const TargetTuple &TT) {
   MCAsmInfo *MAI;
-  if (TheTriple.isOSBinFormatMachO())
+  if (TT.isOSBinFormatMachO())
     MAI = new AArch64MCAsmInfoDarwin();
   else {
-    assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
-    MAI = new AArch64MCAsmInfoELF(TheTriple);
+    assert(TT.isOSBinFormatELF() && "Only expect Darwin or ELF");
+    MAI = new AArch64MCAsmInfoELF(TT);
   }
 
   // Initial state of the frame pointer is SP.
   unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
-static MCCodeGenInfo *createAArch64MCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createAArch64MCCodeGenInfo(const TargetTuple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
   assert((TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()) &&
          "Only expect Darwin and ELF targets");
 
   if (CM == CodeModel::Default)
     CM = CodeModel::Small;
static MCCodeGenInfo *createAArch64MCCodeGenInfo(const TargetTuple &TT,
   else if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
     RM = Reloc::Static;
 
   MCCodeGenInfo *X = new MCCodeGenInfo();
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
+static MCInstPrinter *createAArch64MCInstPrinter(const TargetTuple &TT,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
                                                  const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new AArch64InstPrinter(MAI, MII, MRI);
   if (SyntaxVariant == 1)
     return new AArch64AppleInstPrinter(MAI, MII, MRI);
 
   return nullptr;
 }
 
-static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
+static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx,
                                      MCAsmBackend &TAB, raw_pwrite_stream &OS,
                                      MCCodeEmitter *Emitter, bool RelaxAll) {
   return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
 }
 
 static MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
                                        raw_pwrite_stream &OS,
                                        MCCodeEmitter *Emitter, bool RelaxAll,

llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
     FP32Denormals = false;
     FP64Denormals = false;
   }
   return *this;
 }
 
 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
                                  TargetMachine &TM)
-    : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
-      DumpCode(false), R600ALUInst(false), HasVertexCache(false),
-      TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
-      FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
-      CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
-      EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
-      EnableUnsafeDSOffsetFolding(false),
+    : AMDGPUGenSubtargetInfo(TargetTuple(TT), GPU, FS), DevName(GPU),
+      Is64bit(false), DumpCode(false), R600ALUInst(false),
+      HasVertexCache(false), TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600),
+      FP64(false), FP64Denormals(false), FP32Denormals(false),
+      FastFMAF32(false), CaymanISA(false), FlatAddressSpace(false),
+      EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true),
+      EnableLoadStoreOpt(false), EnableUnsafeDSOffsetFolding(false),
       WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
       EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
       GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
       IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),
       FrameLowering(TargetFrameLowering::StackGrowsUp,
                     64 * 16, // Maximum stack alignment (long16)
                     0),
       InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createAMDGPUELFObjectWriter(Is64Bit, OS);
   }
 };
 
 } // end anonymous namespace
 
 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
-                                           const Triple &TT, StringRef CPU) {
-  Triple TargetTriple(TT);
-
+                                           const TargetTuple &TT,
+                                           StringRef CPU) {
   // Use 64-bit ELF for amdgcn
-  return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn);
+  return new ELFAMDGPUAsmBackend(T, TT.getArch() == TargetTuple::amdgcn);
 }

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCASMINFO_H
 #define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 namespace llvm {
 
-class Triple;
+class TargetTuple;
 
 // If you need to create another MCAsmInfo class, which inherits from MCAsmInfo,
 // you will need to make sure your new class sets PrivateGlobalPrefix to
 // a prefix that won't appear in a function name.  The default value
 // for PrivateGlobalPrefix is 'L', so it will consider any function starting
 // with 'L' as a local symbol.
 class AMDGPUMCAsmInfo : public MCAsmInfoELF {
 public:
-  explicit AMDGPUMCAsmInfo(const Triple &TT);
+  explicit AMDGPUMCAsmInfo(const TargetTuple &TT);
 };
 } // namespace llvm
 #endif

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp

 //===-- MCTargetDesc/AMDGPUMCAsmInfo.cpp - Assembly Info ------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 /// \file
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUMCAsmInfo.h"
 
 using namespace llvm;
-AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() {
+AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const TargetTuple &TT) : MCAsmInfoELF() {
   HasSingleParameterDotFile = false;
   //===------------------------------------------------------------------===//
   MaxInstLength = 16;
   SeparatorString = "\n";
   CommentString = ";";
   PrivateLabelPrefix = "";
   InlineAsmStart = ";#ASMSTART";
   InlineAsmEnd = ";#ASMEND";

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h

 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
-class Triple;
+class TargetTuple;
 class raw_pwrite_stream;
 class raw_ostream;
 
 extern Target TheAMDGPUTarget;
 extern Target TheGCNTarget;
 
 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
                                        const MCRegisterInfo &MRI,
                                        MCContext &Ctx);
 
 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
                                      const MCRegisterInfo &MRI,
                                      MCContext &Ctx);
 
 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     const Triple &TT, StringRef CPU);
+                                     const TargetTuple &TT, StringRef CPU);
 
 MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
                                             raw_pwrite_stream &OS);
 } // End llvm namespace
 
 #define GET_REGINFO_ENUM
 #include "AMDGPUGenRegisterInfo.inc"
 
 #define GET_INSTRINFO_ENUM
 #include "AMDGPUGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_ENUM
 #include "AMDGPUGenSubtargetInfo.inc"
 
 #endif

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

 #include "AMDGPUGenRegisterInfo.inc"
 
 static MCInstrInfo *createAMDGPUMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitAMDGPUMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createAMDGPUMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitAMDGPUMCRegisterInfo(X, 0);
   return X;
 }
 
-static MCSubtargetInfo *
-createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(const TargetTuple &TT,
+                                                    StringRef CPU,
+                                                    StringRef FS) {
   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const TargetTuple &TT,
                                                 Reloc::Model RM,
                                                 CodeModel::Model CM,
                                                 CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
+static MCInstPrinter *createAMDGPUMCInstPrinter(const TargetTuple &T,
                                                 unsigned SyntaxVariant,
                                                 const MCAsmInfo &MAI,
                                                 const MCInstrInfo &MII,
                                                 const MCRegisterInfo &MRI) {
   return new AMDGPUInstPrinter(MAI, MII, MRI);
 }
 
 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,

llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

void ARMAsmPrinter::emitAttributes() {
   // Compute ARM ELF Attributes based on the default subtarget that
   // we'd have constructed. The existing ARM behavior isn't LTO clean
   // anyhow.
   // FIXME: For ifunc related functions we could iterate over and look
   // for a feature string that doesn't match the default one.
   const Triple &TT = TM.getTargetTriple();
   StringRef CPU = TM.getTargetCPU();
   StringRef FS = TM.getTargetFeatureString();
-  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
+  std::string ArchFS = ARM_MC::ParseARMTargetTuple(TargetTuple(TT), CPU);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
     else
       ArchFS = FS;
   }
   const ARMBaseTargetMachine &ATM =
       static_cast<const ARMBaseTargetMachine &>(TM);

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

if (STI.isThumb1Only())
     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
 
   return new ARMFrameLowering(STI);
 }
 
 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS,
                            const ARMBaseTargetMachine &TM, bool IsLittle)
-    : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
+    : ARMGenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others),
       ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
       TargetTriple(TT), Options(TM.Options), TM(TM),
       FrameLowering(initializeFrameLowering(CPU, FS)),
       // At this point initializeSubtargetDependencies has been called so
       // we can query directly.
       InstrInfo(isThumb1Only()
                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
                     : !isThumb()
if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s"))
       CPUString = "swift";
     else
       CPUString = "generic";
   }
 
   // Insert the architecture feature derived from the target triple into the
   // feature string. This is important for setting features that are implied
   // based on the architecture version.
-  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
+  std::string ArchFS =
+      ARM_MC::ParseARMTargetTuple(TargetTuple(TargetTriple), CPUString);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
     else
       ArchFS = FS;
   }
   ParseSubtargetFeatures(CPUString, ArchFS);
 

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

 
 namespace {
 
 class ARMAsmBackend : public MCAsmBackend {
   const MCSubtargetInfo *STI;
   bool isThumbMode;    // Currently emitting Thumb code.
   bool IsLittleEndian; // Big or little endian.
 public:
-  ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle)
+  ARMAsmBackend(const Target &T, const TargetTuple &TT, bool IsLittle)
       : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
         isThumbMode(TT.getArchName().startswith("thumb")),
         IsLittleEndian(IsLittle) {}
 
   ~ARMAsmBackend() override { delete STI; }
 
   unsigned getNumFixupKinds() const override {
     return ARM::NumTargetFixupKinds;

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

case ARM::AK_ARMV7M:
     return MachO::CPU_SUBTYPE_ARM_V7M;
   case ARM::AK_ARMV7EM:
     return MachO::CPU_SUBTYPE_ARM_V7EM;
   }
 }
 
 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const Triple &TheTriple, StringRef CPU,
+                                        const TargetTuple &TT, StringRef CPU,
                                         bool isLittle) {
-  switch (TheTriple.getObjectFormat()) {
+  switch (TT.getObjectFormat()) {
   default:
     llvm_unreachable("unsupported object format");
-  case Triple::MachO: {
-    MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
-    return new ARMAsmBackendDarwin(T, TheTriple, CS);
-  }
-  case Triple::COFF:
-    assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
-    return new ARMAsmBackendWinCOFF(T, TheTriple);
-  case Triple::ELF:
-    assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
-    uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
-    return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle);
+  case TargetTuple::MachO: {
+    MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TT.getArchName());
+    return new ARMAsmBackendDarwin(T, TT, CS);
+  }
+  case TargetTuple::COFF:
+    assert(TT.isOSWindows() && "non-Windows ARM COFF is not supported");
+    return new ARMAsmBackendWinCOFF(T, TT);
+  case TargetTuple::ELF:
+    assert(TT.isOSBinFormatELF() && "using ELF for non-ELF target");
+    uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
+    return new ARMAsmBackendELF(T, TT, OSABI, isLittle);
   }
 }
 
 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const Triple &TT, StringRef CPU) {
+                                          const TargetTuple &TT,
+                                          StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, true);
 }
 
 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const Triple &TT, StringRef CPU) {
+                                          const TargetTuple &TT,
+                                          StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, false);
 }
 
 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            const Triple &TT, StringRef CPU) {
+                                            const TargetTuple &TT,
+                                            StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, true);
 }
 
 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            const Triple &TT, StringRef CPU) {
+                                            const TargetTuple &TT,
+                                            StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, false);
 }

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h

 #include "llvm/Support/MachO.h"
 
 using namespace llvm;
 
 namespace {
 class ARMAsmBackendDarwin : public ARMAsmBackend {
 public:
   const MachO::CPUSubTypeARM Subtype;
-  ARMAsmBackendDarwin(const Target &T, const Triple &TT,
+  ARMAsmBackendDarwin(const Target &T, const TargetTuple &TT,
                       MachO::CPUSubTypeARM st)
       : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) {
     HasDataInCodeSupport = true;
   }
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createARMMachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPU_TYPE_ARM,
                                      Subtype);
   }
 };
 }
 
 #endif

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h

 #ifndef LLVM_LIB_TARGET_ARM_ELFARMASMBACKEND_H
 #define LLVM_LIB_TARGET_ARM_ELFARMASMBACKEND_H
 
 using namespace llvm;
 namespace {
 class ARMAsmBackendELF : public ARMAsmBackend {
 public:
   uint8_t OSABI;
-  ARMAsmBackendELF(const Target &T, const Triple &TT, uint8_t OSABI,
+  ARMAsmBackendELF(const Target &T, const TargetTuple &TT, uint8_t OSABI,
                    bool IsLittle)
       : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createARMELFObjectWriter(OS, OSABI, isLittle());
   }
 };
 }
 
 #endif

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h

 #ifndef LLVM_LIB_TARGET_ARM_ARMASMBACKENDWINCOFF_H
 #define LLVM_LIB_TARGET_ARM_ARMASMBACKENDWINCOFF_H
 
 using namespace llvm;
 
 namespace {
 class ARMAsmBackendWinCOFF : public ARMAsmBackend {
 public:
-  ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple)
-      : ARMAsmBackend(T, TheTriple, true) {}
+  ARMAsmBackendWinCOFF(const Target &T, const TargetTuple &TT)
+      : ARMAsmBackend(T, TT, true) {}
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false);
   }
 };
 }
 
 #endif

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

 }
 
 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S) {
   return new ARMTargetStreamer(S);
 }
 
 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
                                                 const MCSubtargetInfo &STI) {
-  const Triple &TT = STI.getTargetTriple();
+  const TargetTuple &TT = STI.getTargetTuple();
   if (TT.isOSBinFormatELF())
     return new ARMTargetELFStreamer(S);
   return new ARMTargetStreamer(S);
 }
 
 MCELFStreamer *createARMELFStreamer(MCContext &Context, MCAsmBackend &TAB,
                                     raw_pwrite_stream &OS,
                                     MCCodeEmitter *Emitter, bool RelaxAll,

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h

 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCASMINFO_H
 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoCOFF.h"
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit ARMMCAsmInfoDarwin(const Triple &TheTriple);
+  explicit ARMMCAsmInfoDarwin(const TargetTuple &TT);
 };
 
 class ARMELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit ARMELFMCAsmInfo(const Triple &TT);
+  explicit ARMELFMCAsmInfo(const TargetTuple &TT);
 
   void setUseIntegratedAssembler(bool Value) override;
 };
 
 class ARMCOFFMCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
   void anchor() override;
 
 public:

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp

 //===-- ARMMCAsmInfo.cpp - ARM asm properties -----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the ARMMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 void ARMMCAsmInfoDarwin::anchor() { }
 
-ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::armeb) ||
-      (TheTriple.getArch() == Triple::thumbeb))
+ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const TargetTuple &TT) {
+  if ((TT.getArch() == TargetTuple::armeb) ||
+      (TT.getArch() == TargetTuple::thumbeb))
     IsLittleEndian = false;
 
   Data64bitsDirective = nullptr;
   CommentString = "@";
   Code16Directive = ".code\t16";
   Code32Directive = ".code\t32";
   UseDataRegionDirectives = true;
 
   SupportsDebugInformation = true;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::SjLj;
 
   UseIntegratedAssembler = true;
 }
 
 void ARMELFMCAsmInfo::anchor() { }
 
-ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::armeb) ||
-      (TheTriple.getArch() == Triple::thumbeb))
+ARMELFMCAsmInfo::ARMELFMCAsmInfo(const TargetTuple &TT) {
+  if ((TT.getArch() == TargetTuple::armeb) ||
+      (TT.getArch() == TargetTuple::thumbeb))
     IsLittleEndian = false;
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;
 
   Data64bitsDirective = nullptr;
   CommentString = "@";
   Code16Directive = ".code\t16";
   Code32Directive = ".code\t32";
 
   SupportsDebugInformation = true;
 
   // Exceptions handling
-  switch (TheTriple.getOS()) {
-  case Triple::Bitrig:
-  case Triple::NetBSD:
+  switch (TT.getOS()) {
+  case TargetTuple::Bitrig:
+  case TargetTuple::NetBSD:
     ExceptionsType = ExceptionHandling::DwarfCFI;
     break;
   default:
     ExceptionsType = ExceptionHandling::ARM;
     break;
   }
 
   // foo(plt) instead of foo@plt

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

public:
 
   bool isThumb(const MCSubtargetInfo &STI) const {
     return STI.getFeatureBits()[ARM::ModeThumb];
   }
   bool isThumb2(const MCSubtargetInfo &STI) const {
     return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
   }
   bool isTargetMachO(const MCSubtargetInfo &STI) const {
-    const Triple &TT = STI.getTargetTriple();
+    const TargetTuple &TT = STI.getTargetTuple();
     return TT.isOSBinFormatMachO();
   }
 
   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
 
   // getBinaryCodeForInstr - TableGen'erated function for getting the
   // binary encoding for an instruction.
   uint64_t getBinaryCodeForInstr(const MCInst &MI,

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class MCStreamer;
 class MCRelocationInfo;
 class MCTargetStreamer;
 class StringRef;
 class Target;
-class Triple;
+class TargetTuple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheARMLETarget, TheThumbLETarget;
 extern Target TheARMBETarget, TheThumbBETarget;
 
 namespace ARM_MC {
-std::string ParseARMTriple(const Triple &TT, StringRef CPU);
+std::string ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU);
 
 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
-MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
+MCSubtargetInfo *createARMMCSubtargetInfo(const TargetTuple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
                                              formatted_raw_ostream &OS,
                                              MCInstPrinter *InstPrint,
                                              bool isVerboseAsm);
 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
                                                 const MCSubtargetInfo &STI);
 
 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
 
 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
 
 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const Triple &TT, StringRef CPU,
+                                  const TargetTuple &TT, StringRef CPU,
                                   bool IsLittleEndian);
 
 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+                                    const TargetTuple &TT, StringRef CPU);
 
 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+                                    const TargetTuple &TT, StringRef CPU);
 
 MCAsmBackend *createThumbLEAsmBackend(const Target &T,
                                       const MCRegisterInfo &MRI,
-                                      const Triple &TT, StringRef CPU);
+                                      const TargetTuple &TT, StringRef CPU);
 
 MCAsmBackend *createThumbBEAsmBackend(const Target &T,
                                       const MCRegisterInfo &MRI,
-                                      const Triple &TT, StringRef CPU);
+                                      const TargetTuple &TT, StringRef CPU);
 
 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
 // object file.
 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
                                      raw_pwrite_stream &OS,
                                      MCCodeEmitter *Emitter, bool RelaxAll);
 
 /// Construct an ELF Mach-O object writer.

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

 // This file provides ARM specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMBaseInfo.h"
 #include "ARMMCAsmInfo.h"
 #include "ARMMCTargetDesc.h"
 #include "InstPrinter/ARMInstPrinter.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"

 }
 
 #define GET_INSTRINFO_MC_DESC
 #include "ARMGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "ARMGenSubtargetInfo.inc"
 
-std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
-  bool isThumb =
-      TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
+std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) {
+  bool isThumb = TT.getArch() == TargetTuple::thumb ||
+                 TT.getArch() == TargetTuple::thumbeb;
 
   bool NoCPU = CPU == "generic" || CPU.empty();
   std::string ARMArchFeature;
   switch (TT.getSubArch()) {
   default:
     llvm_unreachable("invalid sub-architecture for ARM");
-  case Triple::ARMSubArch_v8:
+  case TargetTuple::ARMSubArch_v8:
     if (NoCPU)
       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
       ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
                        "+trustzone,+t2xtpk,+crypto,+crc";
     else
       // Use CPU to figure out the exact features
       ARMArchFeature = "+v8";
     break;
-  case Triple::ARMSubArch_v8_1a:
+  case TargetTuple::ARMSubArch_v8_1a:
     if (NoCPU)
       // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a
       ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
                        "+trustzone,+t2xtpk,+crypto,+crc";
     else
       // Use CPU to figure out the exact features
       ARMArchFeature = "+v8.1a";
     break;
-  case Triple::ARMSubArch_v7m:
+  case TargetTuple::ARMSubArch_v7m:
     isThumb = true;
     if (NoCPU)
       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
     else
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case Triple::ARMSubArch_v7em:
+  case TargetTuple::ARMSubArch_v7em:
     if (NoCPU)
       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
       //       FeatureT2XtPk, FeatureMClass
       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
     else
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case Triple::ARMSubArch_v7s:
+  case TargetTuple::ARMSubArch_v7s:
     if (NoCPU)
       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
       //      Swift
       ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
     else
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case Triple::ARMSubArch_v7:
+  case TargetTuple::ARMSubArch_v7:
     // v7 CPUs have lots of different feature sets. If no CPU is specified,
     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
     // the "minimum" feature set and use CPU string to figure out the exact
     // features.
     if (NoCPU)
       // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
       ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
     else
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case Triple::ARMSubArch_v6t2:
+  case TargetTuple::ARMSubArch_v6t2:
     ARMArchFeature = "+v6t2";
     break;
-  case Triple::ARMSubArch_v6k:
+  case TargetTuple::ARMSubArch_v6k:
     ARMArchFeature = "+v6k";
     break;
-  case Triple::ARMSubArch_v6m:
+  case TargetTuple::ARMSubArch_v6m:
     isThumb = true;
     if (NoCPU)
       // v6m: FeatureNoARM, FeatureMClass
       ARMArchFeature = "+v6m,+noarm,+mclass";
     else
       ARMArchFeature = "+v6";
     break;
-  case Triple::ARMSubArch_v6:
+  case TargetTuple::ARMSubArch_v6:
     ARMArchFeature = "+v6";
     break;
-  case Triple::ARMSubArch_v5te:
+  case TargetTuple::ARMSubArch_v5te:
     ARMArchFeature = "+v5te";
     break;
-  case Triple::ARMSubArch_v5:
+  case TargetTuple::ARMSubArch_v5:
     ARMArchFeature = "+v5t";
     break;
-  case Triple::ARMSubArch_v4t:
+  case TargetTuple::ARMSubArch_v4t:
     ARMArchFeature = "+v4t";
     break;
-  case Triple::NoSubArch:
+  case TargetTuple::NoSubArch:
     break;
   }
 
   if (isThumb) {
     if (ARMArchFeature.empty())
       ARMArchFeature = "+thumb-mode";
     else
       ARMArchFeature += ",+thumb-mode";
   }
 
   if (TT.isOSNaCl()) {
     if (ARMArchFeature.empty())
       ARMArchFeature = "+nacl-trap";
     else
       ARMArchFeature += ",+nacl-trap";
   }
 
   return ARMArchFeature;
 }
 
-MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
+MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const TargetTuple &TT,
                                                   StringRef CPU, StringRef FS) {
-  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
+  std::string ArchFS = ARM_MC::ParseARMTargetTuple(TT, CPU);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
     else
       ArchFS = FS;
   }
 
   return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
 }
 
 static MCInstrInfo *createARMMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitARMMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
+static MCRegisterInfo *createARMMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
   return X;
 }
 
 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
+                                     const TargetTuple &TT) {
   MCAsmInfo *MAI;
-  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
-    MAI = new ARMMCAsmInfoDarwin(TheTriple);
-  else if (TheTriple.isWindowsMSVCEnvironment())
+  if (TT.isOSDarwin() || TT.isOSBinFormatMachO())
+    MAI = new ARMMCAsmInfoDarwin(TT);
+  else if (TT.isWindowsMSVCEnvironment())
     MAI = new ARMCOFFMCAsmInfoMicrosoft();
-  else if (TheTriple.isOSWindows())
+  else if (TT.isOSWindows())
     MAI = new ARMCOFFMCAsmInfoGNU();
   else
-    MAI = new ARMELFMCAsmInfo(TheTriple);
+    MAI = new ARMELFMCAsmInfo(TT);
 
   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
 
   return MAI;
 }
 
-static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
+static MCCodeGenInfo *createARMMCCodeGenInfo(const TargetTuple &TT,
+                                             Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (RM == Reloc::Default) {
     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
     RM = TT.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
   }
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
+static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx,
                                      MCAsmBackend &MAB, raw_pwrite_stream &OS,
                                      MCCodeEmitter *Emitter, bool RelaxAll) {
   return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
-                              T.getArch() == Triple::thumb);
+                              TT.getArch() == TargetTuple::thumb);
 }
 
 static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
                                           raw_pwrite_stream &OS,
                                           MCCodeEmitter *Emitter, bool RelaxAll,
                                           bool DWARFMustBeAtTheEnd) {
   return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
 }
 
-static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
+static MCInstPrinter *createARMMCInstPrinter(const TargetTuple &TT,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
                                              const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new ARMInstPrinter(MAI, MII, MRI);
   return nullptr;
 }
 
-static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
+static MCRelocationInfo *createARMMCRelocationInfo(const TargetTuple &TT,
                                                    MCContext &Ctx) {
   if (TT.isOSBinFormatMachO())
     return createARMMachORelocationInfo(Ctx);
   // Default to the stock relocation info.
   return llvm::createMCRelocationInfo(TT, Ctx);
 }
 
 namespace {

llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp

 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "BPFGenSubtargetInfo.inc"
 
 void BPFSubtarget::anchor() {}
 
 BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const TargetMachine &TM)
-    : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
-      TLInfo(TM, *this) {}
+    : BPFGenSubtargetInfo(TargetTuple(TT), CPU, FS), InstrInfo(),
+      FrameLowering(*this), TLInfo(TM, *this) {}

llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp

 
 MCObjectWriter *BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
   return createBPFELFObjectWriter(OS, 0, IsLittleEndian);
 }
 }
 
 MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const Triple &TT, StringRef CPU) {
+                                        const TargetTuple &TT, StringRef CPU) {
   return new BPFAsmBackend(/*IsLittleEndian=*/true);
 }
 
 MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const Triple &TT, StringRef CPU) {
+                                          const TargetTuple &TT,
+                                          StringRef CPU) {
   return new BPFAsmBackend(/*IsLittleEndian=*/false);
 }

llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H
 #define LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H
 
 #include "llvm/ADT/StringRef.h"
 #include "llvm/MC/MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 
 namespace llvm {
 class Target;
-class Triple;
 
 class BPFMCAsmInfo : public MCAsmInfo {
 public:
-  explicit BPFMCAsmInfo(const Triple &TT) {
-    if (TT.getArch() == Triple::bpfeb)
+  explicit BPFMCAsmInfo(const TargetTuple &TT) {
+    if (TT.getArch() == TargetTuple::bpfeb)
       IsLittleEndian = false;
 
     PrivateGlobalPrefix = ".L";
     WeakRefDirective = "\t.weak\t";
 
     UsesELFSectionDirectiveForBSS = true;
     HasSingleParameterDotFile = false;
     HasDotTypeDotSizeDirective = false;
 
     SupportsDebugInformation = true;
   }
 };
 }
 
 #endif

llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h

 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class StringRef;
 class Target;
-class Triple;
+class TargetTuple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheBPFleTarget;
 extern Target TheBPFbeTarget;
 extern Target TheBPFTarget;
 
 MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII,
                                       const MCRegisterInfo &MRI,
                                       MCContext &Ctx);
 MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
 
 MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const Triple &TT, StringRef CPU);
+                                  const TargetTuple &TT, StringRef CPU);
 MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+                                    const TargetTuple &TT, StringRef CPU);
 
 MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS,
                                          uint8_t OSABI, bool IsLittleEndian);
 }
 
 // Defines symbolic names for BPF registers.  This defines a mapping from
 // register name to register number.
 //

llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp

 using namespace llvm;
 
 static MCInstrInfo *createBPFMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitBPFMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createBPFMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createBPFMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */);
   return X;
 }
 
-static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT,
+static MCSubtargetInfo *createBPFMCSubtargetInfo(const TargetTuple &TT,
                                                  StringRef CPU, StringRef FS) {
   return createBPFMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createBPFMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
+static MCCodeGenInfo *createBPFMCCodeGenInfo(const TargetTuple &TT,
+                                             Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCStreamer *createBPFMCStreamer(const Triple &T,
-                                       MCContext &Ctx, MCAsmBackend &MAB,
-                                       raw_pwrite_stream &OS, MCCodeEmitter *Emitter,
-                                       bool RelaxAll) {
+static MCStreamer *createBPFMCStreamer(const TargetTuple &TT, MCContext &Ctx,
+                                       MCAsmBackend &MAB, raw_pwrite_stream &OS,
+                                       MCCodeEmitter *Emitter, bool RelaxAll) {
   return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
 }
 
-static MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
+static MCInstPrinter *createBPFMCInstPrinter(const TargetTuple &TT,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
                                              const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new BPFInstPrinter(MAI, MII, MRI);
   return 0;
 }

llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp

HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   }
 
   ParseSubtargetFeatures(CPUString, FS);
   return *this;
 }
 
 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
                                    StringRef FS, const TargetMachine &TM)
-    : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
+    : HexagonGenSubtargetInfo(TargetTuple(TT), CPU, FS), CPUString(CPU),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       FrameLowering() {
 
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUString);
 
   // UseMemOps on by default unless disabled explicitly
   if (DisableMemOps)

llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

bool writeNopData(uint64_t Count,
     return true;
   }
 };
 } // end anonymous namespace
 
 namespace llvm {
 MCAsmBackend *createHexagonAsmBackend(Target const &T,
                                       MCRegisterInfo const & /*MRI*/,
-                                      const Triple &TT, StringRef CPU) {
+                                      const TargetTuple &TT, StringRef CPU) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   return new HexagonAsmBackend(T, OSABI, CPU);
 }
 }

llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h

 
 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCASMINFO_H
 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCASMINFO_H
 
 #include "llvm/ADT/StringRef.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class HexagonMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit HexagonMCAsmInfo(const Triple &TT);
+  explicit HexagonMCAsmInfo(const TargetTuple &TT);
 };
 
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp

 
 #include "HexagonMCAsmInfo.h"
 
 using namespace llvm;
 
 // Pin the vtable to this file.
 void HexagonMCAsmInfo::anchor() {}
 
-HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
+HexagonMCAsmInfo::HexagonMCAsmInfo(const TargetTuple &TT) {
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";
   Data64bitsDirective = nullptr;  // .xword is only supported by V9.
   ZeroDirective = "\t.skip\t";
   CommentString = "//";
 
   LCOMMDirectiveAlignmentType = LCOMM::ByteAlignment;
   InlineAsmStart = "# InlineAsm Start";
   InlineAsmEnd = "# InlineAsm End";
   ZeroDirective = "\t.space\t";
   AscizDirective = "\t.string\t";
 
   SupportsDebugInformation = true;
   UsesELFSectionDirectiveForBSS  = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
 }

llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h

 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
-class Triple;
+class TargetTuple;
 class StringRef;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheHexagonTarget;
 
 extern const InstrStage HexagonStages[];
 
 MCInstrInfo *createHexagonMCInstrInfo();
 
 MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII,
                                           MCRegisterInfo const &MRI,
                                           MCContext &MCT);
 
 MCAsmBackend *createHexagonAsmBackend(Target const &T,
                                       MCRegisterInfo const &MRI,
-                                      const Triple &TT, StringRef CPU);
+                                      const TargetTuple &TT, StringRef CPU);
 
 MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
                                              uint8_t OSABI, StringRef CPU);
 
 } // End llvm namespace
 
 // Define symbolic names for Hexagon registers.  This defines a mapping from
 // register name to register number.

llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

 #include "HexagonGenRegisterInfo.inc"
 
 MCInstrInfo *llvm::createHexagonMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitHexagonMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createHexagonMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitHexagonMCRegisterInfo(X, Hexagon::R0);
   return X;
 }
 
-static MCSubtargetInfo *
-createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+static MCSubtargetInfo *createHexagonMCSubtargetInfo(const TargetTuple &TT,
+                                                     StringRef CPU,
+                                                     StringRef FS) {
   return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 namespace {
 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
 public:
   HexagonTargetAsmStreamer(MCStreamer &S,
                            formatted_raw_ostream &, bool,
HexagonMCELFStreamer &HexagonELFStreamer =
         static_cast<HexagonMCELFStreamer &>(getStreamer());
     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
         Symbol, Size, ByteAlignment, AccessSize);
   }
 };
 }
 
 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
+                                         const TargetTuple &TT) {
   MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
 
   // VirtualFP = (R30 + #0).
   MCCFIInstruction Inst =
       MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
-static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createHexagonMCCodeGenInfo(const TargetTuple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   // For the time being, use static relocations, since there's really no
   // support for PIC yet.
   X->initMCCodeGenInfo(Reloc::Static, CM, OL);
   return X;
 }
 
-static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
+static MCInstPrinter *createHexagonMCInstPrinter(const TargetTuple &TT,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
                                                  const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return (new HexagonInstPrinter(MAI, MII, MRI));
   else
     return nullptr;
 }
 
 static MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S,
                                                    formatted_raw_ostream &OS,
                                                    MCInstPrinter *InstPrint,
                                                    bool IsVerboseAsm) {
   return new HexagonTargetAsmStreamer(S,  OS, IsVerboseAsm, *InstPrint);
 }
 
-static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
+static MCStreamer *createMCStreamer(const TargetTuple &TT, MCContext &Context,
                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
                                     MCCodeEmitter *Emitter, bool RelaxAll) {
   return createHexagonELFStreamer(Context, MAB, OS, Emitter);
 }
 
 static MCTargetStreamer *
 createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) {
   return new HexagonTargetELFStreamer(S, STI);

llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H
 #define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class MSP430MCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit MSP430MCAsmInfo(const Triple &TT);
+  explicit MSP430MCAsmInfo(const TargetTuple &TT);
 };
 
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "MSP430MCAsmInfo.h"
 using namespace llvm;
 
 void MSP430MCAsmInfo::anchor() { }
 
-MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) {
+MSP430MCAsmInfo::MSP430MCAsmInfo(const TargetTuple &TT) {
   PointerSize = CalleeSaveStackSlotSize = 2;
 
   CommentString = ";";
 
   AlignmentIsInBytes = false;
   UsesELFSectionDirectiveForBSS = true;
 }

llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp

 #include "MSP430GenRegisterInfo.inc"
 
 static MCInstrInfo *createMSP430MCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitMSP430MCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createMSP430MCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitMSP430MCRegisterInfo(X, MSP430::PC);
   return X;
 }
 
-static MCSubtargetInfo *
-createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+static MCSubtargetInfo *createMSP430MCSubtargetInfo(const TargetTuple &TT,
+                                                    StringRef CPU,
+                                                    StringRef FS) {
   return createMSP430MCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createMSP430MCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createMSP430MCCodeGenInfo(const TargetTuple &TT,
                                                 Reloc::Model RM,
                                                 CodeModel::Model CM,
                                                 CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
+static MCInstPrinter *createMSP430MCInstPrinter(const TargetTuple &T,
                                                 unsigned SyntaxVariant,
                                                 const MCAsmInfo &MAI,
                                                 const MCInstrInfo &MII,
                                                 const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new MSP430InstPrinter(MAI, MII, MRI);
   return nullptr;
 }

llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp

 MSP430Subtarget &
 MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   ParseSubtargetFeatures("generic", FS);
   return *this;
 }
 
 MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
                                  const std::string &FS, const TargetMachine &TM)
-    : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(),
+    : MSP430GenSubtargetInfo(TargetTuple(TT), CPU, FS), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 #include "MipsGenAsmMatcher.inc"
 #undef GET_OPERAND_DIAGNOSTIC_TYPES
 
   };
 
   MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
                 const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options), STI(sti),
-        ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
-                                          sti.getCPU(), Options)) {
+        ABI(MipsABIInfo::computeTargetABI(sti.getTargetTuple(), sti.getCPU(),
+                                          Options)) {
     MCAsmParserExtension::Initialize(parser);
 
     parser.addAliasForDirective(".asciiz", ".asciz");
 
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
 
     // Remember the initial assembler options. The user can not modify these.
MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
     if (!isABI_O32() && !useOddSPReg() != 0)
       report_fatal_error("-mno-odd-spreg requires the O32 ABI");
 
     CurrentFn = nullptr;
 
     IsPicEnabled =
         (getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_);
 
-    Triple TheTriple(sti.getTargetTriple());
-    if ((TheTriple.getArch() == Triple::mips) ||
-        (TheTriple.getArch() == Triple::mips64))
+    const TargetTuple &TT = sti.getTargetTuple();
+    if ((TT.getArch() == TargetTuple::mips) ||
+        (TT.getArch() == TargetTuple::mips64))
       IsLittleEndian = false;
     else
       IsLittleEndian = true;
   }
 
   /// True if all of $fcc0 - $fcc7 exist for the current ISA.
   bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
 

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h

 //===---- MipsABIInfo.h - Information about MIPS ABI's --------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
 
 #include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/MC/MCRegisterInfo.h"
 
 namespace llvm {
 
 class MCTargetOptions;
 class StringRef;
 class TargetRegisterClass;
 
 class MipsABIInfo {
 public:
   enum class ABI { Unknown, O32, N32, N64, EABI };
 
 protected:
   ABI ThisABI;
 
 public:
   MipsABIInfo(ABI ThisABI) : ThisABI(ThisABI) {}
 
   static MipsABIInfo Unknown() { return MipsABIInfo(ABI::Unknown); }
   static MipsABIInfo O32() { return MipsABIInfo(ABI::O32); }
   static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
   static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
   static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); }
-  static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU,
+  static MipsABIInfo computeTargetABI(const TargetTuple &TT, StringRef CPU,
                                       const MCTargetOptions &Options);
 
   bool IsKnown() const { return ThisABI != ABI::Unknown; }
   bool IsO32() const { return ThisABI == ABI::O32; }
   bool IsN32() const { return ThisABI == ABI::N32; }
   bool IsN64() const { return ThisABI == ABI::N64; }
   bool IsEABI() const { return ThisABI == ABI::EABI; }
   ABI GetEnumValue() const { return ThisABI; }

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp

 unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
   if (IsO32())
     return CC != CallingConv::Fast ? 16 : 0;
   if (IsN32() || IsN64() || IsEABI())
     return 0;
   llvm_unreachable("Unhandled ABI");
 }
 
-MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
+MipsABIInfo MipsABIInfo::computeTargetABI(const TargetTuple &TT, StringRef CPU,
                                           const MCTargetOptions &Options) {
   if (Options.getABIName().startswith("o32"))
     return MipsABIInfo::O32();
   else if (Options.getABIName().startswith("n32"))
     return MipsABIInfo::N32();
   else if (Options.getABIName().startswith("n64"))
     return MipsABIInfo::N64();
   else if (Options.getABIName().startswith("eabi"))
     return MipsABIInfo::EABI();
   else if (!Options.getABIName().empty())
     llvm_unreachable("Unknown ABI option for MIPS");
 
   // FIXME: This shares code with the selectMipsCPU routine that's
   // used and not shared in a couple of other places. This needs unifying
   // at some level.
   if (CPU.empty() || CPU == "generic") {
-    if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
+    if (TT.getArch() == TargetTuple::mips ||
+        TT.getArch() == TargetTuple::mipsel)
       CPU = "mips32";
     else
       CPU = "mips64";
   }
 
   return StringSwitch<MipsABIInfo>(CPU)
       .Case("mips1", MipsABIInfo::O32())
       .Case("mips2", MipsABIInfo::O32())

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

 //
 //===----------------------------------------------------------------------===//
 //
 
 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
 
 #include "MCTargetDesc/MipsFixupKinds.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCAsmBackend.h"
 
 namespace llvm {
 
 class MCAssembler;
 struct MCFixupKindInfo;
 class Target;
 class MCObjectWriter;
 
 class MipsAsmBackend : public MCAsmBackend {
-  Triple::OSType OSType;
+  TargetTuple::OSType OSType;
   bool IsLittle; // Big or little endian
   bool Is64Bit;  // 32 or 64 bit words
 
 public:
-  MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle,
+  MipsAsmBackend(const Target &T, TargetTuple::OSType OSType, bool IsLittle,
                  bool Is64Bit)
       : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
 
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                   uint64_t Value, bool IsPCRel) const override;
 

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
   // access to MCContext from here which allows us to report a fatal error
   // with *possibly* a source code location.
   (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
 }
 
 // MCAsmBackend
 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
                                              const MCRegisterInfo &MRI,
-                                             const Triple &TT, StringRef CPU) {
+                                             const TargetTuple &TT,
+                                             StringRef CPU) {
   return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
                             /*Is64Bit*/ false);
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
                                              const MCRegisterInfo &MRI,
-                                             const Triple &TT, StringRef CPU) {
+                                             const TargetTuple &TT,
+                                             StringRef CPU) {
   return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
                             /*Is64Bit*/ false);
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
                                              const MCRegisterInfo &MRI,
-                                             const Triple &TT, StringRef CPU) {
+                                             const TargetTuple &TT,
+                                             StringRef CPU) {
   return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
                                              const MCRegisterInfo &MRI,
-                                             const Triple &TT, StringRef CPU) {
+                                             const TargetTuple &TT,
+                                             StringRef CPU) {
   return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
                             /*Is64Bit*/ true);
 }

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H
 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class MipsMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit MipsMCAsmInfo(const Triple &TheTriple);
+  explicit MipsMCAsmInfo(const TargetTuple &TT);
 };
 
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp

 //===-- MipsMCAsmInfo.cpp - Mips Asm Properties ---------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the MipsMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MipsMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 
 using namespace llvm;
 
 void MipsMCAsmInfo::anchor() { }
 
-MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::mips) ||
-      (TheTriple.getArch() == Triple::mips64))
+MipsMCAsmInfo::MipsMCAsmInfo(const TargetTuple &TT) {
+  if ((TT.getArch() == TargetTuple::mips) ||
+      (TT.getArch() == TargetTuple::mips64))
     IsLittleEndian = false;
 
-  if ((TheTriple.getArch() == Triple::mips64el) ||
-      (TheTriple.getArch() == Triple::mips64)) {
+  if ((TT.getArch() == TargetTuple::mips64el) ||
+      (TT.getArch() == TargetTuple::mips64)) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
 
   AlignmentIsInBytes          = false;
   Data16bitsDirective         = "\t.2byte\t";
   Data32bitsDirective         = "\t.4byte\t";
   Data64bitsDirective         = "\t.8byte\t";
   PrivateGlobalPrefix         = "$";

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class StringRef;
 class Target;
-class Triple;
+class TargetTuple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheMipsTarget;
 extern Target TheMipselTarget;
 extern Target TheMips64Target;
 extern Target TheMips64elTarget;
 
 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
                                          const MCRegisterInfo &MRI,
                                          MCContext &Ctx);
 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
                                          const MCRegisterInfo &MRI,
                                          MCContext &Ctx);
 
 MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
                                        const MCRegisterInfo &MRI,
-                                       const Triple &TT, StringRef CPU);
+                                       const TargetTuple &TT, StringRef CPU);
 MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
                                        const MCRegisterInfo &MRI,
-                                       const Triple &TT, StringRef CPU);
+                                       const TargetTuple &TT, StringRef CPU);
 MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
                                        const MCRegisterInfo &MRI,
-                                       const Triple &TT, StringRef CPU);
+                                       const TargetTuple &TT, StringRef CPU);
 MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
                                        const MCRegisterInfo &MRI,
-                                       const Triple &TT, StringRef CPU);
+                                       const TargetTuple &TT, StringRef CPU);
 
 MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
                                           bool IsLittleEndian, bool Is64Bit);
 
 namespace MIPS_MC {
-StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
+StringRef selectMipsCPU(const TargetTuple &TT, StringRef CPU);
 }
 
 } // End llvm namespace
 
 // Defines symbolic names for Mips registers.  This defines a mapping from
 // register name to register number.
 #define GET_REGINFO_ENUM
 #include "MipsGenRegisterInfo.inc"

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

 //===----------------------------------------------------------------------===//
 
 #include "InstPrinter/MipsInstPrinter.h"
 #include "MipsELFStreamer.h"
 #include "MipsMCAsmInfo.h"
 #include "MipsMCNaCl.h"
 #include "MipsMCTargetDesc.h"
 #include "MipsTargetStreamer.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/CommandLine.h"

 #define GET_SUBTARGETINFO_MC_DESC
 #include "MipsGenSubtargetInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "MipsGenRegisterInfo.inc"
 
 /// Select the Mips CPU for the given triple and cpu name.
 /// FIXME: Merge with the copy in MipsSubtarget.cpp
-StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
+StringRef MIPS_MC::selectMipsCPU(const TargetTuple &TT, StringRef CPU) {
   if (CPU.empty() || CPU == "generic") {
-    if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
+    if (TT.getArch() == TargetTuple::mips ||
+        TT.getArch() == TargetTuple::mipsel)
       CPU = "mips32";
     else
       CPU = "mips64";
   }
   return CPU;
 }
 
 static MCInstrInfo *createMipsMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitMipsMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createMipsMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitMipsMCRegisterInfo(X, Mips::RA);
   return X;
 }
 
-static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
+static MCSubtargetInfo *createMipsMCSubtargetInfo(const TargetTuple &TT,
                                                   StringRef CPU, StringRef FS) {
   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
-                                      const Triple &TT) {
+                                      const TargetTuple &TT) {
   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
 
   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
-static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
+static MCCodeGenInfo *createMipsMCCodeGenInfo(const TargetTuple &TT,
+                                              Reloc::Model RM,
                                               CodeModel::Model CM,
                                               CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (CM == CodeModel::JITDefault)
     RM = Reloc::Static;
   else if (RM == Reloc::Default)
     RM = Reloc::PIC_;
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
+static MCInstPrinter *createMipsMCInstPrinter(const TargetTuple &T,
                                               unsigned SyntaxVariant,
                                               const MCAsmInfo &MAI,
                                               const MCInstrInfo &MII,
                                               const MCRegisterInfo &MRI) {
   return new MipsInstPrinter(MAI, MII, MRI);
 }
 
-static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
+static MCStreamer *createMCStreamer(const TargetTuple &T, MCContext &Context,
                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
                                     MCCodeEmitter *Emitter, bool RelaxAll) {
   MCStreamer *S;
   if (!T.isOSNaCl())
     S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
   else
     S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
   return S;

llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp

 
 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
 
   // Compute MIPS architecture attributes based on the default subtarget
   // that we'd have constructed. Module level directives aren't LTO
   // clean anyhow.
   // FIXME: For ifunc related functions we could iterate over and look
   // for a feature string that doesn't match the default one.
-  const Triple &TT = TM.getTargetTriple();
+  TargetTuple TT(TargetTuple(TM.getTargetTriple()));
   StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
   StringRef FS = TM.getTargetFeatureString();
   const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
-  const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
+  const MipsSubtarget STI(TM.getTargetTriple(), CPU, FS, MTM.isLittleEndian(),
+                          MTM);
 
   bool IsABICalls = STI.isABICalls();
   const MipsABIInfo &ABI = MTM.getABI();
   if (IsABICalls) {
     getTargetStreamer().emitDirectiveAbiCalls();
     Reloc::Model RM = TM.getRelocationModel();
     // FIXME: This condition should be a lot more complicated that it is here.
     //        Ideally it should test for properties of the ABI and not the ABI

llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp

static cl::opt<bool>
     GPOpt("mgpopt", cl::Hidden,
           cl::desc("Enable gp-relative addressing of mips small data items"));
 
 void MipsSubtarget::anchor() { }
 
 MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
                              const std::string &FS, bool little,
                              const MipsTargetMachine &TM)
-    : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
-      IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
-      NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
-      IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
-      HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
-      HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
-      InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
-      HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
-      HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
-      TargetTriple(TT), TSInfo(),
+    : MipsGenSubtargetInfo(TargetTuple(TT), CPU, FS),
+      MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false),
+      IsSingleFloat(false), IsFPXX(false), NoABICalls(false), IsFP64bit(false),
+      UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
+      HasCnMips(false), HasMips3_32(false), HasMips3_32r2(false),
+      HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
+      InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
+      InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
+      AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
+      UseTCCInDIV(false), HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
       FrameLowering(MipsFrameLowering::create(*this)),
       TLInfo(MipsTargetLowering::create(TM, *this)) {
 
   PreviousInMips16Mode = InMips16Mode;
 
   if (MipsArchVersion == MipsDefault)

 
 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
   return CodeGenOpt::Aggressive;
 }
 
 MipsSubtarget &
 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                                const TargetMachine &TM) {
-  std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
+  std::string CPUName =
+      MIPS_MC::selectMipsCPU(TargetTuple(TM.getTargetTriple()), CPU);
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUName);
 
   if (InMips16Mode && !IsSoftFloat)
     InMips16HardFloat = true;

llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp

extern "C" void LLVMInitializeMipsTarget() {
   RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
   RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
 }
 
 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
                                      const TargetOptions &Options,
                                      bool isLittle) {
   std::string Ret = "";
-  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
+  MipsABIInfo ABI =
+      MipsABIInfo::computeTargetABI(TargetTuple(TT), CPU, Options.MCOptions);
 
   // There are both little and big endian mips.
   if (isLittle)
     Ret += "e";
   else
     Ret += "E";
 
   Ret += "-m:m";

 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,
                                      Reloc::Model RM, CodeModel::Model CM,
                                      CodeGenOpt::Level OL, bool isLittle)
     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
                         CPU, FS, Options, RM, CM, OL),
       isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
-      ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
+      ABI(MipsABIInfo::computeTargetABI(TargetTuple(TT), CPU,
+                                        Options.MCOptions)),
       Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
       NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
                         isLittle, *this),
       Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
                       isLittle, *this) {
   Subtarget = &DefaultSubtarget;
   initAsmInfo();
 }

llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h

 
 #ifndef LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCASMINFO_H
 #define LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfo.h"
 
 namespace llvm {
 class Target;
-class Triple;
+class TargetTuple;
 
 class NVPTXMCAsmInfo : public MCAsmInfo {
   virtual void anchor();
 
 public:
-  explicit NVPTXMCAsmInfo(const Triple &TheTriple);
+  explicit NVPTXMCAsmInfo(const TargetTuple &TT);
 };
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp

 //===-- NVPTXMCAsmInfo.cpp - NVPTX asm properties -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the NVPTXMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "NVPTXMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 // -debug-compile - Command line option to inform opt and llc passes to
 // compile for debugging
 static cl::opt<bool> CompileForDebugging("debug-compile",
                                          cl::desc("Compile for debugging"),
                                          cl::Hidden, cl::init(false));
 
 void NVPTXMCAsmInfo::anchor() {}
 
-NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple) {
-  if (TheTriple.getArch() == Triple::nvptx64) {
+NVPTXMCAsmInfo::NVPTXMCAsmInfo(const TargetTuple &TT) {
+  if (TT.getArch() == TargetTuple::nvptx64) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
 
   CommentString = "//";
 
   HasSingleParameterDotFile = false;
 
   InlineAsmStart = " inline asm";

llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp

 #include "NVPTXGenRegisterInfo.inc"
 
 static MCInstrInfo *createNVPTXMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitNVPTXMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createNVPTXMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createNVPTXMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   // PTX does not have a return address register.
   InitNVPTXMCRegisterInfo(X, 0);
   return X;
 }
 
 static MCSubtargetInfo *
-createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+createNVPTXMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) {
   return createNVPTXMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const TargetTuple &TT,
                                                Reloc::Model RM,
                                                CodeModel::Model CM,
                                                CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   // The default relocation model is used regardless of what the client has
   // specified, as it is the only relocation model currently supported.
   X->initMCCodeGenInfo(Reloc::Default, CM, OL);
   return X;
 }
 
-static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,
+static MCInstPrinter *createNVPTXMCInstPrinter(const TargetTuple &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,
                                                const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new NVPTXInstPrinter(MAI, MII, MRI);
   return nullptr;
 }

llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp

NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
   }
 
   return *this;
 }
 
 NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS,
                                const NVPTXTargetMachine &TM)
-    : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM),
-      InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)),
+    : NVPTXGenSubtargetInfo(TargetTuple(TT), CPU, FS), PTXVersion(0),
+      SmVersion(20), TM(TM), InstrInfo(),
+      TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), TSInfo(),
       FrameLowering() {}
 
 bool NVPTXSubtarget::hasImageHandles() const {
   // Enable handles for Kepler+, where CUDA supports indirect surfaces and
   // textures
   if (TM.getDrvInterface() == NVPTX::CUDA)
     return (SmVersion >= 30);
 
   // Disabled, otherwise
   return false;
 }

llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

#include "PPCGenAsmMatcher.inc"
   /// }
 
 
 public:
   PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &, const MCInstrInfo &MII,
                const MCTargetOptions &Options)
       : MCTargetAsmParser(Options), STI(STI), MII(MII) {
     // Check for 64-bit vs. 32-bit pointer mode.
-    Triple TheTriple(STI.getTargetTriple());
-    IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
-               TheTriple.getArch() == Triple::ppc64le);
-    IsDarwin = TheTriple.isMacOSX();
+    const TargetTuple &TT = STI.getTargetTuple();
+    IsPPC64 = (TT.getArch() == TargetTuple::ppc64 ||
+               TT.getArch() == TargetTuple::ppc64le);
+    IsDarwin = TT.isMacOSX();
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
   }
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
 
   bool ParseDirective(AsmToken DirectiveID) override;

llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
       return createPPCELFObjectWriter(OS, is64, isLittleEndian(), OSABI);
     }
   };
 
 } // end anonymous namespace
 
 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const Triple &TT, StringRef CPU) {
+                                        const TargetTuple &TT, StringRef CPU) {
   if (TT.isOSDarwin())
     return new DarwinPPCAsmBackend(T);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
-  bool IsLittleEndian = TT.getArch() == Triple::ppc64le;
+  bool IsLittleEndian = TT.getArch() == TargetTuple::ppc64le;
   return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI);
 }

llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h

 
 #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCASMINFO_H
 #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple &);
+  explicit PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &);
 };
 
 class PPCELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit PPCELFMCAsmInfo(bool is64Bit, const Triple &);
+  explicit PPCELFMCAsmInfo(bool is64Bit, const TargetTuple &);
 };
 
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp

 //===-- PPCMCAsmInfo.cpp - PPC asm properties -----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the MCAsmInfoDarwin properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 
 using namespace llvm;
 
 void PPCMCAsmInfoDarwin::anchor() { }
 
-PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) {
+PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &TT) {
   if (is64Bit) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
   IsLittleEndian = false;
 
   CommentString = ";";
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   if (!is64Bit)
     Data64bitsDirective = nullptr; // We can't emit a 64-bit unit in PPC32 mode.
 
   AssemblerDialect = 1;           // New-Style mnemonics.
   SupportsDebugInformation= true; // Debug information.
 
   // The installed assembler for OSX < 10.6 lacks some directives.
   // FIXME: this should really be a check on the assembler characteristics
   // rather than OS version
-  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
+  if (TT.isMacOSX() && TT.isMacOSXVersionLT(10, 6))
     HasWeakDefCanBeHiddenDirective = false;
 
   UseIntegratedAssembler = true;
 }
 
 void PPCELFMCAsmInfo::anchor() { }
 
-PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const Triple& T) {
+PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const TargetTuple &TT) {
   // FIXME: This is not always needed. For example, it is not needed in the
   // v2 abi.
   NeedsLocalForSize = true;
 
   if (is64Bit) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
-  IsLittleEndian = T.getArch() == Triple::ppc64le;
+  IsLittleEndian = TT.getArch() == TargetTuple::ppc64le;
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;
 
   CommentString = "#";
 
   // Uses '.section' before '.bss' directive
   UsesELFSectionDirectiveForBSS = true;  

llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
   
   // Add a fixup for the TLS register, which simply provides a relocation
   // hint to the linker that this statement is part of a relocation sequence.
   // Return the thread-pointer register's encoding.
   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
-  const Triple &TT = STI.getTargetTriple();
-  bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
+  const TargetTuple &TT = STI.getTargetTuple();
+  bool isPPC64 = TT.getArch() == TargetTuple::ppc64 ||
+                 TT.getArch() == TargetTuple::ppc64le;
   return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
 }
 
 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
   // For special TLS calls, we need two fixups; one for the branch target
   // (__tls_get_addr), which we create via getDirectBrEncoding as usual,

llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
-class Triple;
+class TargetTuple;
 class StringRef;
 class raw_pwrite_stream;
 class raw_ostream;
 
 extern Target ThePPC32Target;
 extern Target ThePPC64Target;
 extern Target ThePPC64LETarget;
 
 MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
                                       const MCRegisterInfo &MRI,
                                       MCContext &Ctx);
 
 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const Triple &TT, StringRef CPU);
+                                  const TargetTuple &TT, StringRef CPU);
 
 /// Construct an PPC ELF object writer.
 MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
                                          bool IsLittleEndian, uint8_t OSABI);
 /// Construct a PPC Mach-O object writer.
 MCObjectWriter *createPPCMachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
                                           uint32_t CPUType,
                                           uint32_t CPUSubtype);

llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

 PPCTargetStreamer::PPCTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
 
 static MCInstrInfo *createPPCMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitPPCMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
-  bool isPPC64 =
-      (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
+static MCRegisterInfo *createPPCMCRegisterInfo(const TargetTuple &TT) {
+  bool isPPC64 = (TT.getArch() == TargetTuple::ppc64 ||
+                  TT.getArch() == TargetTuple::ppc64le);
   unsigned Flavour = isPPC64 ? 0 : 1;
   unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
 
   MCRegisterInfo *X = new MCRegisterInfo();
   InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
   return X;
 }
 
-static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
+static MCSubtargetInfo *createPPCMCSubtargetInfo(const TargetTuple &TT,
                                                  StringRef CPU, StringRef FS) {
   return createPPCMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
-  bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
-                  TheTriple.getArch() == Triple::ppc64le);
+                                     const TargetTuple &TT) {
+  bool isPPC64 = (TT.getArch() == TargetTuple::ppc64 ||
+                  TT.getArch() == TargetTuple::ppc64le);
 
   MCAsmInfo *MAI;
-  if (TheTriple.isOSDarwin())
-    MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
+  if (TT.isOSDarwin())
+    MAI = new PPCMCAsmInfoDarwin(isPPC64, TT);
   else
-    MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
+    MAI = new PPCELFMCAsmInfo(isPPC64, TT);
 
   // Initial state of the frame pointer is R1.
   unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
   MCCFIInstruction Inst =
       MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
-static MCCodeGenInfo *createPPCMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
+static MCCodeGenInfo *createPPCMCCodeGenInfo(const TargetTuple &TT,
+                                             Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   if (RM == Reloc::Default) {
     if (TT.isOSDarwin())
       RM = Reloc::DynamicNoPIC;
     else
       RM = Reloc::Static;
   }
   if (CM == CodeModel::Default) {
-    if (!TT.isOSDarwin() &&
-        (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
+    if (!TT.isOSDarwin() && (TT.getArch() == TargetTuple::ppc64 ||
+                             TT.getArch() == TargetTuple::ppc64le))
       CM = CodeModel::Medium;
   }
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
 namespace {
 class PPCTargetAsmStreamer : public PPCTargetStreamer {
static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
                                                  formatted_raw_ostream &OS,
                                                  MCInstPrinter *InstPrint,
                                                  bool isVerboseAsm) {
   return new PPCTargetAsmStreamer(S, OS);
 }
 
 static MCTargetStreamer *
 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
-  const Triple &TT = STI.getTargetTriple();
+  const TargetTuple &TT = STI.getTargetTuple();
   if (TT.isOSBinFormatELF())
     return new PPCTargetELFStreamer(S);
   return new PPCTargetMachOStreamer(S);
 }
 
-static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
+static MCInstPrinter *createPPCMCInstPrinter(const TargetTuple &TT,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
                                              const MCRegisterInfo &MRI) {
-  return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin());
+  return new PPCInstPrinter(MAI, MII, MRI, TT.isOSDarwin());
 }
 
 extern "C" void LLVMInitializePowerPCTargetMC() {
   for (Target *T : {&ThePPC32Target, &ThePPC64Target, &ThePPC64LETarget}) {
     // Register the MC asm info.
     RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
 
     // Register the MC codegen info.

llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp

PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                             StringRef FS) {
   initializeEnvironment();
   initSubtargetFeatures(CPU, FS);
   return *this;
 }
 
 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const PPCTargetMachine &TM)
-    : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
+    : PPCGenSubtargetInfo(TargetTuple(TT), CPU, FS), TargetTriple(TT),
       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
               TargetTriple.getArch() == Triple::ppc64le),
       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
       InstrInfo(*this), TLInfo(TM, *this) {}
 
 void PPCSubtarget::initializeEnvironment() {
   StackAlignment = 16;
   DarwinDirective = PPC::DIR_NONE;

llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

#include "SparcGenAsmMatcher.inc"
   // returns true if Tok is matched to a register and returns register in RegNo.
   bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
                          unsigned &RegKind);
 
   bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
   bool parseDirectiveWord(unsigned Size, SMLoc L);
 
   bool is64Bit() const {
-    return STI.getTargetTriple().getArch() == Triple::sparcv9;
+    return STI.getTargetTuple().getArch() == TargetTuple::sparcv9;
   }
 
   void expandSET(MCInst &Inst, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
 public:
   SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
                 const MCInstrInfo &MII,

llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
       for (uint64_t i = 0; i != NumNops; ++i)
         OW->write32(0x01000000);
 
       return true;
     }
   };
 
   class ELFSparcAsmBackend : public SparcAsmBackend {
-    Triple::OSType OSType;
+    TargetTuple::OSType OSType;
+
   public:
-    ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
-      SparcAsmBackend(T), OSType(OSType) { }
+    ELFSparcAsmBackend(const Target &T, TargetTuple::OSType OSType)
+        : SparcAsmBackend(T), OSType(OSType) {}
 
     void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                     uint64_t Value, bool IsPCRel) const override {
 
       Value = adjustFixupValue(Fixup.getKind(), Value);
       if (!Value) return;           // Doesn't change encoding.
 
       unsigned Offset = Fixup.getOffset();
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
       return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI);
     }
   };
 
 } // end anonymous namespace
 
 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const Triple &TT, StringRef CPU) {
+                                          const TargetTuple &TT,
+                                          StringRef CPU) {
   return new ELFSparcAsmBackend(T, TT.getOS());
 }

llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCASMINFO_H
 #define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class SparcELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit SparcELFMCAsmInfo(const Triple &TheTriple);
+  explicit SparcELFMCAsmInfo(const TargetTuple &TT);
   const MCExpr*
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
   const MCExpr* getExprForFDESymbol(const MCSymbol *Sym,
                                     unsigned Encoding,
                                     MCStreamer &Streamer) const override;
 
 };
 
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp

 //===-- SparcMCAsmInfo.cpp - Sparc asm properties -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the SparcMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SparcMCAsmInfo.h"
 #include "SparcMCExpr.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCStreamer.h"
 
 using namespace llvm;
 
 void SparcELFMCAsmInfo::anchor() {}
 
-SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) {
-  bool isV9 = (TheTriple.getArch() == Triple::sparcv9);
-  IsLittleEndian = (TheTriple.getArch() == Triple::sparcel);
+SparcELFMCAsmInfo::SparcELFMCAsmInfo(const TargetTuple &TT) {
+  bool isV9 = (TT.getArch() == TargetTuple::sparcv9);
+  IsLittleEndian = (TT.getArch() == TargetTuple::sparcel);
 
   if (isV9) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
 
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";
   // .xword is only supported by V9.

llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h

 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
-class Triple;
+class TargetTuple;
 class StringRef;
 class raw_pwrite_stream;
 class raw_ostream;
 
 extern Target TheSparcTarget;
 extern Target TheSparcV9Target;
 extern Target TheSparcelTarget;
 
 MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
 MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+                                    const TargetTuple &TT, StringRef CPU);
 MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
                                            bool IsLIttleEndian, uint8_t OSABI);
 } // End llvm namespace
 
 // Defines symbolic names for Sparc registers.  This defines a mapping from
 // register name to register number.
 //
 #define GET_REGINFO_ENUM

llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp

 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "SparcGenSubtargetInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "SparcGenRegisterInfo.inc"
 
 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI,
-                                       const Triple &TT) {
+                                       const TargetTuple &TT) {
   MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
   unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
   MAI->addInitialFrameState(Inst);
   return MAI;
 }
 
 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
+                                         const TargetTuple &TT) {
   MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
   unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
   MAI->addInitialFrameState(Inst);
   return MAI;
 }
 
 static MCInstrInfo *createSparcMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitSparcMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createSparcMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitSparcMCRegisterInfo(X, SP::O7);
   return X;
 }
 
 static MCSubtargetInfo *
-createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+createSparcMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) {
   if (CPU.empty())
-    CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
+    CPU = (TT.getArch() == TargetTuple::sparcv9) ? "v9" : "v8";
   return createSparcMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 // Code models. Some only make sense for 64-bit code.
 //
 // SunCC  Reloc   CodeModel  Constraints
 // abs32  Static  Small      text+data+bss linked below 2^32 bytes
 // abs44  Static  Medium     text+data+bss linked below 2^44 bytes
 // abs64  Static  Large      text smaller than 2^31 bytes
 // pic13  PIC_    Small      GOT < 2^13 bytes
 // pic32  PIC_    Medium     GOT < 2^32 bytes
 //
 // All code models require that the text segment is smaller than 2GB.
 
-static MCCodeGenInfo *createSparcMCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createSparcMCCodeGenInfo(const TargetTuple &TT,
                                                Reloc::Model RM,
                                                CodeModel::Model CM,
                                                CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   // The default 32-bit code model is abs32/pic32 and the default 32-bit
   // code model for JIT is abs32.
   switch (CM) {
   default: break;
   case CodeModel::Default:
   case CodeModel::JITDefault: CM = CodeModel::Small; break;
   }
 
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const TargetTuple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   // The default 64-bit code model is abs44/pic32 and the default 64-bit
   // code model for JIT is abs64.
   switch (CM) {

 
 static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
                                                  formatted_raw_ostream &OS,
                                                  MCInstPrinter *InstPrint,
                                                  bool isVerboseAsm) {
   return new SparcTargetAsmStreamer(S, OS);
 }
 
-static MCInstPrinter *createSparcMCInstPrinter(const Triple &T,
+static MCInstPrinter *createSparcMCInstPrinter(const TargetTuple &TT,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,
                                                const MCRegisterInfo &MRI) {
   return new SparcInstPrinter(MAI, MII, MRI);
 }
 
 extern "C" void LLVMInitializeSparcTargetMC() {

llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp

if (!IsV9)
     UsePopc = false;
 
   return *this;
 }
 
 SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, TargetMachine &TM,
                                bool is64Bit)
-    : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit),
+    : SparcGenSubtargetInfo(TargetTuple(TT), CPU, FS), Is64Bit(is64Bit),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       FrameLowering(*this) {}
 
 int SparcSubtarget::getAdjustedFrameSize(int frameSize) const {
 
   if (is64Bit()) {
     // All 64-bit stack frames must be 16-byte aligned, and must reserve space
     // for spilling the 16 window registers at %sp+BIAS..%sp+BIAS+128.

llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

bool SystemZMCAsmBackend::writeNopData(uint64_t Count,
                                        MCObjectWriter *OW) const {
   for (uint64_t I = 0; I != Count; ++I)
     OW->write8(7);
   return true;
 }
 
 MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
                                               const MCRegisterInfo &MRI,
-                                              const Triple &TT, StringRef CPU) {
+                                              const TargetTuple &TT,
+                                              StringRef CPU) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   return new SystemZMCAsmBackend(OSABI);
 }

llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h

 //====-- SystemZMCAsmInfo.h - SystemZ asm properties -----------*- C++ -*--===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCASMINFO_H
 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 #include "llvm/Support/Compiler.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class SystemZMCAsmInfo : public MCAsmInfoELF {
 public:
-  explicit SystemZMCAsmInfo(const Triple &TT);
+  explicit SystemZMCAsmInfo(const TargetTuple &TT);
 };
 
 } // end namespace llvm
 
 #endif

llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp

 //===-- SystemZMCAsmInfo.cpp - SystemZ asm properties ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SystemZMCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSectionELF.h"
 
 using namespace llvm;
 
-SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) {
+SystemZMCAsmInfo::SystemZMCAsmInfo(const TargetTuple &TT) {
   PointerSize = 8;
   CalleeSaveStackSlotSize = 8;
   IsLittleEndian = false;
 
   CommentString = "#";
   ZeroDirective = "\t.space\t";
   Data64bitsDirective = "\t.quad\t";
   UsesELFSectionDirectiveForBSS = true;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   UseIntegratedAssembler = true;
 }

llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h

 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class StringRef;
 class Target;
-class Triple;
+class TargetTuple;
 class raw_pwrite_stream;
 class raw_ostream;
 
 extern Target TheSystemZTarget;
 
 namespace SystemZMC {
 // How many bytes are in the ABI-defined, caller-allocated part of
 // a stack frame.

 } // end namespace SystemZMC
 
 MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
                                           const MCRegisterInfo &MRI,
                                           MCContext &Ctx);
 
 MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const Triple &TT, StringRef CPU);
+                                        const TargetTuple &TT, StringRef CPU);
 
 MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
 } // end namespace llvm
 
 // Defines symbolic names for SystemZ registers.
 // This defines a mapping from register name to register number.
 #define GET_REGINFO_ENUM
 #include "SystemZGenRegisterInfo.inc"

llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp

for (unsigned I = 0; I < 32; ++I) {
       Map[VR128Regs[I]] = I;
     }
   }
   assert(Reg < SystemZ::NUM_TARGET_REGS);
   return Map[Reg];
 }
 
 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
-                                         const Triple &TT) {
+                                         const TargetTuple &TT) {
   MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
   MCCFIInstruction Inst =
       MCCFIInstruction::createDefCfa(nullptr,
                                      MRI.getDwarfRegNum(SystemZ::R15D, true),
                                      SystemZMC::CFAOffsetFromInitialSP);
   MAI->addInitialFrameState(Inst);
   return MAI;
 }
 
 static MCInstrInfo *createSystemZMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitSystemZMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createSystemZMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitSystemZMCRegisterInfo(X, SystemZ::R14D);
   return X;
 }
 
-static MCSubtargetInfo *
-createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+static MCSubtargetInfo *createSystemZMCSubtargetInfo(const TargetTuple &TT,
+                                                     StringRef CPU,
+                                                     StringRef FS) {
   return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createSystemZMCCodeGenInfo(const TargetTuple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   // Static code is suitable for use in a dynamic executable; there is no
   // separate DynamicNoPIC model.
   if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
static MCCodeGenInfo *createSystemZMCCodeGenInfo(const TargetTuple &TT,
   if (CM == CodeModel::Default)
     CM = CodeModel::Small;
   else if (CM == CodeModel::JITDefault)
     CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
+static MCInstPrinter *createSystemZMCInstPrinter(const TargetTuple &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
                                                  const MCRegisterInfo &MRI) {
   return new SystemZInstPrinter(MAI, MII, MRI);
 }
 
 extern "C" void LLVMInitializeSystemZTargetMC() {

llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp

SystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
   return *this;
 }
 
 SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
                                    const TargetMachine &TM)
-    : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
+    : SystemZGenSubtargetInfo(TargetTuple(TT), CPU, FS), HasDistinctOps(false),
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasPopulationCount(false), HasFastSerialization(false),
       HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
       HasTransactionalExecution(false), HasProcessorAssist(false),
       HasVector(false), TargetTriple(TT),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       TSInfo(), FrameLowering() {}
 

llvm/trunk/lib/Target/TargetSubtargetInfo.cpp

 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 using namespace llvm;
 
 //---------------------------------------------------------------------------
 // TargetSubtargetInfo Class
 //
 TargetSubtargetInfo::TargetSubtargetInfo(
-    const Triple &TT, StringRef CPU, StringRef FS,
+    const TargetTuple &TT, StringRef CPU, StringRef FS,
     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
     const InstrStage *IS, const unsigned *OC, const unsigned *FP)
     : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
 }
 
 TargetSubtargetInfo::~TargetSubtargetInfo() {}

llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

unsigned X86AsmInstrumentation::GetFrameRegGeneric(const MCContext &Ctx,
   }
 
   return MRI->getLLVMRegNum(Frame.CurrentCfaRegister, true /* IsEH */);
 }
 
 X86AsmInstrumentation *
 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
                             const MCContext &Ctx, const MCSubtargetInfo &STI) {
-  Triple T(STI.getTargetTriple());
-  const bool hasCompilerRTSupport = T.isOSLinux();
+  const TargetTuple &TT = STI.getTargetTuple();
+  const bool hasCompilerRTSupport = TT.isOSLinux();
   if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
       MCOptions.SanitizeAddress) {
     if (STI.getFeatureBits()[X86::Mode32Bit] != 0)
       return new X86AddressSanitizer32(STI);
     if (STI.getFeatureBits()[X86::Mode64Bit] != 0)
       return new X86AddressSanitizer64(STI);
   }
   return new X86AsmInstrumentation(STI);
 }
 
 } // end llvm namespace

llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

uint32_t generateCompactUnwindEncoding(
     return generateCompactUnwindEncodingImpl(Instrs);
   }
 };
 
 } // end anonymous namespace
 
 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
-                                           const Triple &TheTriple,
+                                           const TargetTuple &TT,
                                            StringRef CPU) {
-  if (TheTriple.isOSBinFormatMachO())
+  if (TT.isOSBinFormatMachO())
     return new DarwinX86_32AsmBackend(T, MRI, CPU);
 
-  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
+  if (TT.isOSWindows() && !TT.isOSBinFormatELF())
     return new WindowsX86AsmBackend(T, false, CPU);
 
-  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
+  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   return new ELFX86_32AsmBackend(T, OSABI, CPU);
 }
 
 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
-                                           const Triple &TheTriple,
+                                           const TargetTuple &TT,
                                            StringRef CPU) {
-  if (TheTriple.isOSBinFormatMachO()) {
+  if (TT.isOSBinFormatMachO()) {
     MachO::CPUSubTypeX86 CS =
-        StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
+        StringSwitch<MachO::CPUSubTypeX86>(TT.getArchName())
             .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
             .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
     return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
   }
 
-  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
+  if (TT.isOSWindows() && !TT.isOSBinFormatELF())
     return new WindowsX86AsmBackend(T, true, CPU);
 
-  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
+  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
 
-  if (TheTriple.getEnvironment() == Triple::GNUX32)
+  if (TT.getEnvironment() == TargetTuple::GNUX32)
     return new ELFX86_X32AsmBackend(T, OSABI, CPU);
   return new ELFX86_64AsmBackend(T, OSABI, CPU);
 }

llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h

 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCASMINFO_H
 
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCAsmInfoCOFF.h"
 #include "llvm/MC/MCAsmInfoDarwin.h"
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class X86MCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit X86MCAsmInfoDarwin(const Triple &Triple);
+  explicit X86MCAsmInfoDarwin(const TargetTuple &TT);
 };
 
 struct X86_64MCAsmInfoDarwin : public X86MCAsmInfoDarwin {
-  explicit X86_64MCAsmInfoDarwin(const Triple &Triple);
+  explicit X86_64MCAsmInfoDarwin(const TargetTuple &TT);
   const MCExpr *
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
 };
 
 class X86ELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit X86ELFMCAsmInfo(const Triple &Triple);
+  explicit X86ELFMCAsmInfo(const TargetTuple &TT);
 };
 
 class X86MCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
   void anchor() override;
 
 public:
-  explicit X86MCAsmInfoMicrosoft(const Triple &Triple);
+  explicit X86MCAsmInfoMicrosoft(const TargetTuple &TT);
 };
 
 class X86MCAsmInfoGNUCOFF : public MCAsmInfoGNUCOFF {
   void anchor() override;
 
 public:
-  explicit X86MCAsmInfoGNUCOFF(const Triple &Triple);
+  explicit X86MCAsmInfoGNUCOFF(const TargetTuple &TT);
 };
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp

 //===-- X86MCAsmInfo.cpp - X86 asm properties -----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the X86MCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ELF.h"
 using namespace llvm;
 

 
 static cl::opt<bool>
 MarkedJTDataRegions("mark-data-regions", cl::init(false),
   cl::desc("Mark code section jump table data regions."),
   cl::Hidden);
 
 void X86MCAsmInfoDarwin::anchor() { }
 
-X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) {
-  bool is64Bit = T.getArch() == Triple::x86_64;
+X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const TargetTuple &TT) {
+  bool is64Bit = TT.getArch() == TargetTuple::x86_64;
   if (is64Bit)
     PointerSize = CalleeSaveStackSlotSize = 8;
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   if (!is64Bit)
X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const TargetTuple &TT) {
   UseDataRegionDirectives = MarkedJTDataRegions;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   // old assembler lacks some directives
   // FIXME: this should really be a check on the assembler characteristics
   // rather than OS version
-  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
+  if (TT.isMacOSX() && TT.isMacOSXVersionLT(10, 6))
     HasWeakDefCanBeHiddenDirective = false;
 
   // Assume ld64 is new enough that the abs-ified FDE relocs may be used
   // (actually, must, since otherwise the non-extern relocations we produce
   // overwhelm ld64's tiny little mind and it fails).
   DwarfFDESymbolsUseAbsDiff = true;
 
   UseIntegratedAssembler = true;
 }
 
-X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple)
-  : X86MCAsmInfoDarwin(Triple) {
-}
+X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const TargetTuple &TT)
+    : X86MCAsmInfoDarwin(TT) {}
 
 void X86ELFMCAsmInfo::anchor() { }
 
-X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
-  bool is64Bit = T.getArch() == Triple::x86_64;
-  bool isX32 = T.getEnvironment() == Triple::GNUX32;
+X86ELFMCAsmInfo::X86ELFMCAsmInfo(const TargetTuple &TT) {
+  bool is64Bit = TT.getArch() == TargetTuple::x86_64;
+  bool isX32 = TT.getEnvironment() == TargetTuple::GNUX32;
 
   // For ELF, x86-64 pointer size depends on the ABI.
   // For x86-64 without the x32 ABI, pointer size is 8. For x86 and for x86-64
   // with the x32 ABI, pointer size remains the default 4.
   PointerSize = (is64Bit && !isX32) ? 8 : 4;
 
   // OTOH, stack slot size is always 8 for x86-64, even with the x32 ABI.
   CalleeSaveStackSlotSize = is64Bit ? 8 : 4;
X86_64MCAsmInfoDarwin::getExprForPersonalitySymbol(const MCSymbol *Sym,
   const MCExpr *Res =
     MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_GOTPCREL, Context);
   const MCExpr *Four = MCConstantExpr::create(4, Context);
   return MCBinaryExpr::createAdd(Res, Four, Context);
 }
 
 void X86MCAsmInfoMicrosoft::anchor() { }
 
-X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) {
-  if (Triple.getArch() == Triple::x86_64) {
+X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const TargetTuple &TT) {
+  if (TT.getArch() == TargetTuple::x86_64) {
     PrivateGlobalPrefix = ".L";
     PrivateLabelPrefix = ".L";
     PointerSize = 8;
     WinEHEncodingType = WinEH::EncodingType::Itanium;
   } else {
     // 32-bit X86 doesn't use CFI, so this isn't a real encoding type. It's just
     // a place holder that the Windows EHStreamer looks for to suppress CFI
     // output. In particular, usesWindowsCFI() returns false.
     WinEHEncodingType = WinEH::EncodingType::X86;
   }
 
   ExceptionsType = ExceptionHandling::WinEH;
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   AllowAtInName = true;
 
   UseIntegratedAssembler = true;
 }
 
 void X86MCAsmInfoGNUCOFF::anchor() { }
 
-X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) {
-  assert(Triple.isOSWindows() && "Windows is the only supported COFF target");
-  if (Triple.getArch() == Triple::x86_64) {
+X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const TargetTuple &TT) {
+  assert(TT.isOSWindows() && "Windows is the only supported COFF target");
+  if (TT.getArch() == TargetTuple::x86_64) {
     PrivateGlobalPrefix = ".L";
     PrivateLabelPrefix = ".L";
     PointerSize = 8;
     WinEHEncodingType = WinEH::EncodingType::Itanium;
     ExceptionsType = ExceptionHandling::WinEH;
   } else {
     ExceptionsType = ExceptionHandling::DwarfCFI;
   }
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   UseIntegratedAssembler = true;
 }

llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h

 class MCContext;
 class MCInstrInfo;
 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class MCRelocationInfo;
 class MCStreamer;
 class Target;
-class Triple;
+class TargetTuple;
 class StringRef;
 class raw_ostream;
 class raw_pwrite_stream;
 
 extern Target TheX86_32Target, TheX86_64Target;
 
 /// Flavour of dwarf regnumbers
 ///
 namespace DWARFFlavour {
   enum {
     X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
   };
 }
 
 ///  Native X86 register numbers
 ///
 namespace N86 {
   enum {
     EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
   };
 }
 
 namespace X86_MC {
-std::string ParseX86Triple(const Triple &TT);
+std::string ParseX86TargetTuple(const TargetTuple &TT);
 
-unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
+unsigned getDwarfRegFlavour(const TargetTuple &TT, bool isEH);
 
 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
 
 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
-MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
+MCSubtargetInfo *createX86MCSubtargetInfo(const TargetTuple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
                                       const MCRegisterInfo &MRI,
                                       MCContext &Ctx);
 
 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     const Triple &TT, StringRef CPU);
+                                     const TargetTuple &TT, StringRef CPU);
 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     const Triple &TT, StringRef CPU);
+                                     const TargetTuple &TT, StringRef CPU);
 
 /// Construct an X86 Windows COFF machine code streamer which will generate
 /// PE/COFF format object files.
 ///
 /// Takes ownership of \p AB and \p CE.
 MCStreamer *createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB,
                                      raw_pwrite_stream &OS, MCCodeEmitter *CE,
                                      bool RelaxAll);

llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

 // This file provides X86 specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86MCTargetDesc.h"
 #include "InstPrinter/X86ATTInstPrinter.h"
 #include "InstPrinter/X86IntelInstPrinter.h"
 #include "X86MCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MachineLocation.h"
 #include "llvm/Support/ErrorHandling.h"

 #include "X86GenRegisterInfo.inc"
 
 #define GET_INSTRINFO_MC_DESC
 #include "X86GenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "X86GenSubtargetInfo.inc"
 
-std::string X86_MC::ParseX86Triple(const Triple &TT) {
+std::string X86_MC::ParseX86TargetTuple(const TargetTuple &TT) {
   std::string FS;
-  if (TT.getArch() == Triple::x86_64)
+  if (TT.getArch() == TargetTuple::x86_64)
     FS = "+64bit-mode,-32bit-mode,-16bit-mode";
-  else if (TT.getEnvironment() != Triple::CODE16)
+  else if (TT.getEnvironment() != TargetTuple::CODE16)
     FS = "-64bit-mode,+32bit-mode,-16bit-mode";
   else
     FS = "-64bit-mode,-32bit-mode,+16bit-mode";
 
   return FS;
 }
 
-unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
-  if (TT.getArch() == Triple::x86_64)
+unsigned X86_MC::getDwarfRegFlavour(const TargetTuple &TT, bool isEH) {
+  if (TT.getArch() == TargetTuple::x86_64)
     return DWARFFlavour::X86_64;
 
   if (TT.isOSDarwin())
     return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
   if (TT.isOSCygMing())
     // Unsupported by now, just quick fallback
     return DWARFFlavour::X86_32_Generic;
   return DWARFFlavour::X86_32_Generic;
 }
 
 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
   // FIXME: TableGen these.
   for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
     unsigned SEH = MRI->getEncodingValue(Reg);
     MRI->mapLLVMRegToSEHReg(Reg, SEH);
   }
 }
 
-MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
+MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const TargetTuple &TT,
                                                   StringRef CPU, StringRef FS) {
-  std::string ArchFS = X86_MC::ParseX86Triple(TT);
+  std::string ArchFS = X86_MC::ParseX86TargetTuple(TT);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
     else
       ArchFS = FS;
   }
 
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = "generic";
 
   return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
 }
 
 static MCInstrInfo *createX86MCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitX86MCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
-  unsigned RA = (TT.getArch() == Triple::x86_64)
+static MCRegisterInfo *createX86MCRegisterInfo(const TargetTuple &TT) {
+  unsigned RA = (TT.getArch() == TargetTuple::x86_64)
                     ? X86::RIP  // Should have dwarf #16.
                     : X86::EIP; // Should have dwarf #8.
 
   MCRegisterInfo *X = new MCRegisterInfo();
   InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
                         X86_MC::getDwarfRegFlavour(TT, true), RA);
   X86_MC::InitLLVM2SEHRegisterMapping(X);
   return X;
 }
 
 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
-  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
+                                     const TargetTuple &TT) {
+  bool is64Bit = TT.getArch() == TargetTuple::x86_64;
 
   MCAsmInfo *MAI;
-  if (TheTriple.isOSBinFormatMachO()) {
+  if (TT.isOSBinFormatMachO()) {
     if (is64Bit)
-      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
+      MAI = new X86_64MCAsmInfoDarwin(TT);
     else
-      MAI = new X86MCAsmInfoDarwin(TheTriple);
-  } else if (TheTriple.isOSBinFormatELF()) {
+      MAI = new X86MCAsmInfoDarwin(TT);
+  } else if (TT.isOSBinFormatELF()) {
     // Force the use of an ELF container.
-    MAI = new X86ELFMCAsmInfo(TheTriple);
-  } else if (TheTriple.isWindowsMSVCEnvironment() ||
-             TheTriple.isWindowsCoreCLREnvironment()) {
-    MAI = new X86MCAsmInfoMicrosoft(TheTriple);
-  } else if (TheTriple.isOSCygMing() ||
-             TheTriple.isWindowsItaniumEnvironment()) {
-    MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
+    MAI = new X86ELFMCAsmInfo(TT);
+  } else if (TT.isWindowsMSVCEnvironment() ||
+             TT.isWindowsCoreCLREnvironment()) {
+    MAI = new X86MCAsmInfoMicrosoft(TT);
+  } else if (TT.isOSCygMing() || TT.isWindowsItaniumEnvironment()) {
+    MAI = new X86MCAsmInfoGNUCOFF(TT);
   } else {
     // The default is ELF.
-    MAI = new X86ELFMCAsmInfo(TheTriple);
+    MAI = new X86ELFMCAsmInfo(TT);
   }
 
   // Initialize initial frame state.
   // Calculate amount of bytes used for return address storing
   int stackGrowth = is64Bit ? -8 : -4;
 
   // Initial state of the frame pointer is esp+stackGrowth.
   unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
       nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
   MAI->addInitialFrameState(Inst);
 
   // Add return address to move list
   unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
   MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
       nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
   MAI->addInitialFrameState(Inst2);
 
   return MAI;
 }
 
-static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM,
+static MCCodeGenInfo *createX86MCCodeGenInfo(const TargetTuple &TT,
+                                             Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
-  bool is64Bit = TT.getArch() == Triple::x86_64;
+  bool is64Bit = TT.getArch() == TargetTuple::x86_64;
 
   if (RM == Reloc::Default) {
     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
     // use static relocation model by default.
     if (TT.isOSDarwin()) {
       if (is64Bit)
         RM = Reloc::PIC_;
static MCCodeGenInfo *createX86MCCodeGenInfo(const TargetTuple &TT,
   else if (CM == CodeModel::JITDefault)
     // 64-bit JIT places everything in the same buffer except external funcs.
     CM = is64Bit ? CodeModel::Large : CodeModel::Small;
 
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
+static MCInstPrinter *createX86MCInstPrinter(const TargetTuple &TT,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
                                              const MCRegisterInfo &MRI) {
   if (SyntaxVariant == 0)
     return new X86ATTInstPrinter(MAI, MII, MRI);
   if (SyntaxVariant == 1)
     return new X86IntelInstPrinter(MAI, MII, MRI);
   return nullptr;
 }
 
-static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
+static MCRelocationInfo *createX86MCRelocationInfo(const TargetTuple &TT,
                                                    MCContext &Ctx) {
-  if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
+  if (TT.isOSBinFormatMachO() && TT.getArch() == TargetTuple::x86_64)
     return createX86_64MachORelocationInfo(Ctx);
-  else if (TheTriple.isOSBinFormatELF())
+  else if (TT.isOSBinFormatELF())
     return createX86_64ELFRelocationInfo(Ctx);
   // Default to the stock relocation info.
-  return llvm::createMCRelocationInfo(TheTriple, Ctx);
+  return llvm::createMCRelocationInfo(TT, Ctx);
 }
 
 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
   return new MCInstrAnalysis(Info);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeX86TargetMC() {

llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp

 #include "X86GenRegisterInfo.inc"
 
 static cl::opt<bool>
 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
           cl::desc("Enable use of a base pointer for complex stack frames"));
 
 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
-                         X86_MC::getDwarfRegFlavour(TT, false),
-                         X86_MC::getDwarfRegFlavour(TT, true),
+                         X86_MC::getDwarfRegFlavour(TargetTuple(TT), false),
+                         X86_MC::getDwarfRegFlavour(TargetTuple(TT), true),
                          (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
   X86_MC::InitLLVM2SEHRegisterMapping(this);
 
   // Cache some information.
   Is64Bit = TT.isArch64Bit();
   IsWin64 = Is64Bit && TT.isOSWindows();
 
   // Use a callee-saved register as the base pointer.  These registers must

llvm/trunk/lib/Target/X86/X86Subtarget.cpp

X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
   initializeEnvironment();
   initSubtargetFeatures(CPU, FS);
   return *this;
 }
 
 X86Subtarget::X86Subtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const X86TargetMachine &TM,
                            unsigned StackAlignOverride)
-    : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
+    : X86GenSubtargetInfo(TargetTuple(TT), CPU, FS), X86ProcFamily(Others),
       PICStyle(PICStyles::None), TargetTriple(TT),
       StackAlignOverride(StackAlignOverride),
       In64BitMode(TargetTriple.getArch() == Triple::x86_64),
       In32BitMode(TargetTriple.getArch() == Triple::x86 &&
                   TargetTriple.getEnvironment() != Triple::CODE16),
       In16BitMode(TargetTriple.getArch() == Triple::x86 &&
                   TargetTriple.getEnvironment() == Triple::CODE16),
       TSInfo(), InstrInfo(initializeSubtargetDependencies(CPU, FS)),

llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCASMINFO_H
 #define LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class XCoreMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit XCoreMCAsmInfo(const Triple &TT);
+  explicit XCoreMCAsmInfo(const TargetTuple &TT);
 };
 
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp

 //===-- XCoreMCAsmInfo.cpp - XCore asm properties -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "XCoreMCAsmInfo.h"
 using namespace llvm;
 
 void XCoreMCAsmInfo::anchor() { }
 
-XCoreMCAsmInfo::XCoreMCAsmInfo(const Triple &TT) {
+XCoreMCAsmInfo::XCoreMCAsmInfo(const TargetTuple &TT) {
   SupportsDebugInformation = true;
   Data16bitsDirective = "\t.short\t";
   Data32bitsDirective = "\t.long\t";
   Data64bitsDirective = nullptr;
   ZeroDirective = "\t.space\t";
   CommentString = "#";
 
   AscizDirective = ".asciiz";

llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp

 #include "XCoreGenRegisterInfo.inc"
 
 static MCInstrInfo *createXCoreMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitXCoreMCInstrInfo(X);
   return X;
 }
 
-static MCRegisterInfo *createXCoreMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createXCoreMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitXCoreMCRegisterInfo(X, XCore::LR);
   return X;
 }
 
 static MCSubtargetInfo *
-createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+createXCoreMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) {
   return createXCoreMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
-                                       const Triple &TT) {
+                                       const TargetTuple &TT) {
   MCAsmInfo *MAI = new XCoreMCAsmInfo(TT);
 
   // Initial state of the frame pointer is SP.
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
-static MCCodeGenInfo *createXCoreMCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createXCoreMCCodeGenInfo(const TargetTuple &TT,
                                                Reloc::Model RM,
                                                CodeModel::Model CM,
                                                CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (RM == Reloc::Default) {
     RM = Reloc::Static;
   }
   if (CM == CodeModel::Default) {
     CM = CodeModel::Small;
   }
   if (CM != CodeModel::Small && CM != CodeModel::Large)
     report_fatal_error("Target only supports CodeModel Small or Large");
 
   X->initMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 
-static MCInstPrinter *createXCoreMCInstPrinter(const Triple &T,
+static MCInstPrinter *createXCoreMCInstPrinter(const TargetTuple &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,
                                                const MCRegisterInfo &MRI) {
   return new XCoreInstPrinter(MAI, MII, MRI);
 }
 
 XCoreTargetStreamer::XCoreTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}

llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp

 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "XCoreGenSubtargetInfo.inc"
 
 void XCoreSubtarget::anchor() { }
 
 XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, const TargetMachine &TM)
-    : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
-      TLInfo(TM, *this), TSInfo() {}
+    : XCoreGenSubtargetInfo(TargetTuple(TT), CPU, FS), InstrInfo(),
+      FrameLowering(*this), TLInfo(TM, *this), TSInfo() {}

llvm/trunk/tools/dsymutil/DwarfLinker.cpp

bool DwarfStreamer::init(Triple TheTriple, StringRef OutputFilename) {
 
   // Create the output file.
   std::error_code EC;
   OutFile =
       llvm::make_unique<raw_fd_ostream>(OutputFilename, EC, sys::fs::F_None);
   if (EC)
     return error(Twine(OutputFilename) + ": " + EC.message(), Context);
 
-  MS = TheTarget->createMCObjectStreamer(TheTriple, *MC, *MAB, *OutFile, MCE,
-                                         *MSTI, false,
+  MS = TheTarget->createMCObjectStreamer(TargetTuple(TheTriple), *MC, *MAB,
+                                         *OutFile, MCE, *MSTI, false,
                                          /*DWARFMustBeAtTheEnd*/ false);
   if (!MS)
     return error("no object streamer for target " + TripleName, Context);
 
   // Finally create the AsmPrinter we'll use to emit the DIEs.
   TM.reset(TheTarget->createTargetMachine(TripleName, "", "", TargetOptions()));
   if (!TM)
     return error("no target machine for target " + TripleName, Context);

llvm/trunk/tools/llvm-mc/llvm-mc.cpp

int main(int argc, char **argv) {
   std::unique_ptr<MCStreamer> Str;
 
   std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
   std::unique_ptr<MCSubtargetInfo> STI(
       TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
 
   MCInstPrinter *IP = nullptr;
   if (FileType == OFT_AssemblyFile) {
-    IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant,
-                                        *MAI, *MCII, *MRI);
+    IP = TheTarget->createMCInstPrinter(TargetTuple(Triple(TripleName)),
+                                        OutputAsmVariant, *MAI, *MCII, *MRI);
 
     // Set the display preference for hex vs. decimal immediates.
     IP->setPrintImmHex(PrintImmHex);
 
     // Set up the AsmStreamer.
     MCCodeEmitter *CE = nullptr;
     MCAsmBackend *MAB = nullptr;
     if (ShowEncoding) {
if (FileType == OFT_AssemblyFile) {
 
     if (!Out->os().supportsSeeking()) {
       BOS = make_unique<buffer_ostream>(Out->os());
       OS = BOS.get();
     }
 
     MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
     MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
-    Str.reset(TheTarget->createMCObjectStreamer(TheTriple, Ctx, *MAB, *OS, CE,
-                                                *STI, RelaxAll,
+    Str.reset(TheTarget->createMCObjectStreamer(TargetTuple(TheTriple), Ctx,
+                                                *MAB, *OS, CE, *STI, RelaxAll,
                                                 /*DWARFMustBeAtTheEnd*/ false));
     if (NoExecStack)
       Str->InitSections(true);
   }
 
   int Res = 1;
   bool disassemble = false;
   switch (Action) {

llvm/trunk/tools/llvm-objdump/MachODump.cpp

static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF,
   if (RelInfo) {
     Symbolizer.reset(TheTarget->createMCSymbolizer(
         TripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp,
         &SymbolizerInfo, &Ctx, std::move(RelInfo)));
     DisAsm->setSymbolizer(std::move(Symbolizer));
   }
   int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
   std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
-      Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI));
+      TargetTuple(Triple(TripleName)), AsmPrinterVariant, *AsmInfo, *InstrInfo,
+      *MRI));
   // Set the display preference for hex vs. decimal immediates.
   IP->setPrintImmHex(PrintImmHex);
   // Comment stream and backing vector.
   SmallString<128> CommentsToEmit;
   raw_svector_ostream CommentStream(CommentsToEmit);
   // FIXME: Setting the CommentStream in the InstPrinter is problematic in that
   // if it is done then arm64 comments for string literals don't get printed
   // and some constant get printed instead and not setting it causes intel
if (ThumbTarget) {
     if (ThumbRelInfo) {
       ThumbSymbolizer.reset(ThumbTarget->createMCSymbolizer(
           ThumbTripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp,
           &ThumbSymbolizerInfo, PtrThumbCtx, std::move(ThumbRelInfo)));
       ThumbDisAsm->setSymbolizer(std::move(ThumbSymbolizer));
     }
     int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect();
     ThumbIP.reset(ThumbTarget->createMCInstPrinter(
-        Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo,
-        *ThumbInstrInfo, *ThumbMRI));
+        TargetTuple(Triple(ThumbTripleName)), ThumbAsmPrinterVariant,
+        *ThumbAsmInfo, *ThumbInstrInfo, *ThumbMRI));
     // Set the display preference for hex vs. decimal immediates.
     ThumbIP->setPrintImmHex(PrintImmHex);
   }
 
   if (ThumbTarget && (!ThumbAsmInfo || !ThumbSTI || !ThumbDisAsm || !ThumbIP)) {
     errs() << "error: couldn't initialize disassembler for target "
            << ThumbTripleName << '\n';
     return;

llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

if (!DisAsm) {
     errs() << "error: no disassembler for target " << TripleName << "\n";
     return;
   }
 
   std::unique_ptr<const MCInstrAnalysis> MIA(
       TheTarget->createMCInstrAnalysis(MII.get()));
 
   int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
-  std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
-      Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MRI));
+  std::unique_ptr<MCInstPrinter> IP(
+      TheTarget->createMCInstPrinter(TargetTuple(Triple(TripleName)),
+                                     AsmPrinterVariant, *AsmInfo, *MII, *MRI));
   if (!IP) {
     errs() << "error: no instruction printer for target " << TripleName
       << '\n';
     return;
   }
   IP->setPrintImmHex(PrintImmHex);
   PrettyPrinter &PIP = selectPrettyPrinter(Triple(TripleName));
 

llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp

static int linkAndVerify() {
   MCContext Ctx(MAI.get(), MRI.get(), nullptr);
 
   std::unique_ptr<MCDisassembler> Disassembler(
     TheTarget->createMCDisassembler(*STI, Ctx));
   assert(Disassembler && "Unable to create disassembler!");
 
   std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo());
 
-  std::unique_ptr<MCInstPrinter> InstPrinter(
-      TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MRI));
+  std::unique_ptr<MCInstPrinter> InstPrinter(TheTarget->createMCInstPrinter(
+      TargetTuple(Triple(TripleName)), 0, *MAI, *MII, *MRI));
 
   // Load any dylibs requested on the command line.
   loadDylibs();
 
   // Instantiate a dynamic linker.
   TrivialMemoryManager MemMgr;
   RuntimeDyld Dyld(MemMgr, MemMgr);
   Dyld.setProcessAllSections(true);

llvm/trunk/utils/TableGen/SubtargetEmitter.cpp

#endif
   OS << "\n";
 #if 0
   OS << "}\n";
 #endif
 
   // MCInstrInfo initialization routine.
   OS << "static inline MCSubtargetInfo *create" << Target
      << "MCSubtargetInfoImpl("
-     << "const Triple &TT, StringRef CPU, StringRef FS) {\n";
+     << "const TargetTuple &TT, StringRef CPU, StringRef FS) {\n";
   OS << "  return new MCSubtargetInfo(TT, CPU, FS, ";
   if (NumFeatures)
     OS << Target << "FeatureKV, ";
   else
     OS << "None, ";
   if (NumProcs)
     OS << Target << "SubTypeKV, ";
   else
#endif
   // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
   OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
   OS << "#undef GET_SUBTARGETINFO_HEADER\n";
 
   std::string ClassName = Target + "GenSubtargetInfo";
   OS << "namespace llvm {\n";
   OS << "class DFAPacketizer;\n";
   OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
-     << "  explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
+     << "  explicit " << ClassName << "(const TargetTuple &TT, StringRef CPU, "
      << "StringRef FS);\n"
      << "public:\n"
      << "  unsigned resolveSchedClass(unsigned SchedClass, "
      << " const MachineInstr *DefMI,"
      << " const TargetSchedModel *SchedModel) const override;\n"
      << "  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
      << " const;\n"
      << "};\n";
OS << "extern const llvm::MCReadAdvanceEntry "
      << Target << "ReadAdvanceTable[];\n";
 
   if (SchedModels.hasItineraries()) {
     OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
     OS << "extern const unsigned " << Target << "OperandCycles[];\n";
     OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
   }
 
-  OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
-     << "StringRef FS)\n"
+  OS << ClassName << "::" << ClassName
+     << "(const TargetTuple &TT, StringRef CPU, StringRef FS)\n"
      << "  : TargetSubtargetInfo(TT, CPU, FS, ";
   if (NumFeatures)
     OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
   else
     OS << "None, ";
   if (NumProcs)
     OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";
   else