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Differential D106633

[RISCV][Docs] Add description about inline asm constraint for V.
ClosedPublic

Authored by HsiangKai on Jul 22 2021, 8:32 PM.

Details

Reviewers
craig.topper
khchen
kito-cheng
frasercrmck
rogfer01
Commits
rGee3aef93b736: [RISCV][Docs] Add description about inline asm constraint for V.
Summary

Add constraint 'v' in LLVM IR for vector registers and 'vr' and 'vm' for
C/C++ inline asm constraints.

Diff Detail

Event Timeline

HsiangKai created this revision.Jul 22 2021, 8:32 PM
Herald added subscribers: StephenFan, vkmr, jdoerfert and 9 others. · View Herald TranscriptJul 22 2021, 8:32 PM
HsiangKai requested review of this revision.Jul 22 2021, 8:32 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 22 2021, 8:32 PM
kito-cheng added inline comments.Jul 22 2021, 9:12 PM
llvm/docs/LangRef.rst
4782

I thought we only support vr and vm, but v only is not supported?

Harbormaster completed remote builds in B115767: Diff 361075.Jul 22 2021, 9:17 PM
HsiangKai added inline comments.Jul 23 2021, 4:30 AM
llvm/docs/LangRef.rst
4782

In LLVM IR, it still keeps to only use 'v'. The document is IR document. That's why I describe 'v' here.

In Clang, it will convert 'vr' and 'vm' to 'v' in LLVM IR.

You could see the convertConstraint in https://reviews.llvm.org/D98616.

frasercrmck accepted this revision.Jul 29 2021, 2:00 AM

LGTM.

This revision is now accepted and ready to land.Jul 29 2021, 2:00 AM
kito-cheng added inline comments.Jul 29 2021, 7:55 AM
llvm/docs/LangRef.rst
4782

Description at the begin of this chapter

`
The constraint codes are, in general, expected to behave the same way they do in GCC. LLVM’s support is often implemented on an ‘as-needed’ basis, to support C inline asm code which was supported by GCC. A mismatch in behavior between LLVM and GCC likely indicates a bug in LLVM.

I would suggest remove v, it's impossible to implement v and vr/vm on GCC site.

HsiangKai updated this revision to Diff 363000.Jul 30 2021, 2:15 AM

After D107139, usr 'vr' for vector register and 'vm' for vector mask in IR.

kito-cheng accepted this revision.Jul 30 2021, 2:30 AM

LGTM

Harbormaster completed remote builds in B117126: Diff 363000.Jul 30 2021, 3:15 AM
Closed by commit rGee3aef93b736: [RISCV][Docs] Add description about inline asm constraint for V. (authored by HsiangKai). · Explain WhyJul 31 2021, 3:01 PM
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rGee3aef93b736: [RISCV][Docs] Add description about inline asm constraint for V..

Revision Contents

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llvm/
docs/
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Diff 363322

llvm/docs/LangRef.rst

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- ``A``: An address operand (using a general-purpose register, without an - ``A``: An address operand (using a general-purpose register, without an
offset). offset).
- ``I``: A 12-bit signed integer immediate operand. - ``I``: A 12-bit signed integer immediate operand.
- ``J``: A zero integer immediate operand. - ``J``: A zero integer immediate operand.
- ``K``: A 5-bit unsigned integer immediate operand. - ``K``: A 5-bit unsigned integer immediate operand.
- ``f``: A 32- or 64-bit floating-point register (requires F or D extension). - ``f``: A 32- or 64-bit floating-point register (requires F or D extension).
- ``r``: A 32- or 64-bit general-purpose register (depending on the platform - ``r``: A 32- or 64-bit general-purpose register (depending on the platform
``XLEN``). ``XLEN``).
- ``vr``: A vector register. (requires V extension).
kito-chengUnsubmitted
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I thought we only support vr and vm, but v only is not supported?

kito-cheng: I thought we only support `vr` and `vm`, but `v` only is not supported?
HsiangKaiAuthorUnsubmitted
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In LLVM IR, it still keeps to only use 'v'. The document is IR document. That's why I describe 'v' here.

In Clang, it will convert 'vr' and 'vm' to 'v' in LLVM IR.

You could see the convertConstraint in https://reviews.llvm.org/D98616.

HsiangKai: In LLVM IR, it still keeps to only use 'v'. The document is IR document. That's why I describe…
kito-chengUnsubmitted
Not Done
ReplyInline Actions

Description at the begin of this chapter

`
The constraint codes are, in general, expected to behave the same way they do in GCC. LLVM’s support is often implemented on an ‘as-needed’ basis, to support C inline asm code which was supported by GCC. A mismatch in behavior between LLVM and GCC likely indicates a bug in LLVM.

I would suggest remove v, it's impossible to implement v and vr/vm on GCC site.

kito-cheng: Description at the begin of this chapter ```` The constraint codes are, in general, expected…
- ``vm``: A vector mask register. (requires V extension).
Sparc: Sparc:
- ``I``: An immediate 13-bit signed integer. - ``I``: An immediate 13-bit signed integer.
- ``r``: A 32-bit integer register. - ``r``: A 32-bit integer register.
- ``f``: Any floating-point register on SparcV8, or a floating-point - ``f``: Any floating-point register on SparcV8, or a floating-point
register in the "low" half of the registers on SparcV9. register in the "low" half of the registers on SparcV9.
- ``e``: Any floating-point register. (Same as ``f`` on SparcV8.) - ``e``: Any floating-point register. (Same as ``f`` on SparcV8.)
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