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[RISCV] Optimize getVLENFactoredAmount function.
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Authored by craig.topper on Apr 15 2021, 9:59 AM.

Details

Summary

If the local variable NumOfVReg isPowerOf2_32(NumOfVReg - 1) or isPowerOf2_32(NumOfVReg + 1), the ADDI and MUL instructions can be replaced with SLLI and ADD(or SUB) instructions.

Diff Detail

Event Timeline

StephenFan created this revision.Apr 15 2021, 9:59 AM
StephenFan requested review of this revision.Apr 15 2021, 9:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 15 2021, 9:59 AM

Add Kill flag

LGTM but please add a description of the optimization so that once it is committed it can be understood from git log without needing to read the patch.

frasercrmck accepted this revision.Apr 15 2021, 10:21 AM

LGTM but I agree with Craig.

This revision is now accepted and ready to land.Apr 15 2021, 10:21 AM

Hi @craig.topper , @frasercrmck , Sorry, I missed it. And I will add it right now.

Add git log info.

StephenFan edited the summary of this revision. (Show Details)Apr 16 2021, 8:09 PM

@StephenFan Is something holding up committing this?

craig.topper commandeered this revision.May 21 2021, 12:03 PM
craig.topper edited reviewers, added: StephenFan; removed: craig.topper.

Commandeering so I can update this. It no longer applies cleanly.

Minimize number of virtual registers used to match current version of getVLENFactoredAmount

@StephenFan Is something holding up committing this?

Sorry, I’m writing my undergraduate thesis recently, so I don’t have time to deal with this patch, thank you for helping me deal with it.

StephenFan accepted this revision.May 24 2021, 1:13 AM
This revision was landed with ongoing or failed builds.May 24 2021, 10:06 AM
This revision was automatically updated to reflect the committed changes.
rogfer01 added inline comments.May 27 2021, 1:29 PM
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
1283

I saw a test failing downstream due to this. This should be addImm(ShiftAmount)

frasercrmck added inline comments.May 28 2021, 12:56 AM
llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
306–308

@rogfer01 I believe this line shows the issue you're talking about?