[LLDB] Support AArch64 PAC elf-core register read

[omjavaid]

Summary

This adds support for reading AArch64 Pointer Authentication regset
from elf-core file. Also includes a test-case for the same. Furthermore
there is also a slight refactoring of RegisterContextPOSIXCore_arm64
members and constructor. linux-aarch64-pac.core file is generated using
lldb/test/API/functionalities/postmortem/elf-core/main.c with following
clang arguments:
-march=armv8.5-a -mbranch-protection=pac-ret+leaf -nostdlib -static -g

[DavidSpickett]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

32

How is the sizeof() calculated here? Is it the size of the masks themselves, or a header block. (SVE above is clearly a header of some kind)

lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

451

Do you need anything special to generate the core file? Might be worth noting in the commit message.

Though I guess you can just compile a hello world on a Linux system with PAC.

453

values = {
  "data_mask": "...",
  ...
}

(or dict(data_mask="..."))

[labath]

Seems reasonable to me. I'm happy if @DavidSpickett is.

[omjavaid]

Resolved review comments.

[omjavaid]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

32

added a comment to reflect reason behind pac data minimum size

lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

451

Updated commit message.

[DavidSpickett]

LGTM

lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h

protected:
 
   bool IsGPR(unsigned reg);
 
   bool IsFPR(unsigned reg);
 
   size_t GetFPUSize() { return sizeof(RegisterInfoPOSIX_arm64::FPU); }
 
   bool IsSVE(unsigned reg) const;
+  bool IsPAuth(unsigned reg) const;
 
   bool IsSVEZ(unsigned reg) const { return m_register_info_up->IsSVEZReg(reg); }
   bool IsSVEP(unsigned reg) const { return m_register_info_up->IsSVEPReg(reg); }
   bool IsSVEVG(unsigned reg) const {
     return m_register_info_up->IsSVERegVG(reg);
   }
 
   uint32_t GetRegNumSVEZ0() const {

lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp

if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
     return true;
   return false;
 }
 
 bool RegisterContextPOSIX_arm64::IsSVE(unsigned reg) const {
   return m_register_info_up->IsSVEReg(reg);
 }
 
+bool RegisterContextPOSIX_arm64::IsPAuth(unsigned reg) const {
+  return m_register_info_up->IsPAuthReg(reg);
+}
+
 RegisterContextPOSIX_arm64::RegisterContextPOSIX_arm64(
     lldb_private::Thread &thread,
     std::unique_ptr<RegisterInfoPOSIX_arm64> register_info)
     : lldb_private::RegisterContext(thread, 0),
       m_register_info_up(std::move(register_info)) {}
 
 RegisterContextPOSIX_arm64::~RegisterContextPOSIX_arm64() {}
 

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

public:
 
   bool VectorSizeIsValid(uint32_t vq) {
     if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax)
       return true;
     return false;
   }
 
   bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }
+  bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }
 
   bool IsSVEReg(unsigned reg) const;
   bool IsSVEZReg(unsigned reg) const;
   bool IsSVEPReg(unsigned reg) const;
   bool IsSVERegVG(unsigned reg) const;
   bool IsPAuthReg(unsigned reg) const;
   bool IsMTEReg(unsigned reg) const;
 

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h

public:
 
   bool HardwareSingleStep(bool enable) override;
 
 protected:
   RegisterContextCorePOSIX_arm64(
       lldb_private::Thread &thread,
       std::unique_ptr<RegisterInfoPOSIX_arm64> register_info,
       const lldb_private::DataExtractor &gpregset,
-      const lldb_private::DataExtractor &sveregset,
       llvm::ArrayRef<lldb_private::CoreNote> notes);
 
   bool ReadGPR() override;
 
   bool ReadFPR() override;
 
   bool WriteGPR() override;
 
   bool WriteFPR() override;
 
 private:
-  lldb::DataBufferSP m_gpr_buffer;
-  lldb_private::DataExtractor m_gpr;
-  lldb_private::DataExtractor m_fpregset;
-  lldb_private::DataExtractor m_sveregset;
+  lldb_private::DataExtractor m_gpr_data;
+  lldb_private::DataExtractor m_fpr_data;
+  lldb_private::DataExtractor m_sve_data;
+  lldb_private::DataExtractor m_pac_data;
 
   SVEState m_sve_state;
   uint16_t m_sve_vector_length = 0;
 
   const uint8_t *GetSVEBuffer(uint64_t offset = 0);
 
   void ConfigureRegisterContext();
 
   uint32_t CalculateSVEOffset(const lldb_private::RegisterInfo *reg_info);
 
   uint64_t GetSVERegVG() { return m_sve_vector_length / 8; }
 };
 
 #endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_ARM64_H

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

 #include <memory>
 
 using namespace lldb_private;
 
 std::unique_ptr<RegisterContextCorePOSIX_arm64>
 RegisterContextCorePOSIX_arm64::Create(Thread &thread, const ArchSpec &arch,
                                        const DataExtractor &gpregset,
                                        llvm::ArrayRef<CoreNote> notes) {
-  DataExtractor sveregset =
-      getRegset(notes, arch.GetTriple(), AARCH64_SVE_Desc);
-
   Flags opt_regsets = RegisterInfoPOSIX_arm64::eRegsetMaskDefault;
-  if (sveregset.GetByteSize() > sizeof(sve::user_sve_header))
+
+  DataExtractor sve_data = getRegset(notes, arch.GetTriple(), AARCH64_SVE_Desc);
+  if (sve_data.GetByteSize() > sizeof(sve::user_sve_header))
     opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSVE);
+
+  // Pointer Authentication register set data is based on struct
+  // user_pac_mask declared in ptrace.h. See reference implementation
+  // in Linux kernel source at arch/arm64/include/uapi/asm/ptrace.h.
+  DataExtractor pac_data = getRegset(notes, arch.GetTriple(), AARCH64_PAC_Desc);
+  if (pac_data.GetByteSize() >= sizeof(uint64_t) * 2)
+    opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskPAuth);
+
   auto register_info_up =
       std::make_unique<RegisterInfoPOSIX_arm64>(arch, opt_regsets);
   return std::unique_ptr<RegisterContextCorePOSIX_arm64>(
       new RegisterContextCorePOSIX_arm64(thread, std::move(register_info_up),
-                                         gpregset, sveregset, notes));
+                                         gpregset, notes));
 }
 
 RegisterContextCorePOSIX_arm64::RegisterContextCorePOSIX_arm64(
     Thread &thread, std::unique_ptr<RegisterInfoPOSIX_arm64> register_info,
-    const DataExtractor &gpregset, const DataExtractor &sveregset,
-    llvm::ArrayRef<CoreNote> notes)
-    : RegisterContextPOSIX_arm64(thread, std::move(register_info)),
-      m_sveregset(sveregset) {
-  m_gpr_buffer = std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
-                                                  gpregset.GetByteSize());
-  m_gpr.SetData(m_gpr_buffer);
-  m_gpr.SetByteOrder(gpregset.GetByteOrder());
+    const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
+    : RegisterContextPOSIX_arm64(thread, std::move(register_info)) {
+  m_gpr_data.SetData(std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
+                                                      gpregset.GetByteSize()));
+  m_gpr_data.SetByteOrder(gpregset.GetByteOrder());
+
+  const llvm::Triple &target_triple =
+      m_register_info_up->GetTargetArchitecture().GetTriple();
+  m_fpr_data = getRegset(notes, target_triple, FPR_Desc);
+
+  if (m_register_info_up->IsSVEEnabled())
+    m_sve_data = getRegset(notes, target_triple, AARCH64_SVE_Desc);
 
-  m_fpregset = getRegset(
-      notes, m_register_info_up->GetTargetArchitecture().GetTriple(), FPR_Desc);
+  if (m_register_info_up->IsPAuthEnabled())
+    m_pac_data = getRegset(notes, target_triple, AARCH64_PAC_Desc);
 
   ConfigureRegisterContext();
 }
 
 RegisterContextCorePOSIX_arm64::~RegisterContextCorePOSIX_arm64() {}
 
 bool RegisterContextCorePOSIX_arm64::ReadGPR() { return true; }
 
 bool RegisterContextCorePOSIX_arm64::ReadFPR() { return false; }
 
 bool RegisterContextCorePOSIX_arm64::WriteGPR() {
   assert(0);
   return false;
 }
 
 bool RegisterContextCorePOSIX_arm64::WriteFPR() {
   assert(0);
   return false;
 }
 
 const uint8_t *RegisterContextCorePOSIX_arm64::GetSVEBuffer(uint64_t offset) {
-  return m_sveregset.GetDataStart() + offset;
+  return m_sve_data.GetDataStart() + offset;
 }
 
 void RegisterContextCorePOSIX_arm64::ConfigureRegisterContext() {
-  if (m_sveregset.GetByteSize() > sizeof(sve::user_sve_header)) {
+  if (m_sve_data.GetByteSize() > sizeof(sve::user_sve_header)) {
     uint64_t sve_header_field_offset = 8;
-    m_sve_vector_length = m_sveregset.GetU16(&sve_header_field_offset);
+    m_sve_vector_length = m_sve_data.GetU16(&sve_header_field_offset);
     sve_header_field_offset = 12;
     uint16_t sve_header_flags_field =
-        m_sveregset.GetU16(&sve_header_field_offset);
+        m_sve_data.GetU16(&sve_header_field_offset);
     if ((sve_header_flags_field & sve::ptrace_regs_mask) ==
         sve::ptrace_regs_fpsimd)
       m_sve_state = SVEState::FPSIMD;
     else if ((sve_header_flags_field & sve::ptrace_regs_mask) ==
              sve::ptrace_regs_sve)
       m_sve_state = SVEState::Full;
 
     if (!sve::vl_valid(m_sve_vector_length)) {

 
 bool RegisterContextCorePOSIX_arm64::ReadRegister(const RegisterInfo *reg_info,
                                                   RegisterValue &value) {
   Status error;
   lldb::offset_t offset;
 
   offset = reg_info->byte_offset;
   if (offset + reg_info->byte_size <= GetGPRSize()) {
-    uint64_t v = m_gpr.GetMaxU64(&offset, reg_info->byte_size);
+    uint64_t v = m_gpr_data.GetMaxU64(&offset, reg_info->byte_size);
     if (offset == reg_info->byte_offset + reg_info->byte_size) {
       value = v;
       return true;
     }
   }
 
   const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
   if (reg == LLDB_INVALID_REGNUM)
     return false;
 
   if (IsFPR(reg)) {
     if (m_sve_state == SVEState::Disabled) {
       // SVE is disabled take legacy route for FPU register access
       offset -= GetGPRSize();
-      if (offset < m_fpregset.GetByteSize()) {
-        value.SetFromMemoryData(reg_info, m_fpregset.GetDataStart() + offset,
+      if (offset < m_fpr_data.GetByteSize()) {
+        value.SetFromMemoryData(reg_info, m_fpr_data.GetDataStart() + offset,
                                 reg_info->byte_size, lldb::eByteOrderLittle,
                                 error);
         return error.Success();
       }
     } else {
       // FPSR and FPCR will be located right after Z registers in
       // SVEState::FPSIMD while in SVEState::Full they will be located at the
       // end of register data after an alignment correction based on currently
if (m_sve_state == SVEState::Disabled) {
         // Extract SVE Z register value register number for this reg_info
         if (reg_info->value_regs &&
             reg_info->value_regs[0] != LLDB_INVALID_REGNUM)
           sve_reg_num = reg_info->value_regs[0];
         offset = CalculateSVEOffset(GetRegisterInfoAtIndex(sve_reg_num));
       }
 
       assert(sve_reg_num != LLDB_INVALID_REGNUM);
-      assert(offset < m_sveregset.GetByteSize());
+      assert(offset < m_sve_data.GetByteSize());
       value.SetFromMemoryData(reg_info, GetSVEBuffer(offset),
                               reg_info->byte_size, lldb::eByteOrderLittle,
                               error);
     }
   } else if (IsSVE(reg)) {
     if (IsSVEVG(reg)) {
       value = GetSVERegVG();
       return true;
     }
 
     switch (m_sve_state) {
     case SVEState::FPSIMD: {
       // In FPSIMD state SVE payload mirrors legacy fpsimd struct and so just
       // copy 16 bytes of v register to the start of z register. All other
       // SVE register will be set to zero.
       uint64_t byte_size = 1;
       uint8_t zeros = 0;
       const uint8_t *src = &zeros;
       if (IsSVEZ(reg)) {
         byte_size = 16;
         offset = CalculateSVEOffset(reg_info);
-        assert(offset < m_sveregset.GetByteSize());
+        assert(offset < m_sve_data.GetByteSize());
         src = GetSVEBuffer(offset);
       }
       value.SetFromMemoryData(reg_info, src, byte_size, lldb::eByteOrderLittle,
                               error);
     } break;
     case SVEState::Full:
       offset = CalculateSVEOffset(reg_info);
-      assert(offset < m_sveregset.GetByteSize());
+      assert(offset < m_sve_data.GetByteSize());
       value.SetFromMemoryData(reg_info, GetSVEBuffer(offset),
                               reg_info->byte_size, lldb::eByteOrderLittle,
                               error);
       break;
     case SVEState::Disabled:
     default:
       return false;
     }
+  } else if (IsPAuth(reg)) {
+    offset = reg_info->byte_offset - m_register_info_up->GetPAuthOffset();
+    assert(offset < m_pac_data.GetByteSize());
+    value.SetFromMemoryData(reg_info, m_pac_data.GetDataStart() + offset,
+                            reg_info->byte_size, lldb::eByteOrderLittle, error);
   } else
     return false;
 
   return error.Success();
 }
 
 bool RegisterContextCorePOSIX_arm64::ReadAllRegisterValues(
     lldb::DataBufferSP &data_sp) {

lldb/source/Plugins/Process/elf-core/RegisterUtilities.h

constexpr RegsetDesc FPR_Desc[] = {
     {llvm::Triple::NetBSD, llvm::Triple::x86_64, NETBSD::AMD64::NT_FPREGS},
     {llvm::Triple::OpenBSD, llvm::Triple::UnknownArch, OPENBSD::NT_FPREGS},
 };
 
 constexpr RegsetDesc AARCH64_SVE_Desc[] = {
     {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_SVE},
 };
 
+constexpr RegsetDesc AARCH64_PAC_Desc[] = {
+    {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_PAC_MASK},
+};
+
 constexpr RegsetDesc PPC_VMX_Desc[] = {
     {llvm::Triple::FreeBSD, llvm::Triple::UnknownArch, llvm::ELF::NT_PPC_VMX},
     {llvm::Triple::Linux, llvm::Triple::UnknownArch, llvm::ELF::NT_PPC_VMX},
 };
 
 constexpr RegsetDesc PPC_VSX_Desc[] = {
     {llvm::Triple::Linux, llvm::Triple::UnknownArch, llvm::ELF::NT_PPC_VSX},
 };
 
 } // namespace lldb_private
 
 #endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERUTILITIES_H

lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

def test_aarch64_sve_regs_full(self):
         values["p4"] = "{0x00 0x00 0x00 0x00}"
 
         for regname, value in values.items():
             self.expect("register read {}".format(regname),
                         substrs=["{} = {}".format(regname, value)])
 
         self.expect("register read --all")
 
+    @skipIfLLVMTargetMissing("AArch64")
+    def test_aarch64_pac_regs(self):
+        # Test AArch64/Linux Pointer Authenication register read
+        target = self.dbg.CreateTarget(None)
+        self.assertTrue(target, VALID_TARGET)
+        process = target.LoadCore("linux-aarch64-pac.core")
+
+        values = {"data_mask": "0x007f00000000000", "code_mask": "0x007f00000000000"}
+
+        for regname, value in values.items():
+            self.expect("register read {}".format(regname),
+                        substrs=["{} = {}".format(regname, value)])
+
+        self.expect("register read --all")
+
     @skipIfLLVMTargetMissing("ARM")
     def test_arm_core(self):
         # check 32 bit ARM core file
         target = self.dbg.CreateTarget(None)
         self.assertTrue(target, VALID_TARGET)
         process = target.LoadCore("linux-arm.core")
 
         values = {}