[PowerPC] Materialize 34-bit constants with pli directly

[amyk]

Summary

D92879 introduced emitting pli whenever a constant fits within 34-bits on 64-bit mode.

However, the pli instruction is not produced directly. Instead, we materialize
a 34-bit constant in selectI64Imm(), and rely on td pattern matching to instead
produce a pli. This becomes problematic as there is no guarantee that the 34-bit
constant will reach the td pattern selection for pli and it is possible for other
transformations (such as complex bit permutations) to also produce and utilize
the 34-bit constant materialized through selectI64Imm().

This patch instead produces pli on Power10 directly whenever the constant fits
within 34-bits.

[nemanjai]

LGTM with a comment-related nit.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1062

Nit: this clearly doesn't apply any longer. Please updated it.

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4877–4878

This may no longer be necessary, but this isn't something you necessarily have to address in this patch.

[amyk]

Address review comments:

• Update the comment for emitting pli directly
• Remove the case to ReplaceNode() if the resulting node from selectI64Imm() is not a constant.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

static SDNode *selectI64ImmDirectPrefix(SelectionDAG *CurDAG, const SDLoc &dl,
   auto getI64Imm = [CurDAG, dl](uint64_t Imm) {
     return CurDAG->getTargetConstant(Imm, dl, MVT::i64);
   };
 
   // Following patterns use 1 instruction to materialize Imm.
   InstCnt = 1;
 
   // The pli instruction can materialize up to 34 bits directly.
-  // It is defined in the TD file and so we just return the constant.
+  // If a constant fits within 34-bits, emit the pli instruction here directly.
   if (isInt<34>(Imm))
-    return cast<ConstantSDNode>(CurDAG->getConstant(Imm, dl, MVT::i64));
+    return CurDAG->getMachineNode(PPC::PLI8, dl, MVT::i64,
+                                  CurDAG->getTargetConstant(Imm, dl, MVT::i64));
 
   // Require at least two instructions.
   InstCnt = 2;
   SDNode *Result = nullptr;
   // Patterns : {zeros}{ones}{33-bit value}{zeros}
   //            {zeros}{33-bit value}{zeros}
   //            {zeros}{ones}{33-bit value}
   //            {ones}{33-bit value}{zeros}
void PPCDAGToDAGISel::Select(SDNode *N) {
   // Try to emit integer compares as GPR-only sequences (i.e. no use of CR).
   if (tryIntCompareInGPR(N))
     return;
 
   switch (N->getOpcode()) {
   default: break;
 
   case ISD::Constant:
     if (N->getValueType(0) == MVT::i64) {
-      SDNode *ResNode = selectI64Imm(CurDAG, N);
-      if (!isa<ConstantSDNode>(ResNode)) {
-        ReplaceNode(N, ResNode);
-        return;
-      }
-    }
+      ReplaceNode(N, selectI64Imm(CurDAG, N));
     break;
 
   case ISD::INTRINSIC_WO_CHAIN: {
     if (!Subtarget->isISA3_1())
       break;
     unsigned Opcode = 0;
     switch (N->getConstantOperandVal(0)) {
     default:

llvm/test/CodeGen/PowerPC/p10-constants.ll

 ; CHECK:         pli r3, 262916796
 ; CHECK-NEXT:    rldimi r3, r3, 32, 0
 ; CHECK-NEXT:    blr
 entry:
   ; 0x0FABCABC0FABCABC
   ret i64 1129219040652020412
 }
 
+; Producing `pli` when the constant fits within 34-bits and the constant
+; is being produced in other transformations (such as complex bit permutations).
+define i64 @t_34Bits_Complex(i64 %a, i64 %b) {
+; CHECK-LABEL: t_34Bits_Complex:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rotldi r4, r4, 30
+; CHECK-NEXT:    rldimi r3, r4, 34, 31
+; CHECK-NEXT:    pli r4, -268435457
+; CHECK-NEXT:    and r3, r3, r4
+; CHECK-NEXT:    blr
+;
+; CHECK32-LABEL: t_34Bits_Complex:
+; CHECK32:       # %bb.0: # %entry
+; CHECK32-NEXT:    rlwinm r4, r6, 0, 4, 2
+; CHECK32-NEXT:    rlwimi r3, r5, 0, 31, 29
+; CHECK32-NEXT:    blr
+entry:
+  %and = and i64 %a, 8589934592
+  %and1 = and i64 %b, -8858370049
+  %or = or i64 %and1, %and
+  ret i64 %or
+}
+
 ; The load immediates resulting from phi-nodes are needed to test whether
 ; li/lis is preferred to pli by the instruction selector.
 define dso_local void @t_phiNode() {
 ; CHECK-LABEL: t_phiNode:
 ; CHECK:  lis r6, 18
 ; CHECK-NEXT: li r5, 291
 ; CHECK-NEXT: li r4, 0
 ; CHECK-NEXT:   cmpwi r3, 1