Refactor: Simplify boolean conditional return statements in lib/Target/Mips

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements

[craig.topper]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

935

Fix indentation

1880

Fix indentation

1900

Fix indentation

1918

Fix indentation

[LegalizeAdulthood]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

935

Fixed.

1880

Fixed.

1900

Fixed.

1918

Fixed.

[LegalizeAdulthood]

clang-format

[LegalizeAdulthood]

clang-format

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

public:
   bool isRegList() const { return Kind == k_RegList; }
   bool isMovePRegPair() const {
     if (Kind != k_RegList || RegList.List->size() != 2)
       return false;
 
     unsigned R0 = RegList.List->front();
     unsigned R1 = RegList.List->back();
 
-    if ((R0 == Mips::A1 && R1 == Mips::A2) ||
+    return (R0 == Mips::A1 && R1 == Mips::A2) ||
         (R0 == Mips::A1 && R1 == Mips::A3) ||
         (R0 == Mips::A2 && R1 == Mips::A3) ||
         (R0 == Mips::A0 && R1 == Mips::S5) ||
         (R0 == Mips::A0 && R1 == Mips::S6) ||
         (R0 == Mips::A0 && R1 == Mips::A1) ||
         (R0 == Mips::A0 && R1 == Mips::A2) ||
-        (R0 == Mips::A0 && R1 == Mips::A3))
-      return true;
-
-    return false;
+        (R0 == Mips::A0 && R1 == Mips::A3);
   }
 
   StringRef getToken() const {
     assert(Kind == k_Token && "Invalid access!");
     return StringRef(Tok.Data, Tok.Length);
   }
   bool isRegPair() const { return Kind == k_RegPair; }
 

 
 bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
                                   SmallVectorImpl<MCInst> &Instructions) {
   const MCOperand &ImmOp = Inst.getOperand(1);
   assert(ImmOp.isImm() && "expected immediate operand kind");
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
-  if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
-                    Is32BitImm, IDLoc, Instructions))
-    return true;
-
-  return false;
+  return loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
+                    Is32BitImm, IDLoc, Instructions);
 }
 
 bool
 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
                                     SmallVectorImpl<MCInst> &Instructions) {
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
   const MCOperand &ImmOp = Inst.getOperand(2);
   assert((ImmOp.isImm() || ImmOp.isExpr()) &&
          "expected immediate operand kind");
   if (!ImmOp.isImm()) {
     expandLoadAddressSym(DstRegOp, ImmOp, Is32BitImm, IDLoc, Instructions);
     return false;
   }
   const MCOperand &SrcRegOp = Inst.getOperand(1);
   assert(SrcRegOp.isReg() && "expected register operand kind");
 
-  if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
-                    Is32BitImm, IDLoc, Instructions))
-    return true;
-
-  return false;
+  return loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
+                    Is32BitImm, IDLoc, Instructions);
 }
 
 bool
 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
                                     SmallVectorImpl<MCInst> &Instructions) {
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
   const MCOperand &ImmOp = Inst.getOperand(1);
   assert((ImmOp.isImm() || ImmOp.isExpr()) &&
          "expected immediate operand kind");
   if (!ImmOp.isImm()) {
     expandLoadAddressSym(DstRegOp, ImmOp, Is32BitImm, IDLoc, Instructions);
     return false;
   }
 
-  if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
-                    Is32BitImm, IDLoc, Instructions))
-    return true;
-
-  return false;
+  return loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
+                    Is32BitImm, IDLoc, Instructions);
 }
 
 void MipsAsmParser::expandLoadAddressSym(
     const MCOperand &DstRegOp, const MCOperand &SymOp, bool Is32BitSym,
     SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) {
   warnIfNoMacro(IDLoc);
 
   if (Is32BitSym && isABI_N64())

lib/Target/Mips/MipsFastISel.cpp

bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
   if (Ty->isVectorTy())
     return false;
 
   if (isTypeLegal(Ty, VT))
     return true;
 
   // If this is a type than can be sign or zero-extended to a basic operation
   // go ahead and accept it now.
-  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
-    return true;
-
-  return false;
+  return VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16;
 }
 
 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
   if (isTypeLegal(Ty, VT))
     return true;
   // We will extend this in a later patch:
   //   If this is a type than can be sign or zero-extended to a basic operation
   //   go ahead and accept it now.
-  if (VT == MVT::i8 || VT == MVT::i16)
-    return true;
-  return false;
+  return VT == MVT::i8 || VT == MVT::i16;
 }
 // Because of how EmitCmp is called with fast-isel, you can
 // end up with redundant "andi" instructions after the sequences emitted below.
 // We should try and solve this issue in the future.
 //
 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
   const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
   bool IsUnsigned = CI->isUnsigned();
bool MipsFastISel::selectStore(const Instruction *I) {
   if (SrcReg == 0)
     return false;
 
   // See if we can handle this address.
   Address Addr;
   if (!computeAddress(I->getOperand(1), Addr))
     return false;
 
-  if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
-    return false;
-  return true;
+  return emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment());
 }
 
 //
 // This can cause a redundant sltiu to be generated.
 // FIXME: try and eliminate this in a future patch.
 //
 bool MipsFastISel::selectBranch(const Instruction *I) {
   const BranchInst *BI = cast<BranchInst>(I);

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

return selectAddrRegImm(Addr, Base, Offset) ||
     selectAddrDefault(Addr, Base, Offset);
 }
 
 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
                                            SDValue &Offset) const {
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
-  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
-    return true;
-
-  return false;
+  return selectAddrFrameIndexOffset(Addr, Base, Offset, 9);
 }
 
 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
                                             SDValue &Offset) const {
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
-  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
-    return true;
-
-  return false;
+  return selectAddrFrameIndexOffset(Addr, Base, Offset, 10);
 }
 
 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
                                             SDValue &Offset) const {
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
-  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
-    return true;
-
-  return false;
+  return selectAddrFrameIndexOffset(Addr, Base, Offset, 12);
 }
 
 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
                                             SDValue &Offset) const {
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
-  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
-    return true;
-
-  return false;
+  return selectAddrFrameIndexOffset(Addr, Base, Offset, 16);
 }
 
 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
                                          SDValue &Offset) const {
   return selectAddrRegImm12(Addr, Base, Offset) ||
     selectAddrDefault(Addr, Base, Offset);
 }
 
bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
   return selectAddrDefault(Addr, Base, Offset);
 }
 
 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
                                           SDValue &Offset) const {
   if (selectAddrRegImm10(Addr, Base, Offset))
     return true;
 
-  if (selectAddrDefault(Addr, Base, Offset))
-    return true;
-
-  return false;
+  return selectAddrDefault(Addr, Base, Offset);
 }
 
 // Select constant vector splats.
 //
 // Returns true and sets Imm if:
 // * MSA is enabled
 // * N is a ISD::BUILD_VECTOR representing a constant splat
 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,

lib/Target/Mips/MipsSEISelLowering.cpp

lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
   return Op;
 }
 
 static bool isConstantOrUndef(const SDValue Op) {
   if (Op->getOpcode() == ISD::UNDEF)
     return true;
   if (isa<ConstantSDNode>(Op))
     return true;
-  if (isa<ConstantFPSDNode>(Op))
-    return true;
-  return false;
+  return isa<ConstantFPSDNode>(Op);
 }
 
 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
   for (unsigned i = 0; i < Op->getNumOperands(); ++i)
     if (isConstantOrUndef(Op->getOperand(i)))
       return true;
   return false;
 }