[builtins] Fix value of ARM_INEXACT

[arichardson]

Summary

The existing value of 0x1000 is the bit to enable trapping on inexact (IXE)
not the status bit that indicates that an inexact calculation happened.

[peter.smith]

LGTM, although give Yi some time to respond in case there is something I've missed about the original context.

Relevant quotes from the Arm ARM from https://developer.arm.com/documentation/ddi0487/latest/

IXC, bit [4]

Inexact cumulative floating-point exception bit. This bit is set to 1 to indicate that the Inexact
floating-point exception has occurred since 0 was last written to this bit.
How VFP instructions update this bit depends on the value of the IXE bit.
Advanced SIMD instructions set this bit if the Inexact floating-point exception occurs in one or
more of the floating-point calculations performed by the instruction, regardless of the value of the
IXE bit.
The criteria for the Inexact floating-point exception to occur are different in Flush-to-zero mode.
For more information, see Flushing denormalized numbers to zero on page A1-54.
On a Warm reset, this field resets to an architecturally UNKNOWN value.

IXE bit [12]

Inexact floating-point exception trap enable.
0b0 Untrapped exception handling selected. If the floating-point exception occurs, the IXC
bit is set to 1.
0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does
not update the IXC bit.
This bit is RW only if the implementation supports the trapping of floating-point exceptions. In an
implementation that does not support floating-point exception trapping, this bit is RAZ/WI.
When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always
use untrapped floating-point exception handling in AArch32 state.
On a Warm reset, this field resets to an architecturally UNKNOWN value.

[kongyi]

IIRC, Android test suite was expecting this bit to be set, maybe the test is incorrect. Let me check...

compiler-rt/lib/builtins/arm/fp_mode.c

 #define ARM_TONEAREST  0x0
 #define ARM_UPWARD     0x1
 #define ARM_DOWNWARD   0x2
 #define ARM_TOWARDZERO 0x3
 #define ARM_RMODE_MASK (ARM_TONEAREST | ARM_UPWARD | \
                         ARM_DOWNWARD | ARM_TOWARDZERO)
 #define ARM_RMODE_SHIFT 22
 
-#define ARM_INEXACT     0x1000
+#define ARM_INEXACT     0x10
 
 #ifndef __ARM_FP
 // For soft float targets, allow changing rounding mode by overriding the weak
 // __arm_fe_default_rmode symbol.
 FE_ROUND_MODE __attribute__((weak)) __arm_fe_default_rmode = FE_TONEAREST;
 #endif
 
 FE_ROUND_MODE __fe_getround() {