[AVR] Fix lifeness issues in the AVR backend

[aykevl]

Summary

This patch is a large number of small changes that should hopefully not
affect the generated machine code but are still important to get right
so that the machine verifier won't complain about them. It is the last
in a series of patches to get all the AVR codegen tests to pass with the
machine verifier enabled.

The llvm/test/CodeGen/AVR/pseudo/*.mir changes are also necessary
because without the liveins the used registers are considered undefined
by the machine verifier and it will complain about them.

---

I'm aware there are other issues that trigger the machine verifier in the AVR backend, but this series of patches should at least get ninja -j4 check-llvm-codegen-avr to work with the machine verifier enabled. Actually enabling it for the AVR backend will need to be done in a separate patch (isMachineVerifierClean).

[benshi001]

We need to fix the build failure before commit this patch.

[aykevl]

In D97172#2593337, @benshi001 wrote:

We need to fix the build failure before commit this patch.

What do you mean? Which build failure should be fixed?

[benshi001]

In D97172#2596031, @aykevl wrote:

In D97172#2593337, @benshi001 wrote:

We need to fix the build failure before commit this patch.

What do you mean? Which build failure should be fixed?

https://buildkite.com/llvm-project/diff-checks/builds/30083

Is it an incident? I saw Failed to apply 1_325355.patch. on this page.

[aykevl]

Re-upload (without changes) to try to get the buildbot working...

[benshi001]

In D97172#2600202, @aykevl wrote:

Re-upload (without changes) to try to get the buildbot working...

So you are appreciated to commit it .

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register SrcLoReg, SrcHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
+  bool DstIsUndef = MI.getOperand(0).isUndef();
   bool SrcIsKill = MI.getOperand(1).isKill();
   unsigned OpLo = AVR::STPtrRr;
   unsigned OpHi = AVR::STDPtrQRr;
   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
 
   //:TODO: need to reverse this order like inw and stsw?
   auto MIBLO = buildMI(MBB, MBBI, OpLo)
-    .addReg(DstReg)
+    .addReg(DstReg, getUndefRegState(DstIsUndef))
     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
 
   auto MIBHI = buildMI(MBB, MBBI, OpHi)
-    .addReg(DstReg)
+    .addReg(DstReg, getUndefRegState(DstIsUndef))
     .addImm(1)
     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
 
   MIBLO.setMemRefs(MI.memoperands());
   MIBHI.setMemRefs(MI.memoperands());
 
   MI.eraseFromParent();
   return true;

   // SREG is implicitly dead.
   MI0->getOperand(3).setIsDead();
 
   // eor Rh, Rl
   auto MI1 =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, getKillRegState(DstIsKill))
-          .addReg(DstLoReg, getKillRegState(DstIsKill));
+          .addReg(DstLoReg);
   // SREG is implicitly dead.
   MI1->getOperand(3).setIsDead();
 
   // andi Rl, 0xf0
   auto MI2 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstLoReg, getKillRegState(DstIsKill))
           .addImm(0xf0);
   // SREG is implicitly dead.
   MI2->getOperand(3).setIsDead();
 
   // eor Rh, Rl
   auto MI3 =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, getKillRegState(DstIsKill))
-          .addReg(DstLoReg, getKillRegState(DstIsKill));
+          .addReg(DstLoReg);
   if (ImpIsDead)
     MI3->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::LSLW8Rd>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(2).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // mov Rh, Rl
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg);
 
   // clr Rl
   auto MIBLO =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstLoReg, getKillRegState(DstIsKill))
           .addReg(DstLoReg, getKillRegState(DstIsKill));
   if (ImpIsDead)

   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(2).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // mov Rh, Rl
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg);
 
   // swap Rh
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstHiReg, getKillRegState(DstIsKill));
 
   // andi Rh, 0xf0
   auto MI0 =

   // SREG is implicitly dead.
   MI0->getOperand(3).setIsDead();
 
   // eor Rl, Rh
   auto MI1 =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstLoReg, getKillRegState(DstIsKill))
-          .addReg(DstHiReg, getKillRegState(DstIsKill));
+          .addReg(DstHiReg);
   // SREG is implicitly dead.
   MI1->getOperand(3).setIsDead();
 
   // andi Rh, 0xf
   auto MI2 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, getKillRegState(DstIsKill))
           .addImm(0xf);
   // SREG is implicitly dead.
   MI2->getOperand(3).setIsDead();
 
   // eor Rl, Rh
   auto MI3 =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstLoReg, getKillRegState(DstIsKill))
-          .addReg(DstHiReg, getKillRegState(DstIsKill));
+          .addReg(DstHiReg);
   if (ImpIsDead)
     MI3->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>

   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(2).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // Move upper byte to lower byte.
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg);
 
   // Move the sign bit to the C flag.
   buildMI(MBB, MBBI, AVR::ADDRdRr)
       .addReg(DstHiReg, RegState::Define, getDeadRegState(DstIsDead))
       .addReg(DstHiReg, getKillRegState(DstIsKill) | getDeadRegState(DstIsDead))
       .addReg(DstHiReg, getKillRegState(DstIsKill));
 
   // Set upper byte to 0 or -1.

   bool ImpIsDead = MI.getOperand(2).isDead();
 
   // ror r24
   // clr r24
   // ror r24
 
   buildMI(MBB, MBBI, AVR::RORRd)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, getKillRegState(DstIsKill))
+      ->getOperand(3).setIsUndef(true);
 
   buildMI(MBB, MBBI, AVR::EORRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, getKillRegState(DstIsKill))
       .addReg(DstReg, getKillRegState(DstIsKill));
 
   auto MIRRC =
       buildMI(MBB, MBBI, AVR::RORRd)
           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstReg, getKillRegState(DstIsKill));
 
   if (ImpIsDead)
     MIRRC->getOperand(2).setIsDead();
 
   // SREG is always implicitly killed
   MIRRC->getOperand(3).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::LSRB7Rd>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(2).isDead();
 
   // rol r24
   // clr r24
   // rol r24
 
   buildMI(MBB, MBBI, AVR::ADCRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, getKillRegState(DstIsKill))
+      ->getOperand(4).setIsUndef(true);
 
   buildMI(MBB, MBBI, AVR::EORRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, getKillRegState(DstIsKill))
       .addReg(DstReg, getKillRegState(DstIsKill));
 
   auto MIRRC =
       buildMI(MBB, MBBI, AVR::ADCRdRr)
           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstReg, getKillRegState(DstIsKill))
           .addReg(DstReg, getKillRegState(DstIsKill));
 
   if (ImpIsDead)
     MIRRC->getOperand(3).setIsDead();
 
   // SREG is always implicitly killed
   MIRRC->getOperand(4).setIsKill();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::ASRB7Rd>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   bool DstIsKill = MI.getOperand(1).isKill();
   bool ImpIsDead = MI.getOperand(2).isDead();
 

   if (SrcReg != DstLoReg) {
     buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(SrcReg, getKillRegState(SrcIsKill));
   }
 
   auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-    .addReg(DstHiReg, RegState::Kill)
-    .addReg(DstHiReg, RegState::Kill);
+    .addReg(DstHiReg, RegState::Kill | RegState::Undef)
+    .addReg(DstHiReg, RegState::Kill | RegState::Undef);
 
   if (ImpIsDead)
     EOR->getOperand(3).setIsDead();
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
   unsigned Flags = MI.getFlags();
   unsigned OpLo = AVR::INRdA;
   unsigned OpHi = AVR::INRdA;
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // Low part
   buildMI(MBB, MBBI, OpLo)
     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
     .addImm(0x3d)
     .setMIFlags(Flags);
 
   // High part
   buildMI(MBB, MBBI, OpHi)

llvm/lib/Target/AVR/AVRFrameLowering.cpp

if (Opcode == TII.getCallFrameSetupOpcode()) {
       // values, etc) is tricky and thus left to be optimized in the future.
       BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
 
       MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(AVR::SUBIWRdK), AVR::R31R30)
                               .addReg(AVR::R31R30, RegState::Kill)
                               .addImm(Amount);
       New->getOperand(3).setIsDead();
 
       BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
-          .addReg(AVR::R31R30, RegState::Kill);
+          .addReg(AVR::R31R30);
 
       // Make sure the remaining stack stores are converted to real store
       // instructions.
       fixStackStores(MBB, MI, TII, AVR::R31R30);
     } else {
       assert(Opcode == TII.getCallFrameDestroyOpcode());
 
       // Note that small stack changes could be implemented more efficiently

llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit add with carry pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_adcwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_adcwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20, $sreg
 
     ; CHECK-LABEL: test_adcwrdrr
 
     ; CHECK:       $r14 = ADCRdRr $r14, $r20, implicit-def $sreg, implicit $sreg
     ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = ADCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit add pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_addwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_addwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_addwrdrr
 
     ; CHECK:       $r14 = ADDRdRr $r14, $r20, implicit-def $sreg
     ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = ADDWRdRr $r15r14, $r21r20, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit ANDO pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_andiwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_andiwrdrr
 body: |
   bb.0.entry:
+    liveins: $r17r16
 
     ; CHECK-LABEL: test_andiwrdrr
 
     ; CHECK:      $r16 = ANDIRdK $r16, 175, implicit-def dead $sreg
     ; CHECK-NEXT: $r17 = ANDIRdK $r17, 250, implicit-def $sreg
 
     $r17r16 = ANDIWRdK $r17r16, 64175, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit AND pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_andwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_andwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_andwrdrr
 
     ; CHECK:      $r14 = ANDRdRr $r14, $r20, implicit-def dead $sreg
     ; CHECK-NEXT: $r15 = ANDRdRr $r15, $r21, implicit-def $sreg
 
     $r15r14 = ANDWRdRr $r15r14, $r21r20, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test
 
     ; CHECK:      $r15 = ASRRd $r15, implicit-def $sreg
     ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = ASRWRd $r15r14, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/COMWRd.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit COM pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_comwrd() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_comwrd
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test_comwrd
 
     ; CHECK:      $r14 = COMRd $r14, implicit-def dead $sreg
     ; CHECK-NEXT: $r15 = COMRd $r15, implicit-def $sreg
 
     $r15r14 = COMWRd $r15r14, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit CPCW pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_cpcwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_cpcwrdrr
 body: |
   bb.0.entry:
+    liveins: $r21r20, $r23r22, $sreg
 
     ; CHECK-LABEL: test_cpcwrdrr
 
     ; CHECK:      CPCRdRr $r20, $r22, implicit-def $sreg, implicit killed $sreg
     ; CHECK-NEXT: CPCRdRr $r21, $r23, implicit-def $sreg, implicit killed $sreg
 
     CPCWRdRr $r21r20, $r23r22, implicit-def $sreg, implicit $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit CPW pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_cpwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_cpwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_cpwrdrr
 
     ; CHECK:      CPRdRr $r14, $r20, implicit-def $sreg
     ; CHECK-NEXT: CPCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
 
     CPWRdRr $r15r14, $r21r20, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit EOR pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_eorwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_eorwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_eorwrdrr
 
     ; CHECK:      $r14 = EORRdRr $r14, $r20, implicit-def dead $sreg
     ; CHECK-NEXT: $r15 = EORRdRr $r15, $r21, implicit-def $sreg
 
     $r15r14 = EORWRdRr $r15r14, $r21r20, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir

 ...
 
 ---
 name:            test
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test
 
     $r29r28 = FRMIDX $r31r30, 0, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir

--- |
   }
 ...
 
 ---
 name:            test_lddwrdptrq
 tracksRegLiveness: true
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_lddwrdptrq
 
     ; CHECK:      ldd     r24, Z+10
     ; CHECK-NEXT: ldd     r25, Z+11
 
     early-clobber $r25r24 = LDDWRdPtrQ undef $r31r30, 10
 ...

llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir

--- |
   }
 ...
 
 ---
 name:            test_ldwrdptr
 tracksRegLiveness: true
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_ldwrdptr
 
     ; CHECK:      ld [[SCRATCH:r[0-9]+]], Z
     ; CHECK-NEXT: push [[SCRATCH]]
     ; CHECK-NEXT: ldd [[SCRATCH]], Z+1
     ; CHECK-NEXT: mov r31, [[SCRATCH]]
     ; CHECK-NEXT: pop r30
 
     early-clobber $r31r30 = LDWRdPtr undef $r31r30
 ...
 

llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_ldwrdptr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_ldwrdptr
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_ldwrdptr
 
     ; CHECK:               $r0 = LDRdPtr $r31r30
     ; CHECK-NEXT:          $r1 = LDDRdPtrQ $r31r30, 1
 
     $r1r0 = LDWRdPtr $r31r30
 ...

llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDWRdPtrPd pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_ldwrdptrpd() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_ldwrdptrpd
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_ldwrdptrpd
 
     ; CHECK:      early-clobber $r1, $r31r30 = LDRdPtrPd killed $r31r30
     ; CHECK-NEXT: early-clobber $r0, $r31r30 = LDRdPtrPd killed $r31r30
 
     $r1r0, $r31r30 = LDWRdPtrPd $r31r30
 ...

llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDWRdPtrPi pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_ldwrdptrpi() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_ldwrdptrpi
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_ldwrdptrpi
 
     ; CHECK:      early-clobber $r0, $r31r30 = LDRdPtrPi killed $r31r30
     ; CHECK-NEXT: early-clobber $r1, $r31r30 = LDRdPtrPi killed $r31r30
 
     $r1r0, $r31r30 = LDWRdPtrPi $r31r30
 ...

llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test
 
     ; CHECK:      $r14 = ADDRdRr $r14, $r14, implicit-def $sreg
     ; CHECK-NEXT: $r15 = ADCRdRr $r15, $r15, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = LSLWRd $r15r14, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test
 
     ; CHECK:      $r15 = LSRRd $r15, implicit-def $sreg
     ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = LSRWRd $r15r14, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit NEG pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_negwrd() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_negwrd
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test_negwrd
 
     ; CHECK:      $r15 = NEGRd $r15, implicit-def dead $sreg
     ; CHECK-NEXT: $r14 = NEGRd $r14
     ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r1, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = NEGWRd $r15r14, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit OR pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_oriwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_oriwrdrr
 body: |
   bb.0.entry:
+    liveins: $r21r20
 
     ; CHECK-LABEL: test_oriwrdrr
 
     ; CHECK:      $r20 = ORIRdK $r20, 175, implicit-def dead $sreg
     ; CHECK-NEXT: $r21 = ORIRdK $r21, 250, implicit-def $sreg
 
     $r21r20 = ORIWRdK $r21r20, 64175, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit OR pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_orwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_orwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_orwrdrr
 
     ; CHECK:      $r14 = ORRdRr $r14, $r20, implicit-def dead $sreg
     ; CHECK-NEXT: $r15 = ORRdRr $r15, $r21, implicit-def $sreg
 
     $r15r14 = ORWRdRr $r15r14, $r21r20, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test
 
     ; CHECK:      OUTARr 32, $r15
     ; CHECK-NEXT: OUTARr 31, $r14
 
     OUTWARr 31, $r15r14
 ...

llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_sbciwrdk() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_sbciwrdk
 body: |
   bb.0.entry:
+    liveins: $r21r20, $sreg
 
     ; CHECK-LABEL: test_sbciwrdk
 
     ; CHECK:      $r20 = SBCIRdK $r20, 175, implicit-def $sreg, implicit killed $sreg
     ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
 
     $r21r20 = SBCIWRdK $r21r20, 64175, implicit-def $sreg, implicit $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_sbcwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_sbcwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20, $sreg
 
     ; CHECK-LABEL: test_sbcwrdrr
 
     ; CHECK:      $r14 = SBCRdRr $r14, $r20, implicit-def $sreg
     ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = SBCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/SEXT.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r31
 
     ; CHECK-LABEL: test
 
     ; CHECK:      $r14 = MOVRdRr $r31
     ; CHECK-NEXT: $r15 = MOVRdRr $r31
     ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
     ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = SEXT $r31, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_stswkrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_stswkrr
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_stswkrr
 
     ; CHECK:      STSKRr 2560, $r31
     ; CHECK-NEXT: STSKRr 2559, $r30
 
     STSWKRr 2559, $r31r30
 ...

llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test
 
     ; CHECK:      early-clobber $r31r30 = STPtrPdRr killed $r31r30, $r29, 52
     ; CHECK-NEXT: early-clobber $r31r30 = STPtrPdRr killed $r31r30, $r28, 52
 
     $r31r30 = STWPtrPdRr $r31r30, $r29r28, 52
 ...

llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test
 
     ; CHECK:      early-clobber $r31r30 = STPtrPiRr killed $r31r30, $r28, 52
     ; CHECK-NEXT: early-clobber $r31r30 = STPtrPiRr killed $r31r30, $r29, 52
 
     $r31r30 = STWPtrPiRr $r31r30, $r29r28, 52
 ...

llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_stwptrrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_stwptrrr
 body: |
   bb.0.entry:
+    liveins: $r31r30, $r17r16
 
     ; CHECK-LABEL: test_stwptrrr
 
     ; CHECK:      STPtrRr $r31r30, $r16
     ; CHECK-NEXT: STDPtrQRr $r31r30, 1, $r17
 
     STWPtrRr $r31r30, $r17r16
 ...

llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_subiwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_subiwrdrr
 body: |
   bb.0.entry:
+    liveins: $r21r20
 
     ; CHECK-LABEL: test_subiwrdrr
 
     ; CHECK:      $r20 = SUBIRdK $r20, 175, implicit-def $sreg
     ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
 
     $r21r20 = SUBIWRdK $r21r20, 64175, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction pseudo instruction.
 
 --- |
   target triple = "avr--"
   define void @test_subwrdrr() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_subwrdrr
 body: |
   bb.0.entry:
+    liveins: $r21r20, $r15r14
 
     ; CHECK-LABEL: test_subwrdrr
 
     ; CHECK:      $r14 = SUBRdRr $r14, $r20, implicit-def $sreg
     ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = SUBWRdRr $r15r14, $r21r20, implicit-def $sreg
 ...

llvm/test/CodeGen/AVR/pseudo/ZEXT.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r31
 
     ; CHECK-LABEL: test
 
     ; CHECK:      $r14 = MOVRdRr $r31
     ; CHECK-NEXT: $r15 = MOVRdRr $r31
     ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
     ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = SEXT $r31, implicit-def $sreg
 ...