[LLDB] Arm64/Linux test case for MTE and Pointer Authentication regset

[omjavaid]

Summary

This patch adds a test case to test dynamic register sets. This tests for the availability of certain register sets and query their registers accordingly.

[DavidSpickett]

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

36

Can you explain the logic for the values here?

40

You don't need the brackets around i for % (i).

50

Is it slightly more strict if we have one loop that reads then writes?

for i in range(32):
   write
   read

Since we write the same value, if you write them all then read them all you aren't totally sure that each one is lined up right. Then again I'm sure you've tested sve register writes elsewhere.

Anyway, a single loop for each would be a bit neater.

112

If you move all this code from after the for, into the for loop, you could skip having the bools per register set.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c

15

(I'm not familiar with SVE assembly but anyway..)

Is the .b/.h/.s etc. pattern specific or does it not matter?

32–33

Same here, is the p0/p5/p10/p15 pattern affecting values used in the test or just for fun? (which isn't a bad thing)

69

This appears to be defined but not set.

74

Should there be a #ifndef HWCAP_SVE above too?

83

Would be neat to do these vars like:

unsigned int mte_is_enabled = hwcap2 & HWCAP2_MTE;

[omjavaid]

We are using SVE read/write in this test to make sure we do not overlap register offsets while calculating offsets for the dynamic registers. Further dynamic register sets should also be readable.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

36

P reg sets predicate lanes. P0 will have all lanes set while P5 will have no lanes set. These are just random values testing read/write.

40

Ack.

50

I think you are right. If we do a read after write in a single loop we ll be doing 64 ptrace calls on lldb-server side. More the better.

112

I was actually trying to see whether what cpuinfo reports and what is reported by prctl is same or not.
I am going to revisit this piece and adjust.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c

15

Replied in comment below.

32–33

I copied this from SVE test case that I wrote last year.

P is a predicate register and ptrue/pfalse instruction is used to set a predicate lane with a pattern. pattern is decide based on size specifier, b, h, s and d.

if size specified is b all lanes will be set to 1. which is needed to set al bytes in a Z registers to the specified value.

We are setting p0, p5, p10 and p15 to enable all lanes other p registers are not enabling all lanes thats why they were not used as predicate for setting Z registers in following lines which set a constant value to Z register byte size elements.

69

Ack. I ll adjust these as per your suggestion below.

74

Most distros have now backported ptrace.h to include HWCAP_SVE but other two are still in the process.

83

Cool!

[DavidSpickett]

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

36

I would put that in a comment to save some time for those unfamiliar with SVE.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c

32–33

I'd put that in a comment. Enough for someone triaging a failure to know what's arbitrary numbers and what's very specific.

[omjavaid]

Review comments resolved.

[DavidSpickett]

Some python nits otherwise the test looks good.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

17

These messages are printed on assert failure. So this one would be "Expected a register named...".

33

For this and the other instances of this pattern you an make it one string like:

self.expect("register read z%i" % i, ...

46

Do we need an ffr read if we have a read/write below?

95

These if not could be self.assertFalse.

[omjavaid]

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

17

Agreed.

33

I am kinda old school so choose to write + will fix :)

46

Yes.
There are two values which are being verified:
First we verify value that was written by our assembly code.
After that we use debugger to write and read back values.

95

Yes self.assertTrue I guess. Will fix.

[DavidSpickett]

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

46

Ok but then should the second r/w be of a different value?

program writes A - we read A, so the read works
we write A - we read A, was that our A or the program's A?

[omjavaid]

Minor fix to write unique value to all z/p registers when writing them using register write command.

[omjavaid]

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

46

Second read/write was different value but a fixed value was being used for testing all z/p registers. I have updated this rev to add unique values which are still different from what is written by the main.c

[DavidSpickett]

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

97

Move the closing ) onto the first line. Also I'd indent the line below like:

self.assertTrue(self.isAArch64SVE(), 
    'LLDB enabled AArch64 SVE register set when it was disabled by target.')
self.....

(applies to the next two as well)

107

Should be isAArch64PAuth

lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c

82–83

These are unused since we get it from the cpuinfo, then you can inline the sve check in the if below.

[omjavaid]

fixes review comments.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

97

Ack.

107

Ack.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c

82–83

Ack.

[DavidSpickett]

Did you forget to add the changes? I don't see any diff for the last update.

[omjavaid]

FIxes stale diff uploaded by mistake.

[omjavaid]

In D96463#2613498, @DavidSpickett wrote:

Did you forget to add the changes? I don't see any diff for the last update.

Sorry about that. Check the latest diff should be fixed now.

[DavidSpickett]

LGTM with that one thing fixed.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c

5–11

These can go too.

[omjavaid]

Rebased.

[labath]

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

59–60

I find this combination of %-formatting and string concatenation unsettling. Just use % for the whole string?

lldb/packages/Python/lldbsuite/test/lldbtest.py

class Base(unittest2.TestCase):
 
     def isPPC64le(self):
         """Returns true if the architecture is PPC64LE."""
         arch = self.getArchitecture()
         if re.match("powerpc64le", arch):
             return True
         return False
 
-    def isAArch64SVE(self):
+    def getCPUInfo(self):
         triple = self.dbg.GetSelectedPlatform().GetTriple()
 
         # TODO other platforms, please implement this function
         if not re.match(".*-.*-linux", triple):
             return False
 
         # Need to do something different for non-Linux/Android targets
         cpuinfo_path = self.getBuildArtifact("cpuinfo")
         if configuration.lldb_platform_name:
             self.runCmd('platform get-file "/proc/cpuinfo" ' + cpuinfo_path)
         else:
             cpuinfo_path = "/proc/cpuinfo"
 
         try:
             f = open(cpuinfo_path, 'r')
             cpuinfo = f.read()
             f.close()
         except:
             return False
 
-        return " sve " in cpuinfo
+        return cpuinfo
+
+    def isAArch64SVE(self):
+        return "sve" in self.getCPUInfo()
+
+    def isAArch64MTE(self):
+        return "mte" in self.getCPUInfo()
+
+    def isAArch64PAuth(self):
+        return "paca" in self.getCPUInfo()
 
     def hasLinuxVmFlags(self):
         """ Check that the target machine has "VmFlags" lines in
         its /proc/{pid}/smaps files."""
 
         triple = self.dbg.GetSelectedPlatform().GetTriple()
         if not re.match(".*-.*-linux", triple):
             return False

lldb/test/API/commands/register/register/aarch64_dynamic_regset/Makefile

+C_SOURCES := main.c
+
+CFLAGS_EXTRAS := -march=armv8-a+sve
+
+include Makefile.rules

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

+"""
+Test AArch64 dynamic register sets
+"""
+
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class RegisterCommandsTestCase(TestBase):
+
+    def check_sve_register_size(self, set, name, expected):
+        reg_value = set.GetChildMemberWithName(name)
+        self.assertTrue(reg_value.IsValid(),
+                        'Expected a register named %s' % (name))
+        self.assertEqual(reg_value.GetByteSize(), expected,
+                         'Expected a register %s size == %i bytes' % (name, expected))
+
+    def sve_regs_read_dynamic(self, sve_registers):
+        vg_reg = sve_registers.GetChildMemberWithName("vg")
+        vg_reg_value = sve_registers.GetChildMemberWithName(
+            "vg").GetValueAsUnsigned()
+
+        z_reg_size = vg_reg_value * 8
+        p_reg_size = int(z_reg_size / 8)
+
+        for i in range(32):
+            z_regs_value = '{' + \
+                ' '.join('0x{:02x}'.format(i + 1)
+                         for _ in range(z_reg_size)) + '}'
+            self.expect('register read z%i' %
+                        (i), substrs=[z_regs_value])
+
+        # Set P registers with random test values. The P registers are predicate
+        # registers, which hold one bit for each byte available in a Z register.
+        # For below mentioned values of P registers, P(0,5,10,15) will have all
+        # Z register lanes set while P(4,9,14) will have no lanes set.
+        p_value_bytes = ['0xff', '0x55', '0x11', '0x01', '0x00']
+        for i in range(16):
+            p_regs_value = '{' + \
+                ' '.join(p_value_bytes[i % 5] for _ in range(p_reg_size)) + '}'
+            self.expect('register read p%i' % (i), substrs=[p_regs_value])
+
+        self.expect("register read ffr", substrs=[p_regs_value])
+
+        for i in range(32):
+            z_regs_value = '{' + \
+                ' '.join('0x{:02x}'.format(32 - i)
+                         for _ in range(z_reg_size)) + '}'
+            self.runCmd('register write z%i' %
+                        (i) + " '" + z_regs_value + "'")
+            self.expect('register read z%i' % (i), substrs=[z_regs_value])
+
+        for i in range(16):
+            p_regs_value = '{' + \
+                ' '.join('0x{:02x}'.format(16 - i)
+                         for _ in range(p_reg_size)) + '}'
+            self.runCmd('register write p%i' %
+                        (i) + " '" + p_regs_value + "'")
+            self.expect('register read p%i' % (i), substrs=[p_regs_value])
+
+        p_regs_value = '{' + \
+            ' '.join('0x{:02x}'.format(8)
+                     for _ in range(p_reg_size)) + '}'
+        self.runCmd('register write ffr ' + "'" + p_regs_value + "'")
+        self.expect('register read ffr', substrs=[p_regs_value])
+
+    mydir = TestBase.compute_mydir(__file__)
+
+    @no_debug_info_test
+    @skipIf(archs=no_match(["aarch64"]))
+    @skipIf(oslist=no_match(['linux']))
+    def test_aarch64_dynamic_regset_config(self):
+        """Test AArch64 Dynamic Register sets configuration."""
+        self.build()
+        self.line = line_number('main.c', '// Set a break point here.')
+
+        exe = self.getBuildArtifact("a.out")
+        self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+        lldbutil.run_break_set_by_file_and_line(
+            self, "main.c", self.line, num_expected_locations=1)
+        self.runCmd("run", RUN_SUCCEEDED)
+
+        self.expect("thread backtrace", STOPPED_DUE_TO_BREAKPOINT,
+                    substrs=["stop reason = breakpoint 1."])
+
+        target = self.dbg.GetSelectedTarget()
+        process = target.GetProcess()
+        thread = process.GetThreadAtIndex(0)
+        currentFrame = thread.GetFrameAtIndex(0)
+
+        for registerSet in currentFrame.GetRegisters():
+            if 'Scalable Vector Extension Registers' in registerSet.GetName():
+                self.assertTrue(self.isAArch64SVE(),
+                    'LLDB enabled AArch64 SVE register set when it was disabled by target.')
+                self.sve_regs_read_dynamic(registerSet)
+            if 'MTE Control Register' in registerSet.GetName():
+                self.assertTrue(self.isAArch64MTE(),
+                    'LLDB enabled AArch64 MTE register set when it was disabled by target.')
+                self.runCmd("register write mte_ctrl 0x7fff9")
+                self.expect("register read mte_ctrl",
+                            substrs=['mte_ctrl = 0x000000000007fff9'])
+            if 'Pointer Authentication Registers' in registerSet.GetName():
+                self.assertTrue(self.isAArch64PAuth(),
+                    'LLDB enabled AArch64 Pointer Authentication register set when it was disabled by target.')
+                self.expect("register read data_mask",
+                            substrs=['data_mask = 0x'])
+                self.expect("register read code_mask",
+                            substrs=['code_mask = 0x'])

lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c

+#include <sys/auxv.h>
+
+void set_sve_registers() {
+  // AArch64 SVE extension ISA adds a new set of vector and predicate registers:
+  // 32 Z registers, 16 P registers, and 1 FFR register.
+  // Code below populates SVE registers to be read back by the debugger via
+  // ptrace interface at runtime.
+  // The P registers are predicate registers and hold one bit for each byte
+  // available in a Z vector register. For example, an SVE implementation with
+  // 1024-bit Z registers has 128-bit predicate registers.
+  // ptrue/pfalse instruction is used to set a predicate lane with a pattern.
+  // pattern is decided based on size specifier, b, h, s and d. if size
+  // specified is b all lanes will be set to 1. which is needed to set all bytes
+  // in a Z registers to the specified value.
+  asm volatile("setffr\n\t");
+  asm volatile("ptrue p0.b\n\t");
+  asm volatile("ptrue p1.h\n\t");
+  asm volatile("ptrue p2.s\n\t");
+  asm volatile("ptrue p3.d\n\t");
+  asm volatile("pfalse p4.b\n\t");
+  asm volatile("ptrue p5.b\n\t");
+  asm volatile("ptrue p6.h\n\t");
+  asm volatile("ptrue p7.s\n\t");
+  asm volatile("ptrue p8.d\n\t");
+  asm volatile("pfalse p9.b\n\t");
+  asm volatile("ptrue p10.b\n\t");
+  asm volatile("ptrue p11.h\n\t");
+  asm volatile("ptrue p12.s\n\t");
+  asm volatile("ptrue p13.d\n\t");
+  asm volatile("pfalse p14.b\n\t");
+  asm volatile("ptrue p15.b\n\t");
+
+  asm volatile("cpy  z0.b, p0/z, #1\n\t");
+  asm volatile("cpy  z1.b, p5/z, #2\n\t");
+  asm volatile("cpy  z2.b, p10/z, #3\n\t");
+  asm volatile("cpy  z3.b, p15/z, #4\n\t");
+  asm volatile("cpy  z4.b, p0/z, #5\n\t");
+  asm volatile("cpy  z5.b, p5/z, #6\n\t");
+  asm volatile("cpy  z6.b, p10/z, #7\n\t");
+  asm volatile("cpy  z7.b, p15/z, #8\n\t");
+  asm volatile("cpy  z8.b, p0/z, #9\n\t");
+  asm volatile("cpy  z9.b, p5/z, #10\n\t");
+  asm volatile("cpy  z10.b, p10/z, #11\n\t");
+  asm volatile("cpy  z11.b, p15/z, #12\n\t");
+  asm volatile("cpy  z12.b, p0/z, #13\n\t");
+  asm volatile("cpy  z13.b, p5/z, #14\n\t");
+  asm volatile("cpy  z14.b, p10/z, #15\n\t");
+  asm volatile("cpy  z15.b, p15/z, #16\n\t");
+  asm volatile("cpy  z16.b, p0/z, #17\n\t");
+  asm volatile("cpy  z17.b, p5/z, #18\n\t");
+  asm volatile("cpy  z18.b, p10/z, #19\n\t");
+  asm volatile("cpy  z19.b, p15/z, #20\n\t");
+  asm volatile("cpy  z20.b, p0/z, #21\n\t");
+  asm volatile("cpy  z21.b, p5/z, #22\n\t");
+  asm volatile("cpy  z22.b, p10/z, #23\n\t");
+  asm volatile("cpy  z23.b, p15/z, #24\n\t");
+  asm volatile("cpy  z24.b, p0/z, #25\n\t");
+  asm volatile("cpy  z25.b, p5/z, #26\n\t");
+  asm volatile("cpy  z26.b, p10/z, #27\n\t");
+  asm volatile("cpy  z27.b, p15/z, #28\n\t");
+  asm volatile("cpy  z28.b, p0/z, #29\n\t");
+  asm volatile("cpy  z29.b, p5/z, #30\n\t");
+  asm volatile("cpy  z30.b, p10/z, #31\n\t");
+  asm volatile("cpy  z31.b, p15/z, #32\n\t");
+}
+
+int main() {
+  if (getauxval(AT_HWCAP) & HWCAP_SVE) // check if SVE is present
+    set_sve_registers();
+
+  return 0; // Set a break point here.
+}