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Differential D96296

[AArch64][GlobalISel] Allow vector load legalization into 128-bit-wide types
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Authored by paquette on Feb 8 2021, 2:38 PM.

Details

Reviewers
aemerson
Commits
rG0e85d6348653: [AArch64][GlobalISel] Allow vector load legalization into 128-bit-wide types
Summary

Similar to 3d25fdc5c21f174d38ac78dd01ccaf6eec655bc0

This fixes bad codegen in cases like so:

https://godbolt.org/z/hePhz1

Diff Detail

Event Timeline

paquette created this revision.Feb 8 2021, 2:38 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald TranscriptFeb 8 2021, 2:38 PM
paquette requested review of this revision.Feb 8 2021, 2:38 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 8 2021, 2:38 PM
aemerson accepted this revision.Feb 9 2021, 10:18 AM

LGTM.

This revision is now accepted and ready to land.Feb 9 2021, 10:18 AM
Closed by commit rG0e85d6348653: [AArch64][GlobalISel] Allow vector load legalization into 128-bit-wide types (authored by paquette). · Explain WhyFeb 9 2021, 1:43 PM
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG0e85d6348653: [AArch64][GlobalISel] Allow vector load legalization into 128-bit-wide types.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
6 lines
test/
CodeGen/
AArch64/
GlobalISel/
96 lines

Diff 322491

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 287 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder(G_LOAD)
.legalForTypesWithMemDesc({{s32, p0, 8, 8}, {s32, p0, 16, 8}}) .legalForTypesWithMemDesc({{s32, p0, 8, 8}, {s32, p0, 16, 8}})
.clampScalar(0, s8, s64) .clampScalar(0, s8, s64)
.lowerIfMemSizeNotPow2() .lowerIfMemSizeNotPow2()
// Lower any any-extending loads left into G_ANYEXT and G_LOAD // Lower any any-extending loads left into G_ANYEXT and G_LOAD
.lowerIf([=](const LegalityQuery &Query) { .lowerIf([=](const LegalityQuery &Query) {
return Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits; return Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits;
}) })
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.clampMaxNumElements(0, s32, 2) .clampMaxNumElements(0, s8, 16)
.clampMaxNumElements(0, s64, 1) .clampMaxNumElements(0, s16, 8)
.clampMaxNumElements(0, s32, 4)
.clampMaxNumElements(0, s64, 2)
.customIf(IsPtrVecPred); .customIf(IsPtrVecPred);
getActionDefinitionsBuilder(G_STORE) getActionDefinitionsBuilder(G_STORE)
.legalForTypesWithMemDesc({{s8, p0, 8, 8}, .legalForTypesWithMemDesc({{s8, p0, 8, 8},
{s16, p0, 16, 8}, {s16, p0, 16, 8},
{s32, p0, 8, 8}, {s32, p0, 8, 8},
{s32, p0, 16, 8}, {s32, p0, 16, 8},
{s32, p0, 32, 8}, {s32, p0, 32, 8},
▲ Show 20 Lines • Show All 631 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

Show First 20 Lines • Show All 389 Lines • ▼ Show 20 Lines bb.1:
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
; CHECK: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store 16 + 16) ; CHECK: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store 16 + 16)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%val:_(<4 x s64>) = G_IMPLICIT_DEF %val:_(<4 x s64>) = G_IMPLICIT_DEF
%ptr:_(p0) = COPY $x0 %ptr:_(p0) = COPY $x0
G_STORE %val(<4 x s64>), %ptr(p0) :: (store 32) G_STORE %val(<4 x s64>), %ptr(p0) :: (store 32)
RET_ReallyLR RET_ReallyLR
...
---
name: load_32xs8
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: load_32xs8
; CHECK: liveins: $x0
; CHECK: %ptr:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD %ptr(p0) :: (load 16, align 32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[PTR_ADD]](p0) :: (load 16 + 16)
; CHECK: G_STORE [[LOAD]](<16 x s8>), %ptr(p0) :: (store 16, align 32)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
; CHECK: G_STORE [[LOAD1]](<16 x s8>), [[PTR_ADD1]](p0) :: (store 16 + 16)
; CHECK: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<32 x s8>) = G_LOAD %ptr(p0) :: (load 32)
G_STORE %val(<32 x s8>), %ptr(p0) :: (store 32)
RET_ReallyLR
...
---
name: load_16xs16
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: load_16xs16
; CHECK: liveins: $x0
; CHECK: %ptr:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD %ptr(p0) :: (load 16, align 32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load 16 + 16)
; CHECK: G_STORE [[LOAD]](<8 x s16>), %ptr(p0) :: (store 16, align 32)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
; CHECK: G_STORE [[LOAD1]](<8 x s16>), [[PTR_ADD1]](p0) :: (store 16 + 16)
; CHECK: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<16 x s16>) = G_LOAD %ptr(p0) :: (load 32)
G_STORE %val(<16 x s16>), %ptr(p0) :: (store 32)
RET_ReallyLR
...
---
name: load_8xs32
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: load_8xs32
; CHECK: liveins: $x0
; CHECK: %ptr:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD %ptr(p0) :: (load 16, align 32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p0) :: (load 16 + 16)
; CHECK: G_STORE [[LOAD]](<4 x s32>), %ptr(p0) :: (store 16, align 32)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
; CHECK: G_STORE [[LOAD1]](<4 x s32>), [[PTR_ADD1]](p0) :: (store 16 + 16)
; CHECK: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<8 x s32>) = G_LOAD %ptr(p0) :: (load 32)
G_STORE %val(<8 x s32>), %ptr(p0) :: (store 32)
RET_ReallyLR
...
---
name: load_4xs64
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: load_4xs64
; CHECK: liveins: $x0
; CHECK: %ptr:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr(p0) :: (load 16, align 32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load 16 + 16)
; CHECK: G_STORE [[LOAD]](<2 x s64>), %ptr(p0) :: (store 16, align 32)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
; CHECK: G_STORE [[LOAD1]](<2 x s64>), [[PTR_ADD1]](p0) :: (store 16 + 16)
; CHECK: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<4 x s64>) = G_LOAD %ptr(p0) :: (load 32)
G_STORE %val(<4 x s64>), %ptr(p0) :: (store 32)
RET_ReallyLR