AMDGPU: Fix verifier error with argument passed in CSR SGPR

[arsenm]

Summary

We need to avoid setting the kill flag on the CSR spill if there's an
additional use of the register after the spill.

This does rely on consistency between the entry block liveins and the
MRI's function live ins, which is not something the verifier checks
now.

[rampitec]

LGTM

[arsenm]

f4ca6d8289ef116314d4d5080080907e8cb7342d

llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

static void insertCSRSaves(MachineBasicBlock &SaveBlock,
                            LiveIntervals *LIS) {
   MachineFunction &MF = *SaveBlock.getParent();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 
   MachineBasicBlock::iterator I = SaveBlock.begin();
   if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
+    const MachineRegisterInfo &MRI = MF.getRegInfo();
+
     for (const CalleeSavedInfo &CS : CSI) {
       // Insert the spill to the stack frame.
       MCRegister Reg = CS.getReg();
 
       MachineInstrSpan MIS(I, &SaveBlock);
       const TargetRegisterClass *RC =
         TRI->getMinimalPhysRegClass(Reg, MVT::i32);
 
-      TII.storeRegToStackSlot(SaveBlock, I, Reg, true, CS.getFrameIdx(), RC,
-                              TRI);
+      // If this value was already livein, we probably have a direct use of the
+      // incoming register value, so don't kill at the spill point. This happens
+      // since we pass some special inputs (workgroup IDs) in the callee saved
+      // range.
+      const bool IsLiveIn = MRI.isLiveIn(Reg);
+      TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(),
+                              RC, TRI);
 
       if (LIS) {
         assert(std::distance(MIS.begin(), I) == 1);
         MachineInstr &Inst = *std::prev(I);
 
         LIS->InsertMachineInstrInMaps(Inst);
         LIS->removeAllRegUnitsForPhysReg(Reg);
       }

llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
+
+---
+name: spill_csr_sgpr_argument
+tracksRegLiveness: true
+liveins:
+  - { reg: '$sgpr50' }
+body:             |
+  bb.0:
+    liveins: $sgpr50
+    ; CHECK-LABEL: name: spill_csr_sgpr_argument
+    ; CHECK: liveins: $sgpr50, $vgpr0
+    ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr50, 0, $vgpr0
+    ; CHECK: S_NOP 0, implicit $sgpr50
+    ; CHECK: $sgpr50 = S_MOV_B32 0
+    S_NOP 0, implicit $sgpr50
+    $sgpr50 = S_MOV_B32 0
+
+...