MachineCSE: Add a target query for the LookAheadLimit heurisitic

[• tstellarAMD]

Summary

This heurisitc is used to determine whether or not to CSE physical register defs. My understanding is that this pass will only CSE a physical register def that is within 'LookAheadLimit' instructions of a common expression.

I'm adding a target query for this because the R600 backend needs this LookAheadLimit to be MAX_UINT.

I'm not sure what the original intent of this heuristic was and why the value is 5, so another possibility would be to remove it entirely.

[MatzeB]

Hi Tom,

I don't know the history here, but as this does scan forward for each instruction of the basic block it looks like a way to avoid quadratic runtime behavior for (corner) cases with thousands of instructions in a basic block. I think it is no problem to go to a much higher limit than 5. But why go completely boundless, do you need a guarantee here that the CSE is happening?

• Matthias

[• tstellarAMD]

In D9472#165425, @MatzeB wrote:

Hi Tom,

I don't know the history here, but as this does scan forward for each instruction of the basic block it looks like a way to avoid quadratic runtime behavior for (corner) cases with thousands of instructions in a basic block. I think it is no problem to go to a much higher limit than 5. But why go completely boundless, do you need a guarantee here that the CSE is happening?

Yes, I would like a guarantee that CSE is happening. For AMD GPUs, there is a control register (m0), which is used to clamp memory addresses to avoid out of bound reads and writes. Before each load/store instruction, we emit: s_mov_b32 m0, -1 (-1 disables address clamping) and then rely on MachineCSE to eliminate all the unnecessary moves.

[MatzeB]

In D9472#165495, @tstellarAMD wrote:

In D9472#165425, @MatzeB wrote:

Hi Tom,

I don't know the history here, but as this does scan forward for each instruction of the basic block it looks like a way to avoid quadratic runtime behavior for (corner) cases with thousands of instructions in a basic block. I think it is no problem to go to a much higher limit than 5. But why go completely boundless, do you need a guarantee here that the CSE is happening?

Yes, I would like a guarantee that CSE is happening. For AMD GPUs, there is a control register (m0), which is used to clamp memory addresses to avoid out of bound reads and writes. Before each load/store instruction, we emit: s_mov_b32 m0, -1 (-1 disables address clamping) and then rely on MachineCSE to eliminate all the unnecessary moves.

I assume SelectionDAG CSE isn't enough for you because it does not cover multiple blocks. I'm not happy about the quadratic runtime resulting from an unbounded search, but as this is a target specific option, the patch LGTM.

[hfinkel]

include/llvm/Target/TargetInstrInfo.h

1242

Can we just say something like, "The default lookahead is small to prevent unprofitable quadratic behavior." Next year, no one will know to whom "I" refers without a lot of work ;)

include/llvm/Target/TargetInstrInfo.h

     return false;
   }
 
+  /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
+  /// which is a heuristic used for CSE'ing phys reg defs.
+  virtual unsigned getMachineCSELookAheadLimit () const {
+    // 5 is the value for this heuristic that used to be hard-coded into
+    // the MachineCSE pass.  I have no idea why 5 was choosen.
+    return 5;
+  }
+
 private:
   int CallFrameSetupOpcode, CallFrameDestroyOpcode;
 };

lib/CodeGen/MachineCSE.cpp

     MachineRegisterInfo *MRI;
   public:
     static char ID; // Pass identification
-    MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
+    MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(0), CurrVN(0) {
       initializeMachineCSEPass(*PassRegistry::getPassRegistry());
     }
 

     }
 
   private:
-    const unsigned LookAheadLimit;
+    unsigned LookAheadLimit;
     typedef RecyclingAllocator<BumpPtrAllocator,
         ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
     typedef ScopedHashTable<MachineInstr*, unsigned,

   MRI = &MF.getRegInfo();
   AA = &getAnalysis<AliasAnalysis>();
   DT = &getAnalysis<MachineDominatorTree>();
+  LookAheadLimit = TII->getMachineCSELookAheadLimit();
   return PerformCSE(DT->getRootNode());
 }

lib/Target/R600/SIInstrInfo.h

   bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
                      unsigned Reg, MachineRegisterInfo *MRI) const final;
 
+  unsigned getMachineCSELookAheadLimit() const override { return UINT_MAX; }
+
   bool isSALU(uint16_t Opcode) const {
     return get(Opcode).TSFlags & SIInstrFlags::SALU;
   }