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Differential D93995

[InstSimplify] Fold division by zero to poison
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Authored by nikic on Jan 3 2021, 9:39 AM.

Details

Reviewers
aqjune
spatel
lebedev.ri
Commits
rG766cf7f32e4f: [InstSimplify] Fold division by zero to poison
Summary

Div/rem by zero is immediate undefined behavior and anything goes. Currently we fold it to undef, this patch changes it to fold to poison instead, which is slightly stronger.

Diff Detail

Event Timeline

nikic created this revision.Jan 3 2021, 9:39 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptJan 3 2021, 9:39 AM
nikic requested review of this revision.Jan 3 2021, 9:39 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 3 2021, 9:39 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B83851: Diff 314292.Jan 3 2021, 10:10 AM
aqjune accepted this revision.Jan 3 2021, 11:51 AM

LGTM - Thanks!

This revision is now accepted and ready to land.Jan 3 2021, 11:51 AM
Closed by commit rG766cf7f32e4f: [InstSimplify] Fold division by zero to poison (authored by nikic). · Explain WhyJan 3 2021, 11:54 AM
This revision was automatically updated to reflect the committed changes.
nikic added a commit: rG766cf7f32e4f: [InstSimplify] Fold division by zero to poison.

Revision Contents

PathSize
llvm/
lib/
Analysis/
18 lines
test/
Transforms/
InstCombine/
2 lines
48 lines
11 lines
8 lines
8 lines
2 lines
2 lines
2 lines
2 lines
2 lines
4 lines
InstSimplify/
13 lines
9 lines
10 lines
SLPVectorizer/
X86/
2 lines

Diff 314292

llvm/lib/Analysis/InstructionSimplify.cpp

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} }
/// Check for common or similar folds of integer division or integer remainder. /// Check for common or similar folds of integer division or integer remainder.
/// This applies to all 4 opcodes (sdiv/udiv/srem/urem). /// This applies to all 4 opcodes (sdiv/udiv/srem/urem).
static Value *simplifyDivRem(Value *Op0, Value *Op1, bool IsDiv, static Value *simplifyDivRem(Value *Op0, Value *Op1, bool IsDiv,
const SimplifyQuery &Q) { const SimplifyQuery &Q) {
Type *Ty = Op0->getType(); Type *Ty = Op0->getType();
// X / undef -> undef // X / undef -> poison
// X % undef -> undef // X % undef -> poison
if (Q.isUndefValue(Op1)) if (Q.isUndefValue(Op1))
return Op1; return PoisonValue::get(Ty);
// X / 0 -> undef // X / 0 -> poison
// X % 0 -> undef // X % 0 -> poison
// We don't need to preserve faults! // We don't need to preserve faults!
if (match(Op1, m_Zero())) if (match(Op1, m_Zero()))
return UndefValue::get(Ty); return PoisonValue::get(Ty);
// If any element of a constant divisor fixed width vector is zero or undef, // If any element of a constant divisor fixed width vector is zero or undef
// the whole op is undef. // the behavior is undefined and we can fold the whole op to poison.
auto *Op1C = dyn_cast<Constant>(Op1); auto *Op1C = dyn_cast<Constant>(Op1);
auto *VTy = dyn_cast<FixedVectorType>(Ty); auto *VTy = dyn_cast<FixedVectorType>(Ty);
if (Op1C && VTy) { if (Op1C && VTy) {
unsigned NumElts = VTy->getNumElements(); unsigned NumElts = VTy->getNumElements();
for (unsigned i = 0; i != NumElts; ++i) { for (unsigned i = 0; i != NumElts; ++i) {
Constant *Elt = Op1C->getAggregateElement(i); Constant *Elt = Op1C->getAggregateElement(i);
if (Elt && (Elt->isNullValue() || Q.isUndefValue(Elt))) if (Elt && (Elt->isNullValue() || Q.isUndefValue(Elt)))
return UndefValue::get(Ty); return PoisonValue::get(Ty);
} }
} }
// undef / X -> 0 // undef / X -> 0
// undef % X -> 0 // undef % X -> 0
if (Q.isUndefValue(Op0)) if (Q.isUndefValue(Op0))
return Constant::getNullValue(Ty); return Constant::getNullValue(Ty);
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llvm/test/Transforms/InstCombine/add-shl-sdiv-to-srem.ll

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%rz = add <2 x i64> %sl, %x %rz = add <2 x i64> %sl, %x
ret <2 x i64> %rz ret <2 x i64> %rz
} }
; Vectors with undef values ; Vectors with undef values
define <3 x i8> @add-shl-sdiv-3xi8-undef0(<3 x i8> %x) { define <3 x i8> @add-shl-sdiv-3xi8-undef0(<3 x i8> %x) {
; CHECK-LABEL: @add-shl-sdiv-3xi8-undef0( ; CHECK-LABEL: @add-shl-sdiv-3xi8-undef0(
; CHECK-NEXT: ret <3 x i8> [[X:%.*]] ; CHECK-NEXT: ret <3 x i8> poison
; ;
%sd = sdiv <3 x i8> %x, <i8 -4, i8 undef, i8 -4> %sd = sdiv <3 x i8> %x, <i8 -4, i8 undef, i8 -4>
%sl = shl <3 x i8> %sd, <i8 2, i8 2, i8 2> %sl = shl <3 x i8> %sd, <i8 2, i8 2, i8 2>
%rz = add <3 x i8> %sl, %x %rz = add <3 x i8> %sl, %x
ret <3 x i8> %rz ret <3 x i8> %rz
} }
define <3 x i8> @add-shl-sdiv-3xi8-undef1(<3 x i8> %x) { define <3 x i8> @add-shl-sdiv-3xi8-undef1(<3 x i8> %x) {
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llvm/test/Transforms/InstCombine/div.ll

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; CHECK-NEXT: ret <2 x i64> [[DIV]] ; CHECK-NEXT: ret <2 x i64> [[DIV]]
; ;
%div = sdiv <2 x i64> %x, <i64 -1, i64 -1> %div = sdiv <2 x i64> %x, <i64 -1, i64 -1>
ret <2 x i64> %div ret <2 x i64> %div
} }
define <2 x i64> @sdiv_by_minus1_vec_undef_elt(<2 x i64> %x) { define <2 x i64> @sdiv_by_minus1_vec_undef_elt(<2 x i64> %x) {
; CHECK-LABEL: @sdiv_by_minus1_vec_undef_elt( ; CHECK-LABEL: @sdiv_by_minus1_vec_undef_elt(
; CHECK-NEXT: ret <2 x i64> undef ; CHECK-NEXT: ret <2 x i64> poison
; ;
%div = sdiv <2 x i64> %x, <i64 -1, i64 undef> %div = sdiv <2 x i64> %x, <i64 -1, i64 undef>
ret <2 x i64> %div ret <2 x i64> %div
} }
define i32 @sdiv_by_sext_minus1(i1 %x, i32 %y) { define i32 @sdiv_by_sext_minus1(i1 %x, i32 %y) {
; CHECK-LABEL: @sdiv_by_sext_minus1( ; CHECK-LABEL: @sdiv_by_sext_minus1(
; CHECK-NEXT: [[DIV:%.*]] = sub i32 0, [[Y:%.*]] ; CHECK-NEXT: [[DIV:%.*]] = sub i32 0, [[Y:%.*]]
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; ;
%neg = sub nsw <2 x i8> zeroinitializer, %x %neg = sub nsw <2 x i8> zeroinitializer, %x
%d = sdiv <2 x i8> %neg, <i8 -128, i8 -128> %d = sdiv <2 x i8> %neg, <i8 -128, i8 -128>
ret <2 x i8> %d ret <2 x i8> %d
} }
define <2 x i8> @sdiv_negated_dividend_constant_divisor_vec_undef(<2 x i8> %x) { define <2 x i8> @sdiv_negated_dividend_constant_divisor_vec_undef(<2 x i8> %x) {
; CHECK-LABEL: @sdiv_negated_dividend_constant_divisor_vec_undef( ; CHECK-LABEL: @sdiv_negated_dividend_constant_divisor_vec_undef(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%neg = sub nsw <2 x i8> zeroinitializer, %x %neg = sub nsw <2 x i8> zeroinitializer, %x
%d = sdiv <2 x i8> %neg, <i8 -128, i8 undef> %d = sdiv <2 x i8> %neg, <i8 -128, i8 undef>
ret <2 x i8> %d ret <2 x i8> %d
} }
define <2 x i64> @sdiv_negated_dividend_constant_divisor_vec(<2 x i64> %x) { define <2 x i64> @sdiv_negated_dividend_constant_divisor_vec(<2 x i64> %x) {
; CHECK-LABEL: @sdiv_negated_dividend_constant_divisor_vec( ; CHECK-LABEL: @sdiv_negated_dividend_constant_divisor_vec(
; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i64> [[X:%.*]], <i64 -3, i64 -4> ; CHECK-NEXT: [[DIV1_NEG:%.*]] = sdiv <2 x i64> [[X:%.*]], <i64 -3, i64 -4>
; CHECK-NEXT: ret <2 x i64> [[DIV]] ; CHECK-NEXT: ret <2 x i64> [[DIV1_NEG]]
; ;
%neg = sub nsw <2 x i64> zeroinitializer, %x %neg = sub nsw <2 x i64> zeroinitializer, %x
%div = sdiv <2 x i64> %neg, <i64 3, i64 4> %div = sdiv <2 x i64> %neg, <i64 3, i64 4>
ret <2 x i64> %div ret <2 x i64> %div
} }
define <2 x i64> @sdiv_exact_negated_dividend_constant_divisor_vec(<2 x i64> %x) { define <2 x i64> @sdiv_exact_negated_dividend_constant_divisor_vec(<2 x i64> %x) {
; CHECK-LABEL: @sdiv_exact_negated_dividend_constant_divisor_vec( ; CHECK-LABEL: @sdiv_exact_negated_dividend_constant_divisor_vec(
; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i64> [[X:%.*]], <i64 -3, i64 -4> ; CHECK-NEXT: [[DIV1_NEG:%.*]] = sdiv exact <2 x i64> [[X:%.*]], <i64 -3, i64 -4>
; CHECK-NEXT: ret <2 x i64> [[DIV]] ; CHECK-NEXT: ret <2 x i64> [[DIV1_NEG]]
; ;
%neg = sub nsw <2 x i64> zeroinitializer, %x %neg = sub nsw <2 x i64> zeroinitializer, %x
%div = sdiv exact <2 x i64> %neg, <i64 3, i64 4> %div = sdiv exact <2 x i64> %neg, <i64 3, i64 4>
ret <2 x i64> %div ret <2 x i64> %div
} }
; Can't negate signed min vector element. ; Can't negate signed min vector element.
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%a = mul nuw <2 x i8> %z, %x %a = mul nuw <2 x i8> %z, %x
%b = mul <2 x i8> %z, %y %b = mul <2 x i8> %z, %y
%c = udiv <2 x i8> %a, %b %c = udiv <2 x i8> %a, %b
ret <2 x i8> %c ret <2 x i8> %c
} }
define i32 @test_exact_nsw_exact(i32 %x) { define i32 @test_exact_nsw_exact(i32 %x) {
; CHECK-LABEL: @test_exact_nsw_exact( ; CHECK-LABEL: @test_exact_nsw_exact(
; CHECK-NEXT: [[NEG:%.*]] = sdiv exact i32 [[X:%.*]], -3 ; CHECK-NEXT: [[DIV_NEG:%.*]] = sdiv exact i32 [[X:%.*]], -3
; CHECK-NEXT: ret i32 [[NEG]] ; CHECK-NEXT: ret i32 [[DIV_NEG]]
; ;
%div = sdiv exact i32 %x, 3 %div = sdiv exact i32 %x, 3
%neg = sub nsw i32 0, %div %neg = sub nsw i32 0, %div
ret i32 %neg ret i32 %neg
} }
define <2 x i64> @test_exact_vec(<2 x i64> %x) { define <2 x i64> @test_exact_vec(<2 x i64> %x) {
; CHECK-LABEL: @test_exact_vec( ; CHECK-LABEL: @test_exact_vec(
; CHECK-NEXT: [[NEG:%.*]] = sdiv exact <2 x i64> [[X:%.*]], <i64 -3, i64 -4> ; CHECK-NEXT: [[DIV_NEG:%.*]] = sdiv exact <2 x i64> [[X:%.*]], <i64 -3, i64 -4>
; CHECK-NEXT: ret <2 x i64> [[NEG]] ; CHECK-NEXT: ret <2 x i64> [[DIV_NEG]]
; ;
%div = sdiv exact <2 x i64> %x, <i64 3, i64 4> %div = sdiv exact <2 x i64> %x, <i64 3, i64 4>
%neg = sub nsw <2 x i64> zeroinitializer, %div %neg = sub nsw <2 x i64> zeroinitializer, %div
ret <2 x i64> %neg ret <2 x i64> %neg
} }
; Constant is safe to negate. ; Constant is safe to negate.
define <2 x i8> @negate_sdiv_vec_splat(<2 x i8> %x) { define <2 x i8> @negate_sdiv_vec_splat(<2 x i8> %x) {
; CHECK-LABEL: @negate_sdiv_vec_splat( ; CHECK-LABEL: @negate_sdiv_vec_splat(
; CHECK-NEXT: [[NEG:%.*]] = sdiv <2 x i8> [[X:%.*]], <i8 -42, i8 -42> ; CHECK-NEXT: [[DIV_NEG:%.*]] = sdiv <2 x i8> [[X:%.*]], <i8 -42, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[NEG]] ; CHECK-NEXT: ret <2 x i8> [[DIV_NEG]]
; ;
%div = sdiv <2 x i8> %x, <i8 42, i8 42> %div = sdiv <2 x i8> %x, <i8 42, i8 42>
%neg = sub <2 x i8> zeroinitializer, %div %neg = sub <2 x i8> zeroinitializer, %div
ret <2 x i8> %neg ret <2 x i8> %neg
} }
; Dividing by undef is UB. ; Dividing by undef is UB.
define <2 x i8> @negate_sdiv_vec_undef_elt(<2 x i8> %x) { define <2 x i8> @negate_sdiv_vec_undef_elt(<2 x i8> %x) {
; CHECK-LABEL: @negate_sdiv_vec_undef_elt( ; CHECK-LABEL: @negate_sdiv_vec_undef_elt(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%div = sdiv <2 x i8> %x, <i8 undef, i8 42> %div = sdiv <2 x i8> %x, <i8 undef, i8 42>
%neg = sub <2 x i8> zeroinitializer, %div %neg = sub <2 x i8> zeroinitializer, %div
ret <2 x i8> %neg ret <2 x i8> %neg
} }
; Division by -1 may be UB (if numerator is the signed min val), but div-by-1 can be simplified. ; Division by -1 may be UB (if numerator is the signed min val), but div-by-1 can be simplified.
define <2 x i8> @negate_sdiv_vec_splat_one(<2 x i8> %x) { define <2 x i8> @negate_sdiv_vec_splat_one(<2 x i8> %x) {
; CHECK-LABEL: @negate_sdiv_vec_splat_one( ; CHECK-LABEL: @negate_sdiv_vec_splat_one(
; CHECK-NEXT: [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[X:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[X:%.*]]
; CHECK-NEXT: ret <2 x i8> [[NEG]] ; CHECK-NEXT: ret <2 x i8> [[NEG]]
; ;
%div = sdiv <2 x i8> %x, <i8 1, i8 1> %div = sdiv <2 x i8> %x, <i8 1, i8 1>
%neg = sub <2 x i8> zeroinitializer, %div %neg = sub <2 x i8> zeroinitializer, %div
ret <2 x i8> %neg ret <2 x i8> %neg
} }
; Can't negate signed-min constant, but can convert to a compare.. ; Can't negate signed-min constant, but can convert to a compare..
define <2 x i8> @negate_sdiv_vec_splat_signed_min(<2 x i8> %x) { define <2 x i8> @negate_sdiv_vec_splat_signed_min(<2 x i8> %x) {
; CHECK-LABEL: @negate_sdiv_vec_splat_signed_min( ; CHECK-LABEL: @negate_sdiv_vec_splat_signed_min(
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 -128, i8 -128> ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 -128, i8 -128>
; CHECK-NEXT: [[NEG:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i8> ; CHECK-NEXT: [[DIV_NEG:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[NEG]] ; CHECK-NEXT: ret <2 x i8> [[DIV_NEG]]
; ;
%div = sdiv <2 x i8> %x, <i8 -128, i8 -128> %div = sdiv <2 x i8> %x, <i8 -128, i8 -128>
%neg = sub <2 x i8> zeroinitializer, %div %neg = sub <2 x i8> zeroinitializer, %div
ret <2 x i8> %neg ret <2 x i8> %neg
} }
; Division by -1 may be UB for any element of a vector. ; Division by -1 may be UB for any element of a vector.
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; ;
%div = sdiv <2 x i8> %x, <i8 1, i8 -128> %div = sdiv <2 x i8> %x, <i8 1, i8 -128>
%neg = sub <2 x i8> zeroinitializer, %div %neg = sub <2 x i8> zeroinitializer, %div
ret <2 x i8> %neg ret <2 x i8> %neg
} }
define i32 @test_exact_nonsw_exact(i32 %x) { define i32 @test_exact_nonsw_exact(i32 %x) {
; CHECK-LABEL: @test_exact_nonsw_exact( ; CHECK-LABEL: @test_exact_nonsw_exact(
; CHECK-NEXT: [[NEG:%.*]] = sdiv exact i32 [[X:%.*]], -3 ; CHECK-NEXT: [[DIV_NEG:%.*]] = sdiv exact i32 [[X:%.*]], -3
; CHECK-NEXT: ret i32 [[NEG]] ; CHECK-NEXT: ret i32 [[DIV_NEG]]
; ;
%div = sdiv exact i32 %x, 3 %div = sdiv exact i32 %x, 3
%neg = sub i32 0, %div %neg = sub i32 0, %div
ret i32 %neg ret i32 %neg
} }
define i32 @test_exact_nsw_noexact(i32 %x) { define i32 @test_exact_nsw_noexact(i32 %x) {
; CHECK-LABEL: @test_exact_nsw_noexact( ; CHECK-LABEL: @test_exact_nsw_noexact(
; CHECK-NEXT: [[NEG:%.*]] = sdiv i32 [[X:%.*]], -3 ; CHECK-NEXT: [[DIV_NEG:%.*]] = sdiv i32 [[X:%.*]], -3
; CHECK-NEXT: ret i32 [[NEG]] ; CHECK-NEXT: ret i32 [[DIV_NEG]]
; ;
%div = sdiv i32 %x, 3 %div = sdiv i32 %x, 3
%neg = sub nsw i32 0, %div %neg = sub nsw i32 0, %div
ret i32 %neg ret i32 %neg
} }
define i32 @test_exact_nonsw_noexact(i32 %x) { define i32 @test_exact_nonsw_noexact(i32 %x) {
; CHECK-LABEL: @test_exact_nonsw_noexact( ; CHECK-LABEL: @test_exact_nonsw_noexact(
; CHECK-NEXT: [[NEG:%.*]] = sdiv i32 [[X:%.*]], -3 ; CHECK-NEXT: [[DIV_NEG:%.*]] = sdiv i32 [[X:%.*]], -3
; CHECK-NEXT: ret i32 [[NEG]] ; CHECK-NEXT: ret i32 [[DIV_NEG]]
; ;
%div = sdiv i32 %x, 3 %div = sdiv i32 %x, 3
%neg = sub i32 0, %div %neg = sub i32 0, %div
ret i32 %neg ret i32 %neg
} }
define i32 @test_exact_div_nonconst(i32 %x, i32 %y) { define i32 @test_exact_div_nonconst(i32 %x, i32 %y) {
; CHECK-LABEL: @test_exact_div_nonconst( ; CHECK-LABEL: @test_exact_div_nonconst(
Show All 14 Lines;
%div = sdiv exact i32 %x, 1 %div = sdiv exact i32 %x, 1
%neg = sub nsw i32 0, %div %neg = sub nsw i32 0, %div
ret i32 %neg ret i32 %neg
} }
define i8 @test_exact_div_minSigned(i8 %x) { define i8 @test_exact_div_minSigned(i8 %x) {
; CHECK-LABEL: @test_exact_div_minSigned( ; CHECK-LABEL: @test_exact_div_minSigned(
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X:%.*]], -128 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X:%.*]], -128
; CHECK-NEXT: [[NEG:%.*]] = sext i1 [[TMP1]] to i8 ; CHECK-NEXT: [[DIV_NEG:%.*]] = sext i1 [[TMP1]] to i8
; CHECK-NEXT: ret i8 [[NEG]] ; CHECK-NEXT: ret i8 [[DIV_NEG]]
; ;
%div = sdiv exact i8 %x, -128 %div = sdiv exact i8 %x, -128
%neg = sub nsw i8 0, %div %neg = sub nsw i8 0, %div
ret i8 %neg ret i8 %neg
} }
; X / INT_MIN --> X == INT_MIN ; X / INT_MIN --> X == INT_MIN
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; CHECK-NEXT: ret <2 x i8> [[D]] ; CHECK-NEXT: ret <2 x i8> [[D]]
; ;
%d = sdiv <2 x i8> %x, <i8 -128, i8 -128> %d = sdiv <2 x i8> %x, <i8 -128, i8 -128>
ret <2 x i8> %d ret <2 x i8> %d
} }
define <2 x i8> @sdiv_by_int_min_vec_splat_undef(<2 x i8> %x) { define <2 x i8> @sdiv_by_int_min_vec_splat_undef(<2 x i8> %x) {
; CHECK-LABEL: @sdiv_by_int_min_vec_splat_undef( ; CHECK-LABEL: @sdiv_by_int_min_vec_splat_undef(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%d = sdiv <2 x i8> %x, <i8 -128, i8 undef> %d = sdiv <2 x i8> %x, <i8 -128, i8 undef>
ret <2 x i8> %d ret <2 x i8> %d
} }

llvm/test/Transforms/InstCombine/icmp-div-constant.ll

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define i32 @icmp_div(i16 %a, i16 %c) { define i32 @icmp_div(i16 %a, i16 %c) {
; CHECK-LABEL: @icmp_div( ; CHECK-LABEL: @icmp_div(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0
; CHECK-NEXT: br i1 [[TOBOOL]], label [[THEN:%.*]], label [[EXIT:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL]], label [[THEN:%.*]], label [[EXIT:%.*]]
; CHECK: then: ; CHECK: then:
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[C:%.*]], 0 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[C:%.*]], 0
; CHECK-NEXT: [[PHITMP1:%.*]] = sext i1 [[CMP]] to i32 ; CHECK-NEXT: [[PHI_BO:%.*]] = sext i1 [[CMP]] to i32
; CHECK-NEXT: br label [[EXIT]] ; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[PHITMP1]], [[THEN]] ] ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[PHI_BO]], [[THEN]] ]
; CHECK-NEXT: ret i32 [[PHI]] ; CHECK-NEXT: ret i32 [[PHI]]
; ;
entry: entry:
%tobool = icmp eq i16 %a, 0 %tobool = icmp eq i16 %a, 0
br i1 %tobool, label %then, label %exit br i1 %tobool, label %then, label %exit
then: then:
%div = sdiv i16 %c, -1 %div = sdiv i16 %c, -1
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define i32 @icmp_div2(i16 %a, i16 %c) { define i32 @icmp_div2(i16 %a, i16 %c) {
; CHECK-LABEL: @icmp_div2( ; CHECK-LABEL: @icmp_div2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0
; CHECK-NEXT: br i1 [[TOBOOL]], label [[THEN:%.*]], label [[EXIT:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL]], label [[THEN:%.*]], label [[EXIT:%.*]]
; CHECK: then: ; CHECK: then:
; CHECK-NEXT: br label [[EXIT]] ; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ 0, [[THEN]] ] ; CHECK-NEXT: ret i32 -1
; CHECK-NEXT: ret i32 [[PHI]]
; ;
entry: entry:
%tobool = icmp eq i16 %a, 0 %tobool = icmp eq i16 %a, 0
br i1 %tobool, label %then, label %exit br i1 %tobool, label %then, label %exit
then: then:
%div = sdiv i16 %c, 0 %div = sdiv i16 %c, 0
%cmp = icmp ne i16 %div, 0 %cmp = icmp ne i16 %div, 0
br label %exit br label %exit
exit: exit:
%phi = phi i1 [ false, %entry ], [ %cmp, %then ] %phi = phi i1 [ false, %entry ], [ %cmp, %then ]
%zext = zext i1 %phi to i32 %zext = zext i1 %phi to i32
%add = add nsw i32 %zext, -1 %add = add nsw i32 %zext, -1
ret i32 %add ret i32 %add
} }
define i32 @icmp_div3(i16 %a, i16 %c) { define i32 @icmp_div3(i16 %a, i16 %c) {
; CHECK-LABEL: @icmp_div3( ; CHECK-LABEL: @icmp_div3(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[A:%.*]], 0
; CHECK-NEXT: br i1 [[TOBOOL]], label [[THEN:%.*]], label [[EXIT:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL]], label [[THEN:%.*]], label [[EXIT:%.*]]
; CHECK: then: ; CHECK: then:
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[C:%.*]], 0 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[C:%.*]], 0
; CHECK-NEXT: [[PHITMP1:%.*]] = sext i1 [[CMP]] to i32 ; CHECK-NEXT: [[PHI_BO:%.*]] = sext i1 [[CMP]] to i32
; CHECK-NEXT: br label [[EXIT]] ; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[PHITMP1]], [[THEN]] ] ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[PHI_BO]], [[THEN]] ]
; CHECK-NEXT: ret i32 [[PHI]] ; CHECK-NEXT: ret i32 [[PHI]]
; ;
entry: entry:
%tobool = icmp eq i16 %a, 0 %tobool = icmp eq i16 %a, 0
br i1 %tobool, label %then, label %exit br i1 %tobool, label %then, label %exit
then: then:
%div = sdiv i16 %c, 1 %div = sdiv i16 %c, 1
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llvm/test/Transforms/InstCombine/inselt-binop-inseltpoison.ll

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; ;
%ins = insertelement <2 x i8> poison, i8 %x, i32 0 %ins = insertelement <2 x i8> poison, i8 %x, i32 0
%bo = urem <2 x i8> <i8 5, i8 2>, %ins %bo = urem <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @urem_constant_op1(i8 %x) { define <2 x i8> @urem_constant_op1(i8 %x) {
; CHECK-LABEL: @urem_constant_op1( ; CHECK-LABEL: @urem_constant_op1(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> poison, i8 %x, i32 1 %ins = insertelement <2 x i8> poison, i8 %x, i32 1
%bo = urem <2 x i8> %ins, <i8 undef, i8 2> %bo = urem <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @urem_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @urem_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @urem_constant_op1_not_undef_lane( ; CHECK-LABEL: @urem_constant_op1_not_undef_lane(
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; ;
%ins = insertelement <2 x i8> poison, i8 %x, i32 0 %ins = insertelement <2 x i8> poison, i8 %x, i32 0
%bo = srem <2 x i8> <i8 5, i8 2>, %ins %bo = srem <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @srem_constant_op1(i8 %x) { define <2 x i8> @srem_constant_op1(i8 %x) {
; CHECK-LABEL: @srem_constant_op1( ; CHECK-LABEL: @srem_constant_op1(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> poison, i8 %x, i32 1 %ins = insertelement <2 x i8> poison, i8 %x, i32 1
%bo = srem <2 x i8> %ins, <i8 undef, i8 2> %bo = srem <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @srem_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @srem_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @srem_constant_op1_not_undef_lane( ; CHECK-LABEL: @srem_constant_op1_not_undef_lane(
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; ;
%ins = insertelement <2 x i8> poison, i8 %x, i32 0 %ins = insertelement <2 x i8> poison, i8 %x, i32 0
%bo = udiv exact <2 x i8> <i8 5, i8 2>, %ins %bo = udiv exact <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @udiv_constant_op1(i8 %x) { define <2 x i8> @udiv_constant_op1(i8 %x) {
; CHECK-LABEL: @udiv_constant_op1( ; CHECK-LABEL: @udiv_constant_op1(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> poison, i8 %x, i32 1 %ins = insertelement <2 x i8> poison, i8 %x, i32 1
%bo = udiv <2 x i8> %ins, <i8 undef, i8 2> %bo = udiv <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @udiv_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @udiv_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @udiv_constant_op1_not_undef_lane( ; CHECK-LABEL: @udiv_constant_op1_not_undef_lane(
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; ;
%ins = insertelement <2 x i8> poison, i8 %x, i32 0 %ins = insertelement <2 x i8> poison, i8 %x, i32 0
%bo = sdiv <2 x i8> <i8 5, i8 2>, %ins %bo = sdiv <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sdiv_constant_op1(i8 %x) { define <2 x i8> @sdiv_constant_op1(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op1( ; CHECK-LABEL: @sdiv_constant_op1(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> poison, i8 %x, i32 1 %ins = insertelement <2 x i8> poison, i8 %x, i32 1
%bo = sdiv exact <2 x i8> %ins, <i8 undef, i8 2> %bo = sdiv exact <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sdiv_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @sdiv_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op1_not_undef_lane( ; CHECK-LABEL: @sdiv_constant_op1_not_undef_lane(
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llvm/test/Transforms/InstCombine/inselt-binop.ll

Show First 20 Lines • Show All 241 Lines • ▼ Show 20 Lines
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = urem <2 x i8> <i8 5, i8 2>, %ins %bo = urem <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @urem_constant_op1(i8 %x) { define <2 x i8> @urem_constant_op1(i8 %x) {
; CHECK-LABEL: @urem_constant_op1( ; CHECK-LABEL: @urem_constant_op1(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = urem <2 x i8> %ins, <i8 undef, i8 2> %bo = urem <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @urem_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @urem_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @urem_constant_op1_not_undef_lane( ; CHECK-LABEL: @urem_constant_op1_not_undef_lane(
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; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = srem <2 x i8> <i8 5, i8 2>, %ins %bo = srem <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @srem_constant_op1(i8 %x) { define <2 x i8> @srem_constant_op1(i8 %x) {
; CHECK-LABEL: @srem_constant_op1( ; CHECK-LABEL: @srem_constant_op1(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = srem <2 x i8> %ins, <i8 undef, i8 2> %bo = srem <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @srem_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @srem_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @srem_constant_op1_not_undef_lane( ; CHECK-LABEL: @srem_constant_op1_not_undef_lane(
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; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = udiv exact <2 x i8> <i8 5, i8 2>, %ins %bo = udiv exact <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @udiv_constant_op1(i8 %x) { define <2 x i8> @udiv_constant_op1(i8 %x) {
; CHECK-LABEL: @udiv_constant_op1( ; CHECK-LABEL: @udiv_constant_op1(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = udiv <2 x i8> %ins, <i8 undef, i8 2> %bo = udiv <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @udiv_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @udiv_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @udiv_constant_op1_not_undef_lane( ; CHECK-LABEL: @udiv_constant_op1_not_undef_lane(
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; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = sdiv <2 x i8> <i8 5, i8 2>, %ins %bo = sdiv <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sdiv_constant_op1(i8 %x) { define <2 x i8> @sdiv_constant_op1(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op1( ; CHECK-LABEL: @sdiv_constant_op1(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = sdiv exact <2 x i8> %ins, <i8 undef, i8 2> %bo = sdiv exact <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sdiv_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @sdiv_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op1_not_undef_lane( ; CHECK-LABEL: @sdiv_constant_op1_not_undef_lane(
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llvm/test/Transforms/InstCombine/rem.ll

Show First 20 Lines • Show All 241 Lines • ▼ Show 20 Lines;
%shift.upgrd.1 = zext i8 %B to i32 %shift.upgrd.1 = zext i8 %B to i32
%Amt = shl i32 32, %shift.upgrd.1 %Amt = shl i32 32, %shift.upgrd.1
%V = urem i32 %X, %Amt %V = urem i32 %X, %Amt
ret i32 %V ret i32 %V
} }
define i32 @test6(i32 %A) { define i32 @test6(i32 %A) {
; CHECK-LABEL: @test6( ; CHECK-LABEL: @test6(
; CHECK-NEXT: ret i32 undef ; CHECK-NEXT: ret i32 poison
; ;
%B = srem i32 %A, 0 ;; undef %B = srem i32 %A, 0 ;; undef
ret i32 %B ret i32 %B
} }
define i32 @test7(i32 %A) { define i32 @test7(i32 %A) {
; CHECK-LABEL: @test7( ; CHECK-LABEL: @test7(
; CHECK-NEXT: ret i32 0 ; CHECK-NEXT: ret i32 0
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llvm/test/Transforms/InstCombine/sdiv-exact-by-negative-power-of-two.ll

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; CHECK-NEXT: ret <2 x i8> [[DIV]] ; CHECK-NEXT: ret <2 x i8> [[DIV]]
; ;
%div = sdiv exact <2 x i8> %x, <i8 -32, i8 16> %div = sdiv exact <2 x i8> %x, <i8 -32, i8 16>
ret <2 x i8> %div ret <2 x i8> %div
} }
define <2 x i8> @n4_vec_undef(<2 x i8> %x) { define <2 x i8> @n4_vec_undef(<2 x i8> %x) {
; CHECK-LABEL: @n4_vec_undef( ; CHECK-LABEL: @n4_vec_undef(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%div = sdiv exact <2 x i8> %x, <i8 -32, i8 undef> %div = sdiv exact <2 x i8> %x, <i8 -32, i8 undef>
ret <2 x i8> %div ret <2 x i8> %div
} }

llvm/test/Transforms/InstCombine/sdiv-exact-by-power-of-two.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret <2 x i8> [[DIV]] ; CHECK-NEXT: ret <2 x i8> [[DIV]]
; ;
%div = sdiv exact <2 x i8> %x, <i8 32, i8 16> %div = sdiv exact <2 x i8> %x, <i8 32, i8 16>
ret <2 x i8> %div ret <2 x i8> %div
} }
define <2 x i8> @n5_vec_undef(<2 x i8> %x) { define <2 x i8> @n5_vec_undef(<2 x i8> %x) {
; CHECK-LABEL: @n5_vec_undef( ; CHECK-LABEL: @n5_vec_undef(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%div = sdiv exact <2 x i8> %x, <i8 32, i8 undef> %div = sdiv exact <2 x i8> %x, <i8 32, i8 undef>
ret <2 x i8> %div ret <2 x i8> %div
} }
define <2 x i8> @n6_vec_negative(<2 x i8> %x) { define <2 x i8> @n6_vec_negative(<2 x i8> %x) {
; CHECK-LABEL: @n6_vec_negative( ; CHECK-LABEL: @n6_vec_negative(
; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i8> [[X:%.*]], <i8 32, i8 -128> ; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i8> [[X:%.*]], <i8 32, i8 -128>
; CHECK-NEXT: ret <2 x i8> [[DIV]] ; CHECK-NEXT: ret <2 x i8> [[DIV]]
; ;
%div = sdiv exact <2 x i8> %x, <i8 32, i8 128> ; non-non-negative divisor %div = sdiv exact <2 x i8> %x, <i8 32, i8 128> ; non-non-negative divisor
ret <2 x i8> %div ret <2 x i8> %div
} }

llvm/test/Transforms/InstCombine/shift.ll

Show First 20 Lines • Show All 656 Lines • ▼ Show 20 Lines
; ;
%rem = srem <3 x i32> %x, <i32 32, i32 16, i32 1> %rem = srem <3 x i32> %x, <i32 32, i32 16, i32 1>
%shl = shl <3 x i32> <i32 1, i32 1, i32 1>, %rem %shl = shl <3 x i32> <i32 1, i32 1, i32 1>, %rem
ret <3 x i32> %shl ret <3 x i32> %shl
} }
define <2 x i32> @test38_undef(<2 x i32> %x) nounwind readnone { define <2 x i32> @test38_undef(<2 x i32> %x) nounwind readnone {
; CHECK-LABEL: @test38_undef( ; CHECK-LABEL: @test38_undef(
; CHECK-NEXT: ret <2 x i32> undef ; CHECK-NEXT: ret <2 x i32> poison
; ;
%rem = srem <2 x i32> %x, <i32 32, i32 undef> %rem = srem <2 x i32> %x, <i32 32, i32 undef>
%shl = shl <2 x i32> <i32 1, i32 1>, %rem %shl = shl <2 x i32> <i32 1, i32 1>, %rem
ret <2 x i32> %shl ret <2 x i32> %shl
} }
; <rdar://problem/8756731> ; <rdar://problem/8756731>
define i8 @test39(i32 %a0) { define i8 @test39(i32 %a0) {
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llvm/test/Transforms/InstCombine/vector-udiv.ll

Show All 36 Lines
; CHECK-NEXT: ret <4 x i32> [[TMP2]] ; CHECK-NEXT: ret <4 x i32> [[TMP2]]
; ;
%1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9> %1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <4 x i32> @test_v4i32_negconst_undef(<4 x i32> %a0) { define <4 x i32> @test_v4i32_negconst_undef(<4 x i32> %a0) {
; CHECK-LABEL: @test_v4i32_negconst_undef( ; CHECK-LABEL: @test_v4i32_negconst_undef(
; CHECK-NEXT: ret <4 x i32> undef ; CHECK-NEXT: ret <4 x i32> poison
; ;
%1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 undef> %1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 undef>
ret <4 x i32> %1 ret <4 x i32> %1
} }
; X udiv (C1 << N), where C1 is "1<<C2" --> X >> (N+C2) ; X udiv (C1 << N), where C1 is "1<<C2" --> X >> (N+C2)
define <4 x i32> @test_v4i32_shl_splatconst_pow2(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @test_v4i32_shl_splatconst_pow2(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @test_v4i32_shl_splatconst_pow2( ; CHECK-LABEL: @test_v4i32_shl_splatconst_pow2(
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llvm/test/Transforms/InstCombine/vector-urem.ll

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; CHECK-NEXT: ret <4 x i32> [[TMP1]] ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
; ;
%1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8> %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <4 x i32> @test_v4i32_const_pow2_undef(<4 x i32> %a0) { define <4 x i32> @test_v4i32_const_pow2_undef(<4 x i32> %a0) {
; CHECK-LABEL: @test_v4i32_const_pow2_undef( ; CHECK-LABEL: @test_v4i32_const_pow2_undef(
; CHECK-NEXT: ret <4 x i32> undef ; CHECK-NEXT: ret <4 x i32> poison
; ;
%1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 undef> %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 undef>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <4 x i32> @test_v4i32_one(<4 x i32> %a0) { define <4 x i32> @test_v4i32_one(<4 x i32> %a0) {
; CHECK-LABEL: @test_v4i32_one( ; CHECK-LABEL: @test_v4i32_one(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i32> [[A0:%.*]], <i32 1, i32 1, i32 1, i32 1> ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i32> [[A0:%.*]], <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: ret <4 x i32> [[TMP3]] ; CHECK-NEXT: ret <4 x i32> [[TMP3]]
; ;
%1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9> %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <4 x i32> @test_v4i32_negconst_undef(<4 x i32> %a0) { define <4 x i32> @test_v4i32_negconst_undef(<4 x i32> %a0) {
; CHECK-LABEL: @test_v4i32_negconst_undef( ; CHECK-LABEL: @test_v4i32_negconst_undef(
; CHECK-NEXT: ret <4 x i32> undef ; CHECK-NEXT: ret <4 x i32> poison
; ;
%1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 undef> %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 undef>
ret <4 x i32> %1 ret <4 x i32> %1
} }

llvm/test/Transforms/InstSimplify/div.ll

Show All 37 Lines
define <2 x i8> @udiv_zero_elt_vec_constfold(<2 x i8> %x) { define <2 x i8> @udiv_zero_elt_vec_constfold(<2 x i8> %x) {
; CHECK-LABEL: @udiv_zero_elt_vec_constfold( ; CHECK-LABEL: @udiv_zero_elt_vec_constfold(
; CHECK-NEXT: ret <2 x i8> poison ; CHECK-NEXT: ret <2 x i8> poison
; ;
%div = udiv <2 x i8> <i8 1, i8 2>, <i8 42, i8 0> %div = udiv <2 x i8> <i8 1, i8 2>, <i8 42, i8 0>
ret <2 x i8> %div ret <2 x i8> %div
} }
; TODO: instsimplify should fold these to poison
define <2 x i8> @sdiv_zero_elt_vec(<2 x i8> %x) { define <2 x i8> @sdiv_zero_elt_vec(<2 x i8> %x) {
; CHECK-LABEL: @sdiv_zero_elt_vec( ; CHECK-LABEL: @sdiv_zero_elt_vec(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%div = sdiv <2 x i8> %x, <i8 -42, i8 0> %div = sdiv <2 x i8> %x, <i8 -42, i8 0>
ret <2 x i8> %div ret <2 x i8> %div
} }
define <2 x i8> @udiv_zero_elt_vec(<2 x i8> %x) { define <2 x i8> @udiv_zero_elt_vec(<2 x i8> %x) {
; CHECK-LABEL: @udiv_zero_elt_vec( ; CHECK-LABEL: @udiv_zero_elt_vec(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%div = udiv <2 x i8> %x, <i8 0, i8 42> %div = udiv <2 x i8> %x, <i8 0, i8 42>
ret <2 x i8> %div ret <2 x i8> %div
} }
define <2 x i8> @sdiv_undef_elt_vec(<2 x i8> %x) { define <2 x i8> @sdiv_undef_elt_vec(<2 x i8> %x) {
; CHECK-LABEL: @sdiv_undef_elt_vec( ; CHECK-LABEL: @sdiv_undef_elt_vec(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%div = sdiv <2 x i8> %x, <i8 -42, i8 undef> %div = sdiv <2 x i8> %x, <i8 -42, i8 undef>
ret <2 x i8> %div ret <2 x i8> %div
} }
define <2 x i8> @udiv_undef_elt_vec(<2 x i8> %x) { define <2 x i8> @udiv_undef_elt_vec(<2 x i8> %x) {
; CHECK-LABEL: @udiv_undef_elt_vec( ; CHECK-LABEL: @udiv_undef_elt_vec(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%div = udiv <2 x i8> %x, <i8 undef, i8 42> %div = udiv <2 x i8> %x, <i8 undef, i8 42>
ret <2 x i8> %div ret <2 x i8> %div
} }
; Division-by-zero is undef. UB in any vector lane means the whole op is undef. ; Division-by-zero is undef. UB in any vector lane means the whole op is undef.
; Thus, we can simplify this: if any element of 'y' is 0, we can do anything. ; Thus, we can simplify this: if any element of 'y' is 0, we can do anything.
; Therefore, assume that all elements of 'y' must be 1. ; Therefore, assume that all elements of 'y' must be 1.
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define i8 @sdiv_minusone_divisor() { define i8 @sdiv_minusone_divisor() {
; CHECK-LABEL: @sdiv_minusone_divisor( ; CHECK-LABEL: @sdiv_minusone_divisor(
; CHECK-NEXT: ret i8 poison ; CHECK-NEXT: ret i8 poison
; ;
%v = sdiv i8 -128, -1 %v = sdiv i8 -128, -1
ret i8 %v ret i8 %v
} }
; TODO: these should be poison
define i32 @poison(i32 %x) { define i32 @poison(i32 %x) {
; CHECK-LABEL: @poison( ; CHECK-LABEL: @poison(
; CHECK-NEXT: ret i32 poison ; CHECK-NEXT: ret i32 poison
; ;
%v = udiv i32 %x, poison %v = udiv i32 %x, poison
ret i32 %v ret i32 %v
} }
; TODO: this should be poison
define i32 @poison2(i32 %x) { define i32 @poison2(i32 %x) {
; CHECK-LABEL: @poison2( ; CHECK-LABEL: @poison2(
; CHECK-NEXT: ret i32 0 ; CHECK-NEXT: ret i32 0
; ;
%v = udiv i32 poison, %x %v = udiv i32 poison, %x
ret i32 %v ret i32 %v
} }
define <2 x i32> @poison3(<2 x i32> %x) { define <2 x i32> @poison3(<2 x i32> %x) {
; CHECK-LABEL: @poison3( ; CHECK-LABEL: @poison3(
; CHECK-NEXT: ret <2 x i32> undef ; CHECK-NEXT: ret <2 x i32> poison
; ;
%v = udiv <2 x i32> %x, <i32 poison, i32 1> %v = udiv <2 x i32> %x, <i32 poison, i32 1>
ret <2 x i32> %v ret <2 x i32> %v
} }
!0 = !{i32 0, i32 3} !0 = !{i32 0, i32 3}

llvm/test/Transforms/InstSimplify/rem.ll

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define <2 x i8> @urem_zero_elt_vec_constfold(<2 x i8> %x) { define <2 x i8> @urem_zero_elt_vec_constfold(<2 x i8> %x) {
; CHECK-LABEL: @urem_zero_elt_vec_constfold( ; CHECK-LABEL: @urem_zero_elt_vec_constfold(
; CHECK-NEXT: ret <2 x i8> poison ; CHECK-NEXT: ret <2 x i8> poison
; ;
%rem = urem <2 x i8> <i8 1, i8 2>, <i8 42, i8 0> %rem = urem <2 x i8> <i8 1, i8 2>, <i8 42, i8 0>
ret <2 x i8> %rem ret <2 x i8> %rem
} }
; TODO: instsimplify should fold these to poison
define <2 x i8> @srem_zero_elt_vec(<2 x i8> %x) { define <2 x i8> @srem_zero_elt_vec(<2 x i8> %x) {
; CHECK-LABEL: @srem_zero_elt_vec( ; CHECK-LABEL: @srem_zero_elt_vec(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%rem = srem <2 x i8> %x, <i8 -42, i8 0> %rem = srem <2 x i8> %x, <i8 -42, i8 0>
ret <2 x i8> %rem ret <2 x i8> %rem
} }
define <2 x i8> @urem_zero_elt_vec(<2 x i8> %x) { define <2 x i8> @urem_zero_elt_vec(<2 x i8> %x) {
; CHECK-LABEL: @urem_zero_elt_vec( ; CHECK-LABEL: @urem_zero_elt_vec(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%rem = urem <2 x i8> %x, <i8 0, i8 42> %rem = urem <2 x i8> %x, <i8 0, i8 42>
ret <2 x i8> %rem ret <2 x i8> %rem
} }
define <2 x i8> @srem_undef_elt_vec(<2 x i8> %x) { define <2 x i8> @srem_undef_elt_vec(<2 x i8> %x) {
; CHECK-LABEL: @srem_undef_elt_vec( ; CHECK-LABEL: @srem_undef_elt_vec(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%rem = srem <2 x i8> %x, <i8 -42, i8 undef> %rem = srem <2 x i8> %x, <i8 -42, i8 undef>
ret <2 x i8> %rem ret <2 x i8> %rem
} }
define <2 x i8> @urem_undef_elt_vec(<2 x i8> %x) { define <2 x i8> @urem_undef_elt_vec(<2 x i8> %x) {
; CHECK-LABEL: @urem_undef_elt_vec( ; CHECK-LABEL: @urem_undef_elt_vec(
; CHECK-NEXT: ret <2 x i8> undef ; CHECK-NEXT: ret <2 x i8> poison
; ;
%rem = urem <2 x i8> %x, <i8 undef, i8 42> %rem = urem <2 x i8> %x, <i8 undef, i8 42>
ret <2 x i8> %rem ret <2 x i8> %rem
} }
; Division-by-zero is undef. UB in any vector lane means the whole op is undef. ; Division-by-zero is undef. UB in any vector lane means the whole op is undef.
; Thus, we can simplify this: if any element of 'y' is 0, we can do anything. ; Thus, we can simplify this: if any element of 'y' is 0, we can do anything.
; Therefore, assume that all elements of 'y' must be 1. ; Therefore, assume that all elements of 'y' must be 1.
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llvm/test/Transforms/InstSimplify/undef.ll

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; CHECK-NEXT: ret <4 x i8> undef ; CHECK-NEXT: ret <4 x i8> undef
; ;
%b = shl <4 x i8> %a, <i8 8, i8 9, i8 undef, i8 -1> %b = shl <4 x i8> %a, <i8 8, i8 9, i8 undef, i8 -1>
ret <4 x i8> %b ret <4 x i8> %b
} }
define i32 @test20(i32 %a) { define i32 @test20(i32 %a) {
; CHECK-LABEL: @test20( ; CHECK-LABEL: @test20(
; CHECK-NEXT: ret i32 undef ; CHECK-NEXT: ret i32 poison
; ;
%b = udiv i32 %a, 0 %b = udiv i32 %a, 0
ret i32 %b ret i32 %b
} }
define <2 x i32> @test20vec(<2 x i32> %a) { define <2 x i32> @test20vec(<2 x i32> %a) {
; CHECK-LABEL: @test20vec( ; CHECK-LABEL: @test20vec(
; CHECK-NEXT: ret <2 x i32> undef ; CHECK-NEXT: ret <2 x i32> poison
; ;
%b = udiv <2 x i32> %a, zeroinitializer %b = udiv <2 x i32> %a, zeroinitializer
ret <2 x i32> %b ret <2 x i32> %b
} }
define i32 @test21(i32 %a) { define i32 @test21(i32 %a) {
; CHECK-LABEL: @test21( ; CHECK-LABEL: @test21(
; CHECK-NEXT: ret i32 undef ; CHECK-NEXT: ret i32 poison
; ;
%b = sdiv i32 %a, 0 %b = sdiv i32 %a, 0
ret i32 %b ret i32 %b
} }
define <2 x i32> @test21vec(<2 x i32> %a) { define <2 x i32> @test21vec(<2 x i32> %a) {
; CHECK-LABEL: @test21vec( ; CHECK-LABEL: @test21vec(
; CHECK-NEXT: ret <2 x i32> undef ; CHECK-NEXT: ret <2 x i32> poison
; ;
%b = sdiv <2 x i32> %a, zeroinitializer %b = sdiv <2 x i32> %a, zeroinitializer
ret <2 x i32> %b ret <2 x i32> %b
} }
define i32 @test22(i32 %a) { define i32 @test22(i32 %a) {
; CHECK-LABEL: @test22( ; CHECK-LABEL: @test22(
; CHECK-NEXT: ret i32 undef ; CHECK-NEXT: ret i32 undef
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; CHECK-NEXT: ret i32 poison ; CHECK-NEXT: ret i32 poison
; ;
%b = udiv i32 undef, undef %b = udiv i32 undef, undef
ret i32 %b ret i32 %b
} }
define i32 @test38(i32 %a) { define i32 @test38(i32 %a) {
; CHECK-LABEL: @test38( ; CHECK-LABEL: @test38(
; CHECK-NEXT: ret i32 undef ; CHECK-NEXT: ret i32 poison
; ;
%b = udiv i32 %a, undef %b = udiv i32 %a, undef
ret i32 %b ret i32 %b
} }
define i32 @test39() { define i32 @test39() {
; CHECK-LABEL: @test39( ; CHECK-LABEL: @test39(
; CHECK-NEXT: ret i32 poison ; CHECK-NEXT: ret i32 poison
; ;
%b = udiv i32 0, undef %b = udiv i32 0, undef
ret i32 %b ret i32 %b
} }

llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll

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; CHECK-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6 ; CHECK-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
; CHECK-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7 ; CHECK-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
; CHECK-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4 ; CHECK-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4
; CHECK-NEXT: [[AB2:%.*]] = sdiv i32 [[A2]], 8 ; CHECK-NEXT: [[AB2:%.*]] = sdiv i32 [[A2]], 8
; CHECK-NEXT: [[AB3:%.*]] = sdiv i32 [[A3]], 16 ; CHECK-NEXT: [[AB3:%.*]] = sdiv i32 [[A3]], 16
; CHECK-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4 ; CHECK-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; CHECK-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8 ; CHECK-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8
; CHECK-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16 ; CHECK-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> <i32 undef, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i32 1 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> <i32 undef, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i32 1
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[TMP1]], i32 [[AB2]], i32 2 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[TMP1]], i32 [[AB2]], i32 2
; CHECK-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[AB3]], i32 3 ; CHECK-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[AB3]], i32 3
; CHECK-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5 ; CHECK-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
; CHECK-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6 ; CHECK-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
; CHECK-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7 ; CHECK-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
; CHECK-NEXT: ret <8 x i32> [[R7]] ; CHECK-NEXT: ret <8 x i32> [[R7]]
; ;
%a0 = extractelement <8 x i32> %a, i32 0 %a0 = extractelement <8 x i32> %a, i32 0
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