[VE] Expand single-element BUILD_VECTOR to INSERT_VECTOR_ELT

[simoll]

Summary

We do this mostly to be able to test the insert_vector_elt isel patterns. As long as we don't, most single element insertions show up as BUILD_VECTOR in the backend.

[simoll]

• NFC. Rebased.

[kaz7]

llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll

3

|& works only with bash. For example, this test won't work on MacOS. Please use 2>&1 | style.

On the other hand, D93687 has been merged. So I guess this it is posisble to implement this test much simply using LSV instructions.

[simoll]

llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll

3

It's a chicken-egg problem.. i doubt anybody will build LLVM with VE on a MacOS system.. will fix this regardless, rebase the insert/extract element patch and update this test in a followup patch

[simoll]

|& -> 2>&1 |

[simoll]

This now depends on D93687 - the build_vector lowering causes introduces more instances of insert_vector_elt.

[kaz7]

LGTM

llvm/lib/Target/VE/VEISelLowering.cpp

if (isPositionIndependent()) {
       SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, VT);
       return DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Addr);
     }
     return makeHiLoPair(Addr, VEMCExpr::VK_VE_HI32, VEMCExpr::VK_VE_LO32, DAG);
   }
   }
 }
 
+static bool getUniqueInsertion(SDNode *N, unsigned &UniqueIdx) {
+  if (!isa<BuildVectorSDNode>(N))
+    return false;
+  const auto *BVN = cast<BuildVectorSDNode>(N);
+
+  // Find first non-undef insertion.
+  unsigned Idx;
+  for (Idx = 0; Idx < BVN->getNumOperands(); ++Idx) {
+    auto ElemV = BVN->getOperand(Idx);
+    if (!ElemV->isUndef())
+      break;
+  }
+  // Catch the (hypothetical) all-undef case.
+  if (Idx == BVN->getNumOperands())
+    return false;
+  // Remember insertion.
+  UniqueIdx = Idx++;
+  // Verify that all other insertions are undef.
+  for (; Idx < BVN->getNumOperands(); ++Idx) {
+    auto ElemV = BVN->getOperand(Idx);
+    if (!ElemV->isUndef())
+      return false;
+  }
+  return true;
+}
+
 static SDValue getSplatValue(SDNode *N) {
   if (auto *BuildVec = dyn_cast<BuildVectorSDNode>(N)) {
     return BuildVec->getSplatValue();
   }
   return SDValue();
 }
 
 SDValue VETargetLowering::lowerBUILD_VECTOR(SDValue Op,
                                             SelectionDAG &DAG) const {
   SDLoc DL(Op);
   unsigned NumEls = Op.getValueType().getVectorNumElements();
   MVT ElemVT = Op.getSimpleValueType().getVectorElementType();
 
+  // If there is just one element, expand to INSERT_VECTOR_ELT.
+  unsigned UniqueIdx;
+  if (getUniqueInsertion(Op.getNode(), UniqueIdx)) {
+    SDValue AccuV = DAG.getUNDEF(Op.getValueType());
+    auto ElemV = Op->getOperand(UniqueIdx);
+    SDValue IdxV = DAG.getConstant(UniqueIdx, DL, MVT::i64);
+    return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), AccuV,
+                       ElemV, IdxV);
+  }
+
+  // Else emit a broadcast.
   if (SDValue ScalarV = getSplatValue(Op.getNode())) {
     // lower to VEC_BROADCAST
     MVT LegalResVT = MVT::getVectorVT(ElemVT, 256);
 
     auto AVL = DAG.getConstant(NumEls, DL, MVT::i32);
     return DAG.getNode(VEISD::VEC_BROADCAST, DL, LegalResVT, Op.getOperand(0),
                        AVL);
   }

llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll

+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+; Function Attrs: norecurse nounwind readnone
+; Check that a single-element insertion is lowered to a insert_vector_elt node for isel.
+define fastcc <256 x i32> @expand_single_elem_build_vec(i32 %x, i32 %y) {
+; CHECK-LABEL: expand_single_elem_build_vec:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lsv %v0(42), %s0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %r = insertelement <256 x i32> undef, i32 %x, i32 42
+  ret <256 x i32> %r
+}

llvm/test/CodeGen/VE/Vector/insert_elt.ll

 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x i64> undef, i64 %s, i32 %idx
   ret <256 x i64> %ret
 }
 
 define fastcc <256 x i64> @insert_ri7_v256i64(i64 %s) {
 ; CHECK-LABEL: insert_ri7_v256i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    lsv %v0(127), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x i64> undef, i64 %s, i32 127
   ret <256 x i64> %ret
 }
 
 define fastcc <256 x i64> @insert_ri8_v256i64(i64 %s) {
 ; CHECK-LABEL: insert_ri8_v256i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    lea %s1, 128
+; CHECK-NEXT:    lsv %v0(%s1), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x i64> undef, i64 %s, i32 128
   ret <256 x i64> %ret
 }
 
 define fastcc <512 x i64> @insert_ri_v512i64(i64 %s) {
 ; CHECK-LABEL: insert_ri_v512i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v1, %s0
+; CHECK-NEXT:    lsv %v1(116), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <512 x i64> undef, i64 %s, i32 372
   ret <512 x i64> %ret
 }
 
 ;;; <256 x i32>
 
 define fastcc <256 x i32> @insert_rr_v256i32(i32 signext %idx, i32 signext %s) {
 ; CHECK-LABEL: insert_rr_v256i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lsv %v0(%s0), %s1
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x i32> undef, i32 %s, i32 %idx
   ret <256 x i32> %ret
 }
 
 define fastcc <256 x i32> @insert_ri7_v256i32(i32 signext %s) {
 ; CHECK-LABEL: insert_ri7_v256i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lsv %v0(127), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x i32> undef, i32 %s, i32 127
   ret <256 x i32> %ret
 }
 
 define fastcc <256 x i32> @insert_ri8_v256i32(i32 signext %s) {
 ; CHECK-LABEL: insert_ri8_v256i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea %s1, 128
+; CHECK-NEXT:    lsv %v0(%s1), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x i32> undef, i32 %s, i32 128
   ret <256 x i32> %ret
 }
 
 define fastcc <512 x i32> @insert_ri_v512i32(i32 signext %s) {
 ; CHECK-LABEL: insert_ri_v512i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 512
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    lea %s1, 186
+; CHECK-NEXT:    lvs %s2, %v0(%s1)
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    sll %s0, %s0, 32
+; CHECK-NEXT:    or %s0, %s2, %s0
+; CHECK-NEXT:    lsv %v0(%s1), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <512 x i32> undef, i32 %s, i32 372
   ret <512 x i32> %ret
 }
 
 define fastcc <512 x i32> @insert_rr_v512i32(i32 signext %idx, i32 signext %s) {
 ; CHECK-LABEL: insert_rr_v512i32:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x double> undef, double %s, i32 %idx
   ret <256 x double> %ret
 }
 
 define fastcc <256 x double> @insert_ri7_v256f64(double %s) {
 ; CHECK-LABEL: insert_ri7_v256f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    lsv %v0(127), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x double> undef, double %s, i32 127
   ret <256 x double> %ret
 }
 
 define fastcc <256 x double> @insert_ri8_v256f64(double %s) {
 ; CHECK-LABEL: insert_ri8_v256f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    lea %s1, 128
+; CHECK-NEXT:    lsv %v0(%s1), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x double> undef, double %s, i32 128
   ret <256 x double> %ret
 }
 
 define fastcc <512 x double> @insert_ri_v512f64(double %s) {
 ; CHECK-LABEL: insert_ri_v512f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v1, %s0
+; CHECK-NEXT:    lsv %v1(116), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <512 x double> undef, double %s, i32 372
   ret <512 x double> %ret
 }
 
 ;;; <256 x float>
 
 define fastcc <256 x float> @insert_rr_v256f32(i32 signext %idx, float %s) {
 ; CHECK-LABEL: insert_rr_v256f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lsv %v0(%s0), %s1
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x float> undef, float %s, i32 %idx
   ret <256 x float> %ret
 }
 
 define fastcc <256 x float> @insert_ri7_v256f32(float %s) {
 ; CHECK-LABEL: insert_ri7_v256f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    lsv %v0(127), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x float> undef, float %s, i32 127
   ret <256 x float> %ret
 }
 
 define fastcc <256 x float> @insert_ri8_v256f32(float %s) {
 ; CHECK-LABEL: insert_ri8_v256f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 256
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    lea %s1, 128
+; CHECK-NEXT:    lsv %v0(%s1), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <256 x float> undef, float %s, i32 128
   ret <256 x float> %ret
 }
 
 define fastcc <512 x float> @insert_ri_v512f32(float %s) {
 ; CHECK-LABEL: insert_ri_v512f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lea %s0, 512
-; CHECK-NEXT:    lvl %s0
-; CHECK-NEXT:    vbrd %v0, %s0
+; CHECK-NEXT:    sra.l %s0, %s0, 32
+; CHECK-NEXT:    lea %s1, 186
+; CHECK-NEXT:    lvs %s2, %v0(%s1)
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    sll %s0, %s0, 32
+; CHECK-NEXT:    or %s0, %s2, %s0
+; CHECK-NEXT:    lsv %v0(%s1), %s0
 ; CHECK-NEXT:    b.l.t (, %s10)
   %ret = insertelement <512 x float> undef, float %s, i32 372
   ret <512 x float> %ret
 }
 
 define fastcc <512 x float> @insert_rr_v512f32(i32 signext %idx, float %s) {
 ; CHECK-LABEL: insert_rr_v512f32:
 ; CHECK:       # %bb.0: