This is an archive of the discontinued LLVM Phabricator instance.

Differential D93545

[VE] Support RETURNADDR
ClosedPublic

Authored by kaz7 on Dec 18 2020, 7:44 AM.

Details

Reviewers
simoll
k-ishizaka
Commits
rGd99e4a4840d8: [VE] Support RETURNADDR
Summary

Implement RETURNADDR for VE. Add a regression test also.

Diff Detail

Unit TestsFailed

TimeTest
40 msx64 windows > Clangd Unit Tests._/ClangdTests_exe::DirectoryBasedGlobalCompilationDatabaseCacheTest.Cacheable

Event Timeline

kaz7 created this revision.Dec 18 2020, 7:44 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptDec 18 2020, 7:44 AM
kaz7 requested review of this revision.Dec 18 2020, 7:44 AM
Herald added a subscriber: llvm-commits. · View Herald TranscriptDec 18 2020, 7:44 AM
Harbormaster completed remote builds in B82967: Diff 312794.Dec 18 2020, 8:34 AM
simoll added inline comments.Dec 18 2020, 9:13 AM
llvm/lib/Target/VE/VEISelLowering.cpp
1526

I guess you could just use the type of Op here?

kaz7 added inline comments.Dec 18 2020, 5:02 PM
llvm/lib/Target/VE/VEISelLowering.cpp
1526

Sure. I'll change it.

kaz7 updated this revision to Diff 312905.Dec 18 2020, 5:03 PM

Update following a suggestion.

Harbormaster completed remote builds in B83030: Diff 312905.Dec 18 2020, 5:38 PM
simoll accepted this revision.Dec 21 2020, 1:34 AM
This revision is now accepted and ready to land.Dec 21 2020, 1:34 AM
This revision was landed with ongoing or failed builds.Dec 21 2020, 3:06 AM
Closed by commit rGd99e4a4840d8: [VE] Support RETURNADDR (authored by kaz7). · Explain Why
This revision was automatically updated to reflect the committed changes.
kaz7 added a commit: rGd99e4a4840d8: [VE] Support RETURNADDR.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
22 lines
test/
CodeGen/
VE/
Scalar/
91 lines

Diff 312794

llvm/lib/Target/VE/VEISelLowering.cpp

Show First 20 Lines • Show All 1,504 Lines • ▼ Show 20 Linesstatic SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
SDValue FrameAddr = SDValue FrameAddr =
DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, PtrVT); DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, PtrVT);
while (Depth--) while (Depth--)
FrameAddr = DAG.getLoad(Op.getValueType(), DL, DAG.getEntryNode(), FrameAddr = DAG.getLoad(Op.getValueType(), DL, DAG.getEntryNode(),
FrameAddr, MachinePointerInfo()); FrameAddr, MachinePointerInfo());
return FrameAddr; return FrameAddr;
} }
static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
const VETargetLowering &TLI,
const VESubtarget *Subtarget) {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MFI.setReturnAddressIsTaken(true);
if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
return SDValue();
SDValue FrameAddr = lowerFRAMEADDR(Op, DAG, TLI, Subtarget);
SDLoc DL(Op);
EVT PtrVT = TLI.getPointerTy(MF.getDataLayout());
simollUnsubmitted
Not Done
ReplyInline Actions

I guess you could just use the type of Op here?

simoll: I guess you could just use the type of `Op` here?
kaz7AuthorUnsubmitted
Done
ReplyInline Actions

Sure. I'll change it.

kaz7: Sure. I'll change it.
SDValue Offset = DAG.getConstant(8, DL, PtrVT);
return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, DL, PtrVT, FrameAddr, Offset),
MachinePointerInfo());
}
static SDValue getSplatValue(SDNode *N) { static SDValue getSplatValue(SDNode *N) {
if (auto *BuildVec = dyn_cast<BuildVectorSDNode>(N)) { if (auto *BuildVec = dyn_cast<BuildVectorSDNode>(N)) {
return BuildVec->getSplatValue(); return BuildVec->getSplatValue();
} }
return SDValue(); return SDValue();
} }
SDValue VETargetLowering::lowerBUILD_VECTOR(SDValue Op, SDValue VETargetLowering::lowerBUILD_VECTOR(SDValue Op,
Show All 34 LinesSDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::GlobalAddress: case ISD::GlobalAddress:
return lowerGlobalAddress(Op, DAG); return lowerGlobalAddress(Op, DAG);
case ISD::GlobalTLSAddress: case ISD::GlobalTLSAddress:
return lowerGlobalTLSAddress(Op, DAG); return lowerGlobalTLSAddress(Op, DAG);
case ISD::JumpTable: case ISD::JumpTable:
return lowerJumpTable(Op, DAG); return lowerJumpTable(Op, DAG);
case ISD::LOAD: case ISD::LOAD:
return lowerLOAD(Op, DAG); return lowerLOAD(Op, DAG);
case ISD::RETURNADDR:
return lowerRETURNADDR(Op, DAG, *this, Subtarget);
case ISD::BUILD_VECTOR: case ISD::BUILD_VECTOR:
return lowerBUILD_VECTOR(Op, DAG); return lowerBUILD_VECTOR(Op, DAG);
case ISD::STORE: case ISD::STORE:
return lowerSTORE(Op, DAG); return lowerSTORE(Op, DAG);
case ISD::VASTART: case ISD::VASTART:
return lowerVASTART(Op, DAG); return lowerVASTART(Op, DAG);
case ISD::VAARG: case ISD::VAARG:
return lowerVAARG(Op, DAG); return lowerVAARG(Op, DAG);
▲ Show 20 Lines • Show All 329 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/Scalar/returnaddr.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve-- | FileCheck %s
define i8* @h() nounwind readnone optsize {
; CHECK-LABEL: h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s11, -176(, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB0_2: # %entry
; CHECK-NEXT: ld %s0, (, %s9)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: ld %s0, 8(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
entry:
%ret = tail call i8* @llvm.returnaddress(i32 2)
ret i8* %ret
}
declare i8* @llvm.returnaddress(i32) nounwind readnone
define i8* @g() nounwind readnone optsize {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s11, -176(, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB1_2: # %entry
; CHECK-NEXT: ld %s0, (, %s9)
; CHECK-NEXT: ld %s0, 8(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
entry:
%ret = tail call i8* @llvm.returnaddress(i32 1)
ret i8* %ret
}
define i8* @f() nounwind readnone optsize {
; CHECK-LABEL: f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s11, -176(, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB2_2: # %entry
; CHECK-NEXT: ld %s0, 8(, %s9)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
entry:
%ret = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %ret
}