[VE] Add vfmk intrinsic instructions

[kaz7]

Summary

Add vfmk intrinsic instructions, a few pseudo instructions to expand
vfmk intrinsic using VM512 correctly, and regression tests.

[simoll]

llvm/lib/Target/VE/VEInstrInfo.cpp

738

Can we make this static and use something more lightweight than a std::vector?

std::map<unsigned, unsigned[2]>

749

better drop curly braces

753–801

I guess you could loop over this code for each part instead of replicating the code for the lower and upper part.

[kaz7]

Updated following suggestions.

[simoll]

Thanks! One nit, else good to go.

llvm/lib/Target/VE/VEInstrInfo.cpp

784

Nitpick: you can store the iterator here and use it to access first and second below.

llvm/include/llvm/IR/IntrinsicsVEVL.gen.td

 let TargetPrefix = "ve" in def int_ve_vl_vmrgw_vvvMl : GCCBuiltin<"__builtin_ve_vl_vmrgw_vvvMl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
 let TargetPrefix = "ve" in def int_ve_vl_vmrgw_vvvMvl : GCCBuiltin<"__builtin_ve_vl_vmrgw_vvvMvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
 let TargetPrefix = "ve" in def int_ve_vl_vmrgw_vsvMl : GCCBuiltin<"__builtin_ve_vl_vmrgw_vsvMl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i32>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
 let TargetPrefix = "ve" in def int_ve_vl_vmrgw_vsvMvl : GCCBuiltin<"__builtin_ve_vl_vmrgw_vsvMvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i32>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
 let TargetPrefix = "ve" in def int_ve_vl_vshf_vvvsl : GCCBuiltin<"__builtin_ve_vl_vshf_vvvsl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i64>, LLVMType<i32>], [IntrNoMem]>;
 let TargetPrefix = "ve" in def int_ve_vl_vshf_vvvsvl : GCCBuiltin<"__builtin_ve_vl_vshf_vvvsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
 let TargetPrefix = "ve" in def int_ve_vl_vcp_vvmvl : GCCBuiltin<"__builtin_ve_vl_vcp_vvmvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
 let TargetPrefix = "ve" in def int_ve_vl_vex_vvmvl : GCCBuiltin<"__builtin_ve_vl_vex_vvmvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklat_ml : GCCBuiltin<"__builtin_ve_vl_vfmklat_ml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklaf_ml : GCCBuiltin<"__builtin_ve_vl_vfmklaf_ml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkat_Ml : GCCBuiltin<"__builtin_ve_vl_pvfmkat_Ml">, Intrinsic<[LLVMType<v512i1>], [LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkaf_Ml : GCCBuiltin<"__builtin_ve_vl_pvfmkaf_Ml">, Intrinsic<[LLVMType<v512i1>], [LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklgt_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklgt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklgt_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklgt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkllt_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkllt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkllt_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkllt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklne_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklne_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklne_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklne_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkleq_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkleq_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkleq_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkleq_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklge_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklge_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklge_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklge_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklle_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklle_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklle_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklle_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklnum_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklnum_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklnum_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklnum_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklgtnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklgtnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklgtnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklgtnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklltnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklltnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklltnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklltnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklnenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklnenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklnenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklnenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkleqnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkleqnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkleqnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkleqnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklgenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmklgenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmklgenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmklgenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkllenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkllenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkllenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkllenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwgt_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwgt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwgt_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwgt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwlt_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwlt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwlt_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwlt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwne_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwne_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwne_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwne_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkweq_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkweq_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkweq_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkweq_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwge_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwge_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwge_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwge_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwle_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwle_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwle_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwle_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwnum_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwnum_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwnum_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwnum_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwgtnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwgtnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwgtnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwgtnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwltnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwltnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwltnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwltnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwnenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwnenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwnenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwnenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkweqnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkweqnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkweqnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkweqnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwgenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwgenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwgenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwgenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwlenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkwlenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkwlenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkwlenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlogt_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlogt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupgt_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupgt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlogt_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlogt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupgt_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupgt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlolt_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlolt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwuplt_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwuplt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlolt_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlolt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwuplt_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwuplt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlone_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlone_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupne_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupne_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlone_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlone_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupne_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupne_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwloeq_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwloeq_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupeq_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupeq_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwloeq_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwloeq_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupeq_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupeq_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwloge_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwloge_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupge_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupge_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwloge_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwloge_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupge_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupge_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlole_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlole_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwuple_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwuple_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlole_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlole_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwuple_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwuple_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlonum_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlonum_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupnum_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupnum_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlonum_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlonum_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupnum_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupnum_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlonan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlonan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlonan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlonan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlogtnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlogtnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupgtnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupgtnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlogtnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlogtnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupgtnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupgtnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwloltnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwloltnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupltnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupltnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwloltnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwloltnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupltnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupltnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlonenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlonenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupnenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupnenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlonenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlonenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupnenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupnenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwloeqnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwloeqnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupeqnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupeqnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwloeqnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwloeqnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupeqnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupeqnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlogenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlogenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupgenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwupgenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlogenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlogenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwupgenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwupgenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlolenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlolenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwuplenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwuplenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlolenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwlolenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwuplenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkwuplenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwgt_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwgt_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwgt_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwgt_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlt_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlt_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlt_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlt_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwne_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwne_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwne_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwne_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkweq_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkweq_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkweq_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkweq_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwge_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwge_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwge_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwge_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwle_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwle_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwle_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwle_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwnum_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwnum_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwnum_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwnum_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwnan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwnan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwnan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwnan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwgtnan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwgtnan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwgtnan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwgtnan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwltnan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwltnan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwltnan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwltnan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwnenan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwnenan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwnenan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwnenan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkweqnan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkweqnan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkweqnan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkweqnan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwgenan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwgenan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwgenan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwgenan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlenan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlenan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkwlenan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkwlenan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdgt_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdgt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdgt_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdgt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdlt_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdlt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdlt_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdlt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdne_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdne_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdne_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdne_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdeq_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdeq_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdeq_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdeq_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdge_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdge_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdge_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdge_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdle_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdle_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdle_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdle_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdnum_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdnum_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdnum_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdnum_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdgtnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdgtnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdgtnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdgtnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdltnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdltnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdltnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdltnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdnenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdnenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdnenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdnenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdeqnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdeqnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdeqnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdeqnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdgenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdgenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdgenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdgenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdlenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkdlenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkdlenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkdlenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksgt_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksgt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksgt_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksgt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkslt_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkslt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkslt_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkslt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksne_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksne_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksne_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksne_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkseq_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkseq_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkseq_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkseq_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksge_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksge_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksge_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksge_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksle_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksle_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksle_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksle_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksnum_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksnum_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksnum_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksnum_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksgtnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksgtnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksgtnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksgtnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksltnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksltnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksltnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksltnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksnenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksnenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksnenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksnenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkseqnan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkseqnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkseqnan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkseqnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksgenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmksgenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmksgenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmksgenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkslenan_mvl : GCCBuiltin<"__builtin_ve_vl_vfmkslenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vfmkslenan_mvml : GCCBuiltin<"__builtin_ve_vl_vfmkslenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslogt_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslogt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupgt_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupgt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslogt_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslogt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupgt_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupgt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslolt_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslolt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksuplt_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksuplt_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslolt_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslolt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksuplt_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksuplt_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslone_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslone_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupne_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupne_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslone_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslone_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupne_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupne_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksloeq_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksloeq_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupeq_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupeq_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksloeq_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksloeq_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupeq_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupeq_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksloge_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksloge_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupge_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupge_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksloge_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksloge_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupge_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupge_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslole_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslole_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksuple_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksuple_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslole_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslole_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksuple_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksuple_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslonum_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslonum_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupnum_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupnum_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslonum_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslonum_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupnum_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupnum_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslonan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslonan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslonan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslonan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslogtnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslogtnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupgtnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupgtnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslogtnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslogtnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupgtnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupgtnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksloltnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksloltnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupltnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupltnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksloltnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksloltnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupltnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupltnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslonenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslonenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupnenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupnenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslonenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslonenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupnenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupnenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksloeqnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksloeqnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupeqnan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupeqnan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksloeqnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksloeqnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupeqnan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupeqnan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslogenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslogenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupgenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksupgenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslogenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslogenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksupgenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksupgenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslolenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslolenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksuplenan_mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksuplenan_mvl">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslolenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmkslolenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksuplenan_mvml : GCCBuiltin<"__builtin_ve_vl_pvfmksuplenan_mvml">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksgt_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksgt_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksgt_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksgt_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslt_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslt_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslt_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkslt_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksne_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksne_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksne_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksne_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkseq_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkseq_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkseq_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkseq_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksge_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksge_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksge_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksge_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksle_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksle_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksle_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksle_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksnum_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksnum_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksnum_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksnum_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksnan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksnan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksnan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksnan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksgtnan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksgtnan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksgtnan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksgtnan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksltnan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksltnan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksltnan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksltnan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksnenan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksnenan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksnenan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksnenan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkseqnan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkseqnan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkseqnan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkseqnan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksgenan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmksgenan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmksgenan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmksgenan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslenan_Mvl : GCCBuiltin<"__builtin_ve_vl_pvfmkslenan_Mvl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvfmkslenan_MvMl : GCCBuiltin<"__builtin_ve_vl_pvfmkslenan_MvMl">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<i32>], [IntrNoMem]>;

llvm/lib/Target/VE/VEInstrInfo.cpp

 }
 
 static Register getVM512Upper(Register reg) {
   return (reg - VE::VMP0) * 2 + VE::VM0;
 }
 
 static Register getVM512Lower(Register reg) { return getVM512Upper(reg) + 1; }
 
+static void addOperandsForVFMK(MachineInstrBuilder &MIB, MachineInstr &MI,
+                               bool Upper) {
+  // VM512
+  MIB.addReg(Upper ? getVM512Upper(MI.getOperand(0).getReg())
+                   : getVM512Lower(MI.getOperand(0).getReg()));
+
+  switch (MI.getNumExplicitOperands()) {
+  default:
+    report_fatal_error("unexpected number of operands for pvfmk");
+  case 2: // _Ml: VM512, VL
+    // VL
+    MIB.addReg(MI.getOperand(1).getReg());
+    break;
+  case 4: // _Mvl: VM512, CC, VR, VL
+    // CC
+    MIB.addImm(MI.getOperand(1).getImm());
+    // VR
+    MIB.addReg(MI.getOperand(2).getReg());
+    // VL
+    MIB.addReg(MI.getOperand(3).getReg());
+    break;
+  case 5: // _MvMl: VM512, CC, VR, VM512, VL
+    // CC
+    MIB.addImm(MI.getOperand(1).getImm());
+    // VR
+    MIB.addReg(MI.getOperand(2).getReg());
+    // VM512
+    MIB.addReg(Upper ? getVM512Upper(MI.getOperand(3).getReg())
+                     : getVM512Lower(MI.getOperand(3).getReg()));
+    // VL
+    MIB.addReg(MI.getOperand(4).getReg());
+    break;
+  }
+}
+
+static void expandPseudoVFMK(const TargetInstrInfo &TI, MachineInstr &MI) {
+  // replace to pvfmk.w.up and pvfmk.w.lo
+  // replace to pvfmk.s.up and pvfmk.s.lo
+
+  static std::map<unsigned, std::pair<unsigned, unsigned>> VFMKMap = {
+      {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}},
+      {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}},
+      {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}},
+      {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}},
+      {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}},
+      {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}},
+  };
+
+  unsigned Opcode = MI.getOpcode();
+
+  auto Found = VFMKMap.find(Opcode);
+  if (Found == VFMKMap.end())
+    report_fatal_error("unexpected opcode for pseudo vfmk");
+
+  unsigned OpcodeUpper = (*Found).second.first;
+  unsigned OpcodeLower = (*Found).second.second;
+
+  MachineBasicBlock *MBB = MI.getParent();
+  DebugLoc DL = MI.getDebugLoc();
+
+  MachineInstrBuilder Bu = BuildMI(*MBB, MI, DL, TI.get(OpcodeUpper));
+  addOperandsForVFMK(Bu, MI, /* Upper */ true);
+  MachineInstrBuilder Bl = BuildMI(*MBB, MI, DL, TI.get(OpcodeLower));
+  addOperandsForVFMK(Bl, MI, /* Upper */ false);
+
+  MI.eraseFromParent();
+}
+
 bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   case VE::EXTEND_STACK: {
     return expandExtendStackPseudo(MI);
   }
   case VE::EXTEND_STACK_GUARD: {
     MI.eraseFromParent(); // The pseudo instruction is gone now.
     return true;
case VE::SVMyi: {
     MachineInstr *Inst = MIB.getInstr();
     MI.eraseFromParent();
     if (KillSrc) {
       const TargetRegisterInfo *TRI = &getRegisterInfo();
       Inst->addRegisterKilled(MI.getOperand(1).getReg(), TRI, true);
     }
     return true;
   }
+  case VE::VFMKyal:
+  case VE::VFMKynal:
+  case VE::VFMKWyvl:
+  case VE::VFMKWyvyl:
+  case VE::VFMKSyvl:
+  case VE::VFMKSyvyl:
+    expandPseudoVFMK(*this, MI);
   }
   return false;
 }
 
 bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const {
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
   const VESubtarget &STI = MF.getSubtarget<VESubtarget>();

llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td

 def : Pat<(int_ve_vl_vmrgw_vvvMl v256f64:$vy, v256f64:$vz, v512i1:$vm, i32:$vl), (VMRGWvvml v256f64:$vy, v256f64:$vz, v512i1:$vm, i32:$vl)>;
 def : Pat<(int_ve_vl_vmrgw_vvvMvl v256f64:$vy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (VMRGWvvml_v v256f64:$vy, v256f64:$vz, v512i1:$vm, i32:$vl, v256f64:$pt)>;
 def : Pat<(int_ve_vl_vshf_vvvsl v256f64:$vy, v256f64:$vz, i64:$sy, i32:$vl), (VSHFvvrl v256f64:$vy, v256f64:$vz, i64:$sy, i32:$vl)>;
 def : Pat<(int_ve_vl_vshf_vvvsvl v256f64:$vy, v256f64:$vz, i64:$sy, v256f64:$pt, i32:$vl), (VSHFvvrl_v v256f64:$vy, v256f64:$vz, i64:$sy, i32:$vl, v256f64:$pt)>;
 def : Pat<(int_ve_vl_vshf_vvvsl v256f64:$vy, v256f64:$vz, uimm6:$N, i32:$vl), (VSHFvvil v256f64:$vy, v256f64:$vz, (ULO7 $N), i32:$vl)>;
 def : Pat<(int_ve_vl_vshf_vvvsvl v256f64:$vy, v256f64:$vz, uimm6:$N, v256f64:$pt, i32:$vl), (VSHFvvil_v v256f64:$vy, v256f64:$vz, (ULO7 $N), i32:$vl, v256f64:$pt)>;
 def : Pat<(int_ve_vl_vcp_vvmvl v256f64:$vz, v256i1:$vm, v256f64:$pt, i32:$vl), (VCPvml_v v256f64:$vz, v256i1:$vm, i32:$vl, v256f64:$pt)>;
 def : Pat<(int_ve_vl_vex_vvmvl v256f64:$vz, v256i1:$vm, v256f64:$pt, i32:$vl), (VEXvml_v v256f64:$vz, v256i1:$vm, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_vfmklat_ml i32:$vl), (VFMKLal i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklaf_ml i32:$vl), (VFMKLnal i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkat_Ml i32:$vl), (VFMKyal i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkaf_Ml i32:$vl), (VFMKynal i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklgt_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_IG, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklgt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_IG, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkllt_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_IL, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkllt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_IL, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklne_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_INE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklne_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_INE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkleq_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_IEQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkleq_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_IEQ, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklge_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_IGE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklge_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_IGE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklle_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_ILE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklle_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_ILE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklnum_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklnum_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_NUM, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklnan_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_NAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklgtnan_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklgtnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_GNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklltnan_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklltnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_LNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklnenan_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklnenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_NENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkleqnan_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkleqnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_EQNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklgenan_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmklgenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_GENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkllenan_mvl v256f64:$vz, i32:$vl), (VFMKLvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkllenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKLvml CC_LENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwgt_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_IG, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwgt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_IG, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwlt_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_IL, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwlt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_IL, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwne_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_INE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwne_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_INE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkweq_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_IEQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkweq_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_IEQ, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwge_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_IGE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwge_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_IGE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwle_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_ILE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwle_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_ILE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwnum_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwnum_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_NUM, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwnan_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_NAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwgtnan_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwgtnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_GNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwltnan_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwltnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_LNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwnenan_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwnenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_NENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkweqnan_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkweqnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_EQNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwgenan_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwgenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_GENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwlenan_mvl v256f64:$vz, i32:$vl), (VFMKWvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkwlenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKWvml CC_LENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlogt_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_IG, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupgt_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_IG, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlogt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_IG, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupgt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_IG, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlolt_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_IL, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwuplt_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_IL, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlolt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_IL, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwuplt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_IL, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlone_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_INE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupne_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_INE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlone_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_INE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupne_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_INE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwloeq_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_IEQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupeq_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_IEQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwloeq_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_IEQ, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupeq_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_IEQ, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwloge_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_IGE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupge_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_IGE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwloge_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_IGE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupge_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_IGE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlole_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_ILE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwuple_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_ILE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlole_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_ILE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwuple_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_ILE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlonum_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupnum_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlonum_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_NUM, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupnum_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_NUM, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlonan_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupnan_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlonan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_NAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_NAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlogtnan_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupgtnan_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlogtnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_GNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupgtnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_GNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwloltnan_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupltnan_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwloltnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_LNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupltnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_LNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlonenan_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupnenan_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlonenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_NENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupnenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_NENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwloeqnan_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupeqnan_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwloeqnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_EQNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupeqnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_EQNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlogenan_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupgenan_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlogenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_GENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwupgenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_GENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlolenan_mvl v256f64:$vz, i32:$vl), (PVFMKWLOvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwuplenan_mvl v256f64:$vz, i32:$vl), (PVFMKWUPvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlolenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWLOvml CC_LENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwuplenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKWUPvml CC_LENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwgt_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_IG, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwgt_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_IG, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlt_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_IL, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlt_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_IL, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwne_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_INE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwne_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_INE, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkweq_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_IEQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkweq_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_IEQ, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwge_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_IGE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwge_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_IGE, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwle_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_ILE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwle_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_ILE, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwnum_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwnum_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_NUM, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwnan_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwnan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_NAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwgtnan_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwgtnan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_GNAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwltnan_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwltnan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_LNAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwnenan_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwnenan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_NENAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkweqnan_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkweqnan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_EQNAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwgenan_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwgenan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_GENAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlenan_Mvl v256f64:$vz, i32:$vl), (VFMKWyvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkwlenan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKWyvyl CC_LENAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdgt_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_G, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdgt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_G, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdlt_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_L, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdlt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_L, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdne_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_NE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdne_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_NE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdeq_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_EQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdeq_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_EQ, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdge_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_GE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdge_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_GE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdle_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_LE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdle_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_LE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdnum_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdnum_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_NUM, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdnan_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_NAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdgtnan_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdgtnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_GNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdltnan_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdltnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_LNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdnenan_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdnenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_NENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdeqnan_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdeqnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_EQNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdgenan_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdgenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_GENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdlenan_mvl v256f64:$vz, i32:$vl), (VFMKDvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkdlenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKDvml CC_LENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksgt_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_G, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksgt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_G, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkslt_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_L, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkslt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_L, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksne_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_NE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksne_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_NE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkseq_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_EQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkseq_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_EQ, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksge_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_GE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksge_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_GE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksle_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_LE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksle_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_LE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksnum_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksnum_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_NUM, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksnan_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_NAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksgtnan_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksgtnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_GNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksltnan_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksltnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_LNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksnenan_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksnenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_NENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkseqnan_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkseqnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_EQNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksgenan_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmksgenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_GENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkslenan_mvl v256f64:$vz, i32:$vl), (VFMKSvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vfmkslenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (VFMKSvml CC_LENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslogt_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_G, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupgt_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_G, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslogt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_G, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupgt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_G, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslolt_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_L, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksuplt_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_L, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslolt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_L, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksuplt_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_L, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslone_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_NE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupne_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_NE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslone_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_NE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupne_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_NE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksloeq_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_EQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupeq_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_EQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksloeq_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_EQ, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupeq_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_EQ, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksloge_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_GE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupge_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_GE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksloge_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_GE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupge_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_GE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslole_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_LE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksuple_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_LE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslole_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_LE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksuple_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_LE, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslonum_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupnum_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslonum_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_NUM, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupnum_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_NUM, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslonan_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupnan_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslonan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_NAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_NAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslogtnan_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupgtnan_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslogtnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_GNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupgtnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_GNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksloltnan_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupltnan_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksloltnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_LNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupltnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_LNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslonenan_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupnenan_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslonenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_NENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupnenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_NENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksloeqnan_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupeqnan_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksloeqnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_EQNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupeqnan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_EQNAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslogenan_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupgenan_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslogenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_GENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksupgenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_GENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslolenan_mvl v256f64:$vz, i32:$vl), (PVFMKSLOvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksuplenan_mvl v256f64:$vz, i32:$vl), (PVFMKSUPvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslolenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSLOvml CC_LENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksuplenan_mvml v256f64:$vz, v256i1:$vm, i32:$vl), (PVFMKSUPvml CC_LENAN, v256f64:$vz, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksgt_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_G, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksgt_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_G, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslt_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_L, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslt_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_L, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksne_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_NE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksne_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_NE, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkseq_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_EQ, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkseq_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_EQ, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksge_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_GE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksge_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_GE, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksle_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_LE, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksle_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_LE, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksnum_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_NUM, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksnum_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_NUM, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksnan_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_NAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksnan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_NAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksgtnan_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_GNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksgtnan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_GNAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksltnan_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_LNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksltnan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_LNAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksnenan_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_NENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksnenan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_NENAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkseqnan_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_EQNAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkseqnan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_EQNAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksgenan_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_GENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmksgenan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_GENAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslenan_Mvl v256f64:$vz, i32:$vl), (VFMKSyvl CC_LENAN, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pvfmkslenan_MvMl v256f64:$vz, v512i1:$vm, i32:$vl), (VFMKSyvyl CC_LENAN, v256f64:$vz, v512i1:$vm, i32:$vl)>;

llvm/lib/Target/VE/VEInstrVec.td

 //===----------------------------------------------------------------------===//
 // Vector Instructions
 //===----------------------------------------------------------------------===//
 
+//===----------------------------------------------------------------------===//
 // Pseudo instructions for VM512 modifications
-//
-// Specifies hasSideEffects = 0 to disable UnmodeledSideEffects.
+//===----------------------------------------------------------------------===//
 
-let hasSideEffects = 0 in {
+// LVM/SVM instructions using VM512
+let hasSideEffects = 0, isCodeGenOnly = 1 in {
   let Constraints = "$vx = $vd", DisableEncoding = "$vd" in {
     def LVMyir_y : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz, VM512:$vd),
                           "# pseudo LVM $vx, $sy, $sz, $vd">;
     def LVMyim_y : Pseudo<(outs VM512:$vx),
                           (ins uimm3:$sy, mimm:$sz, VM512:$vd),
                           "# pseudo LVM $vx, $sy, $sz, $vd">;
   }
   def LVMyir : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz),
                       "# pseudo LVM $vx, $sy, $sz">;
   def LVMyim : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, mimm:$sz),
                       "# pseudo LVM $vx, $sy, $sz">;
   def SVMyi : Pseudo<(outs I64:$sx), (ins VM512:$vz, uimm3:$sy),
                      "# pseudo SVM $sx, $vz, $sy">;
 }
 
+// VFMK/VFMKW/VFMKS instructions using VM512
+let hasSideEffects = 0, isCodeGenOnly = 1, DisableEncoding = "$vl" in {
+  def VFMKyal : Pseudo<(outs VM512:$vmx), (ins I32:$vl),
+                       "# pseudo-vfmk.at $vmx">;
+  def VFMKynal : Pseudo<(outs VM512:$vmx), (ins I32:$vl),
+                        "# pseudo-vfmk.af $vmx">;
+  def VFMKWyvl  : Pseudo<(outs VM512:$vmx),
+                         (ins CCOp:$cf, V64:$vz, I32:$vl),
+                         "# pseudo-vfmk.w.$cf $vmx, $vz">;
+  def VFMKWyvyl : Pseudo<(outs VM512:$vmx),
+                         (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
+                         "# pseudo-vfmk.w.$cf $vmx, $vz, $vm">;
+  def VFMKSyvl  : Pseudo<(outs VM512:$vmx),
+                         (ins CCOp:$cf, V64:$vz, I32:$vl),
+                         "# pseudo-vfmk.s.$cf $vmx, $vz">;
+  def VFMKSyvyl : Pseudo<(outs VM512:$vmx),
+                         (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
+                         "# pseudo-vfmk.s.$cf $vmx, $vz, $vm">;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //
 // Define all vector instructions defined in SX-Aurora TSUBASA Architecture
 // Guide here.  As those mnemonics, we use mnemonics defined in Vector Engine
 // Assembly Language Reference Manual.
 //
 // Some instructions can update existing data by following instructions

llvm/test/CodeGen/VE/VELIntrinsics/vfmk.ll

+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test vector form mask intrinsic instructions
+;;;
+;;; Note:
+;;;   We test VFMK*al, VFMK*nal, VFMK*vl, VFMK*vml, PVFMK*yal, PVFMK*ynal,
+;;;   PVFMK*vl, PVFMK*vml, PVFMK*yvl, and PVFMK*yvyl instructions.
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklat_ml() {
+; CHECK-LABEL: vfmklat_ml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.at %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %1 = tail call <256 x i1> @llvm.ve.vl.vfmklat.ml(i32 256)
+  ret <256 x i1> %1
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklat.ml(i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklaf_ml() {
+; CHECK-LABEL: vfmklaf_ml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.af %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %1 = tail call <256 x i1> @llvm.ve.vl.vfmklaf.ml(i32 256)
+  ret <256 x i1> %1
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklaf.ml(i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklgt_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklgt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.gt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklgt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklgt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklgt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklgt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.gt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklgt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklgt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkllt_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkllt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.lt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkllt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkllt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkllt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkllt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.lt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkllt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkllt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklne_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklne_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.ne %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklne.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklne.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklne_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklne_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.ne %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklne.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklne.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkleq_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkleq_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.eq %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkleq.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkleq.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkleq_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkleq_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.eq %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkleq.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkleq.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklge_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklge_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.ge %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklge.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklge.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklge_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklge_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.ge %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklge.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklge.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklle_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklle_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.le %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklle.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklle.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklle_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklle_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.le %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklle.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklle.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklnum_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklnum_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.num %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklnum.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklnum.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklnum_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklnum_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.num %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklnum.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklnum.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.nan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.nan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklgtnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklgtnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.gtnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklgtnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklgtnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklgtnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklgtnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.gtnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklgtnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklgtnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklltnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklltnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.ltnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklltnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklltnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklltnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklltnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.ltnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklltnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklltnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklnenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklnenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.nenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklnenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklnenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklnenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklnenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.nenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklnenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklnenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkleqnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkleqnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.eqnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkleqnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkleqnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkleqnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkleqnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.eqnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkleqnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkleqnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklgenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmklgenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.genan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmklgenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklgenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmklgenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmklgenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.genan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmklgenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmklgenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkllenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkllenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.lenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkllenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkllenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkllenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkllenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.lenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkllenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkllenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwgt_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwgt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.gt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwgt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwgt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.gt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwgt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwgt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwlt_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwlt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.lt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwlt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwlt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwlt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwlt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.lt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwlt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwlt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwne_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwne_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ne %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwne.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwne.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwne_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwne_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ne %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwne.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwne.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkweq_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkweq_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.eq %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkweq.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkweq.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkweq_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkweq_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.eq %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkweq.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkweq.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwge_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwge_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ge %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwge.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwge.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwge_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwge_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ge %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwge.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwge.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwle_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwle_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.le %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwle.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwle.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwle_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwle_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.le %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwle.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwle.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwnum_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwnum_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.num %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwnum.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwnum.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwnum_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwnum_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.num %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwnum.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwnum.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.nan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.nan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwgtnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwgtnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.gtnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwgtnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwgtnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwgtnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwgtnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.gtnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwgtnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwgtnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwltnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwltnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ltnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwltnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwltnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwltnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwltnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ltnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwltnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwltnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwnenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwnenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.nenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwnenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwnenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwnenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwnenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.nenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwnenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwnenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkweqnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkweqnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.eqnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkweqnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkweqnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkweqnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkweqnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.eqnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkweqnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkweqnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwgenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwgenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.genan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwgenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwgenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwgenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwgenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.genan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwgenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwgenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwlenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkwlenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.lenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkwlenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwlenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkwlenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkwlenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.lenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkwlenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkwlenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdgt_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdgt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.gt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdgt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdgt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdgt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdgt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.gt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdgt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdgt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdlt_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdlt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.lt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdlt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdlt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdlt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdlt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.lt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdlt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdlt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdne_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdne_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.ne %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdne.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdne.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdne_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdne_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.ne %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdne.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdne.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdeq_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdeq_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.eq %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdeq.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdeq.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdeq_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdeq_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.eq %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdeq.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdeq.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdge_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdge_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.ge %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdge.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdge.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdge_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdge_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.ge %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdge.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdge.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdle_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdle_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.le %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdle.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdle.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdle_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdle_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.le %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdle.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdle.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdnum_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdnum_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.num %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdnum.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdnum.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdnum_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdnum_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.num %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdnum.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdnum.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.nan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.nan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdgtnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdgtnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.gtnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdgtnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdgtnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdgtnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdgtnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.gtnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdgtnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdgtnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdltnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdltnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.ltnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdltnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdltnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdltnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdltnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.ltnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdltnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdltnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdnenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdnenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.nenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdnenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdnenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdnenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdnenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.nenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdnenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdnenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdeqnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdeqnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.eqnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdeqnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdeqnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdeqnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdeqnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.eqnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdeqnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdeqnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdgenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdgenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.genan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdgenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdgenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdgenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdgenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.genan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdgenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdgenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdlenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkdlenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.lenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkdlenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdlenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkdlenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkdlenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.d.lenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkdlenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkdlenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksgt_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksgt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.gt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksgt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksgt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksgt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksgt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.gt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksgt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksgt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkslt_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkslt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.lt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkslt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkslt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkslt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkslt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.lt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkslt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkslt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksne_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksne_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.ne %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksne.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksne.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksne_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksne_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.ne %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksne.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksne.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkseq_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkseq_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.eq %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkseq.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkseq.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkseq_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkseq_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.eq %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkseq.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkseq.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksge_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksge_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.ge %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksge.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksge.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksge_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksge_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.ge %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksge.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksge.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksle_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksle_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.le %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksle.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksle.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksle_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksle_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.le %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksle.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksle.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksnum_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksnum_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.num %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksnum.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksnum.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksnum_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksnum_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.num %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksnum.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksnum.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.nan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.nan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksgtnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksgtnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.gtnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksgtnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksgtnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksgtnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksgtnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.gtnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksgtnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksgtnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksltnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksltnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.ltnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksltnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksltnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksltnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksltnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.ltnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksltnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksltnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksnenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksnenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.nenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksnenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksnenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksnenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksnenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.nenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksnenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksnenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkseqnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkseqnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.eqnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkseqnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkseqnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkseqnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkseqnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.eqnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkseqnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkseqnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksgenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmksgenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.genan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmksgenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksgenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmksgenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmksgenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.genan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmksgenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmksgenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkslenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: vfmkslenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.lenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.vfmkslenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkslenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @vfmkslenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: vfmkslenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.s.lenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.vfmkslenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.vfmkslenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkat_Ml() {
+; CHECK-LABEL: pvfmkat_Ml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.at %vm2
+; CHECK-NEXT:    vfmk.l.at %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %1 = tail call <512 x i1> @llvm.ve.vl.pvfmkat.Ml(i32 256)
+  ret <512 x i1> %1
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkat.Ml(i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkaf_Ml() {
+; CHECK-LABEL: pvfmkaf_Ml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.l.af %vm2
+; CHECK-NEXT:    vfmk.l.af %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %1 = tail call <512 x i1> @llvm.ve.vl.pvfmkaf.Ml(i32 256)
+  ret <512 x i1> %1
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkaf.Ml(i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslogt_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslogt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.gt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslogt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslogt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslogt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslogt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.gt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslogt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslogt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslolt_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslolt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.lt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslolt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslolt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslolt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslolt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.lt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslolt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslolt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslone_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslone_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.ne %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslone.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslone.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslone_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslone_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.ne %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslone.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslone.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksloeq_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksloeq_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.eq %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksloeq.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksloeq.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksloeq_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksloeq_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.eq %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksloeq.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksloeq.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksloge_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksloge_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.ge %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksloge.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksloge.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksloge_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksloge_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.ge %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksloge.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksloge.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslole_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslole_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.le %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslole.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslole.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslole_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslole_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.le %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslole.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslole.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslonum_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslonum_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.num %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslonum.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslonum.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslonum_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslonum_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.num %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslonum.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslonum.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslonan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslonan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.nan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslonan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslonan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslonan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslonan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.nan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslonan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslonan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslogtnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslogtnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.gtnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslogtnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslogtnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslogtnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslogtnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.gtnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslogtnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslogtnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksloltnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksloltnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.ltnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksloltnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksloltnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksloltnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksloltnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.ltnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksloltnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksloltnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslonenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslonenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.nenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslonenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslonenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslonenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslonenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.nenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslonenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslonenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksloeqnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksloeqnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.eqnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksloeqnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksloeqnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksloeqnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksloeqnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.eqnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksloeqnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksloeqnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslogenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslogenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.genan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslogenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslogenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslogenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslogenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.genan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslogenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslogenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslolenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslolenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.lenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkslolenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslolenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkslolenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkslolenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.lo.lenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkslolenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkslolenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupgt_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupgt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.gt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupgt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupgt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupgt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupgt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.gt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupgt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupgt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksuplt_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksuplt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.lt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksuplt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksuplt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksuplt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksuplt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.lt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksuplt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksuplt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupne_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupne_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ne %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupne.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupne.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupne_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupne_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ne %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupne.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupne.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupeq_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupeq_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.eq %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupeq.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupeq.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupeq_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupeq_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.eq %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupeq.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupeq.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupge_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupge_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ge %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupge.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupge.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupge_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupge_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ge %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupge.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupge.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksuple_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksuple_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.le %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksuple.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksuple.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksuple_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksuple_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.le %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksuple.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksuple.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupnum_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupnum_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.num %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupnum.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupnum.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupnum_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupnum_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.num %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupnum.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupnum.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.nan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.nan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupgtnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupgtnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.gtnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupgtnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupgtnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupgtnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupgtnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.gtnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupgtnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupgtnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupltnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupltnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ltnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupltnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupltnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupltnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupltnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ltnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupltnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupltnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupnenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupnenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.nenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupnenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupnenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupnenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupnenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.nenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupnenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupnenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupeqnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupeqnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.eqnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupeqnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupeqnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupeqnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupeqnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.eqnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupeqnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupeqnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupgenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksupgenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.genan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksupgenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupgenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksupgenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksupgenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.genan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksupgenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksupgenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksuplenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksuplenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.lenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmksuplenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksuplenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmksuplenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmksuplenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.lenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmksuplenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmksuplenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlogt_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlogt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.gt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlogt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlogt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlogt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlogt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.gt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlogt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlogt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlolt_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlolt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.lt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlolt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlolt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlolt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlolt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.lt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlolt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlolt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlone_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlone_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ne %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlone.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlone.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlone_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlone_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ne %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlone.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlone.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwloeq_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwloeq_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.eq %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwloeq.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwloeq.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwloeq_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwloeq_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.eq %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwloeq.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwloeq.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwloge_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwloge_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ge %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwloge.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwloge.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwloge_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwloge_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ge %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwloge.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwloge.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlole_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlole_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.le %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlole.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlole.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlole_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlole_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.le %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlole.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlole.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlonum_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlonum_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.num %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlonum.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlonum.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlonum_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlonum_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.num %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlonum.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlonum.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlonan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlonan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.nan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlonan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlonan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlonan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlonan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.nan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlonan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlonan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlogtnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlogtnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.gtnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlogtnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlogtnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlogtnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlogtnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.gtnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlogtnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlogtnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwloltnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwloltnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ltnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwloltnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwloltnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwloltnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwloltnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.ltnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwloltnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwloltnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlonenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlonenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.nenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlonenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlonenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlonenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlonenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.nenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlonenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlonenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwloeqnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwloeqnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.eqnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwloeqnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwloeqnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwloeqnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwloeqnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.eqnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwloeqnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwloeqnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlogenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlogenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.genan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlogenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlogenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlogenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlogenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.genan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlogenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlogenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlolenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlolenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.lenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlolenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlolenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwlolenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwlolenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vfmk.w.lenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwlolenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwlolenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupgt_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupgt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.gt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupgt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupgt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupgt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupgt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.gt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupgt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupgt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwuplt_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwuplt_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.lt %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwuplt.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwuplt.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwuplt_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwuplt_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.lt %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwuplt.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwuplt.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupne_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupne_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ne %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupne.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupne.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupne_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupne_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ne %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupne.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupne.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupeq_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupeq_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.eq %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupeq.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupeq.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupeq_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupeq_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.eq %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupeq.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupeq.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupge_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupge_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ge %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupge.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupge.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupge_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupge_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ge %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupge.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupge.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwuple_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwuple_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.le %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwuple.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwuple.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwuple_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwuple_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.le %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwuple.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwuple.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupnum_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupnum_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.num %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupnum.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupnum.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupnum_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupnum_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.num %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupnum.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupnum.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.nan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.nan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupgtnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupgtnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.gtnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupgtnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupgtnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupgtnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupgtnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.gtnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupgtnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupgtnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupltnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupltnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ltnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupltnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupltnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupltnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupltnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ltnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupltnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupltnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupnenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupnenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.nenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupnenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupnenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupnenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupnenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.nenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupnenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupnenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupeqnan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupeqnan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.eqnan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupeqnan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupeqnan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupeqnan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupeqnan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.eqnan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupeqnan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupeqnan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupgenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwupgenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.genan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupgenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupgenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwupgenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwupgenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.genan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwupgenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwupgenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwuplenan_mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwuplenan_mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.lenan %vm1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.pvfmkwuplenan.mvl(<256 x double> %0, i32 256)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwuplenan.mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @pvfmkwuplenan_mvml(<256 x double> %0, <256 x i1> %1) {
+; CHECK-LABEL: pvfmkwuplenan_mvml:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.lenan %vm1, %v0, %vm1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <256 x i1> @llvm.ve.vl.pvfmkwuplenan.mvml(<256 x double> %0, <256 x i1> %1, i32 256)
+  ret <256 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.pvfmkwuplenan.mvml(<256 x double>, <256 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksgt_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksgt_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.gt %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.gt %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksgt.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksgt.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksgt_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksgt_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.gt %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.gt %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksgt.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksgt.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkslt_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslt_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.lt %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.lt %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkslt.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkslt.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkslt_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkslt_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.lt %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.lt %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkslt.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkslt.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksne_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksne_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ne %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.ne %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksne.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksne.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksne_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksne_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ne %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.ne %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksne.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksne.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkseq_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkseq_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.eq %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.eq %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkseq.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkseq.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkseq_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkseq_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.eq %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.eq %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkseq.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkseq.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksge_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksge_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ge %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.ge %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksge.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksge.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksge_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksge_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ge %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.ge %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksge.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksge.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksle_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksle_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.le %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.le %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksle.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksle.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksle_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksle_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.le %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.le %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksle.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksle.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksnum_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksnum_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.num %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.num %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksnum.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksnum.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksnum_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksnum_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.num %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.num %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksnum.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksnum.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksnan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksnan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.nan %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.nan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksnan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksnan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksnan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksnan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.nan %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.nan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksnan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksnan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksgtnan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksgtnan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.gtnan %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.gtnan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksgtnan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksgtnan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksgtnan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksgtnan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.gtnan %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.gtnan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksgtnan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksgtnan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksltnan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksltnan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ltnan %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.ltnan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksltnan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksltnan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksltnan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksltnan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.ltnan %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.ltnan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksltnan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksltnan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksnenan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksnenan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.nenan %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.nenan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksnenan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksnenan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksnenan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksnenan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.nenan %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.nenan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksnenan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksnenan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkseqnan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkseqnan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.eqnan %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.eqnan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkseqnan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkseqnan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkseqnan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkseqnan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.eqnan %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.eqnan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkseqnan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkseqnan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksgenan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmksgenan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.genan %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.genan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmksgenan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksgenan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmksgenan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmksgenan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.genan %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.genan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmksgenan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmksgenan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkslenan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkslenan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.lenan %vm2, %v0
+; CHECK-NEXT:    pvfmk.s.lo.lenan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkslenan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkslenan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkslenan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkslenan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.s.up.lenan %vm2, %v0, %vm2
+; CHECK-NEXT:    pvfmk.s.lo.lenan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkslenan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkslenan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwgt_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwgt_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.gt %vm2, %v0
+; CHECK-NEXT:    vfmk.w.gt %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwgt.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwgt.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwgt_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwgt_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.gt %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.gt %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwgt.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwgt.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwlt_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlt_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.lt %vm2, %v0
+; CHECK-NEXT:    vfmk.w.lt %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwlt.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwlt.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwlt_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwlt_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.lt %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.lt %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwlt.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwlt.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwne_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwne_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ne %vm2, %v0
+; CHECK-NEXT:    vfmk.w.ne %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwne.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwne.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwne_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwne_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ne %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.ne %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwne.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwne.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkweq_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkweq_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.eq %vm2, %v0
+; CHECK-NEXT:    vfmk.w.eq %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkweq.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkweq.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkweq_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkweq_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.eq %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.eq %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkweq.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkweq.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwge_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwge_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ge %vm2, %v0
+; CHECK-NEXT:    vfmk.w.ge %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwge.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwge.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwge_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwge_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ge %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.ge %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwge.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwge.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwle_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwle_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.le %vm2, %v0
+; CHECK-NEXT:    vfmk.w.le %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwle.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwle.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwle_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwle_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.le %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.le %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwle.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwle.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwnum_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwnum_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.num %vm2, %v0
+; CHECK-NEXT:    vfmk.w.num %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwnum.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwnum.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwnum_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwnum_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.num %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.num %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwnum.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwnum.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwnan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwnan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.nan %vm2, %v0
+; CHECK-NEXT:    vfmk.w.nan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwnan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwnan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwnan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwnan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.nan %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.nan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwnan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwnan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwgtnan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwgtnan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.gtnan %vm2, %v0
+; CHECK-NEXT:    vfmk.w.gtnan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwgtnan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwgtnan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwgtnan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwgtnan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.gtnan %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.gtnan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwgtnan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwgtnan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwltnan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwltnan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ltnan %vm2, %v0
+; CHECK-NEXT:    vfmk.w.ltnan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwltnan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwltnan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwltnan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwltnan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.ltnan %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.ltnan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwltnan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwltnan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwnenan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwnenan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.nenan %vm2, %v0
+; CHECK-NEXT:    vfmk.w.nenan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwnenan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwnenan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwnenan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwnenan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.nenan %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.nenan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwnenan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwnenan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkweqnan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkweqnan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.eqnan %vm2, %v0
+; CHECK-NEXT:    vfmk.w.eqnan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkweqnan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkweqnan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkweqnan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkweqnan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.eqnan %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.eqnan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkweqnan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkweqnan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwgenan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwgenan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.genan %vm2, %v0
+; CHECK-NEXT:    vfmk.w.genan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwgenan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwgenan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwgenan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwgenan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.genan %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.genan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwgenan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwgenan.MvMl(<256 x double>, <512 x i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwlenan_Mvl(<256 x double> %0) {
+; CHECK-LABEL: pvfmkwlenan_Mvl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.lenan %vm2, %v0
+; CHECK-NEXT:    vfmk.w.lenan %vm3, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %2 = tail call <512 x i1> @llvm.ve.vl.pvfmkwlenan.Mvl(<256 x double> %0, i32 256)
+  ret <512 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwlenan.Mvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @pvfmkwlenan_MvMl(<256 x double> %0, <512 x i1> %1) {
+; CHECK-LABEL: pvfmkwlenan_MvMl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvfmk.w.up.lenan %vm2, %v0, %vm2
+; CHECK-NEXT:    vfmk.w.lenan %vm3, %v0, %vm3
+; CHECK-NEXT:    b.l.t (, %s10)
+  %3 = tail call <512 x i1> @llvm.ve.vl.pvfmkwlenan.MvMl(<256 x double> %0, <512 x i1> %1, i32 256)
+  ret <512 x i1> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <512 x i1> @llvm.ve.vl.pvfmkwlenan.MvMl(<256 x double>, <512 x i1>, i32)