[VE] Optimize prologue/epilogue instructions

[kaz7]

Summary

Optimize eliminate FP mechanism. This time optimize a function which has
no call but fixed stack objects. LLVM eliminates FP on such functions now.
Also, optimize GOT/PLT registers save/restore instructions if a given
function doesn't uses them. In addition, remove generating mechanism of
.cfi instructions since those are taken from other architectures and not
inspected yet. Update regression tests, also.

llvm/lib/Target/VE/VEFrameLowering.h

void emitEpilogueInsns(MachineFunction &MF, MachineBasicBlock &MBB,
                          bool RequireFPUpdate) const;
 
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I) const override;
 
   bool hasFP(const MachineFunction &MF) const override;
   bool hasBP(const MachineFunction &MF) const;
+  bool hasGOT(const MachineFunction &MF) const;
 
   // VE reserves argument space always for call sites in the function
   // immediately on entry of the current function.
   bool hasReservedCallFrame(const MachineFunction &MF) const override {
     return true;
   }
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS = nullptr) const override;

llvm/lib/Target/VE/VEFrameLowering.cpp

: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(16), 0,
                           Align(16)),
       STI(ST) {}
 
 void VEFrameLowering::emitPrologueInsns(MachineFunction &MF,
                                         MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MBBI,
                                         uint64_t NumBytes,
                                         bool RequireFPUpdate) const {
+  const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
   DebugLoc DL;
-  const VEInstrInfo &TII =
-      *static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo());
+  const VEInstrInfo &TII = *STI.getInstrInfo();
 
   // Insert following codes here as prologue
   //
-  //    st %fp, 0(,%sp)
-  //    st %lr, 8(,%sp)
-  //    st %got, 24(,%sp)
-  //    st %plt, 32(,%sp)
-  //    st %s17, 40(,%sp) iff this function is using s17 as BP
-  //    or %fp, 0, %sp
+  //    st %fp, 0(, %sp)   iff !isLeafProc
+  //    st %lr, 8(, %sp)   iff !isLeafProc
+  //    st %got, 24(, %sp) iff hasGOT
+  //    st %plt, 32(, %sp) iff hasGOT
+  //    st %s17, 40(, %sp) iff hasBP
+  if (!FuncInfo->isLeafProc()) {
     BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(0)
         .addReg(VE::SX9);
     BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(8)
         .addReg(VE::SX10);
+  }
+  if (hasGOT(MF)) {
     BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(24)
         .addReg(VE::SX15);
     BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(32)
         .addReg(VE::SX16);
+  }
   if (hasBP(MF))
     BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(40)
         .addReg(VE::SX17);
-  BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX9).addReg(VE::SX11).addImm(0);
 }
 
 void VEFrameLowering::emitEpilogueInsns(MachineFunction &MF,
                                         MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MBBI,
                                         uint64_t NumBytes,
                                         bool RequireFPUpdate) const {
+  const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
   DebugLoc DL;
-  const VEInstrInfo &TII =
-      *static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo());
+  const VEInstrInfo &TII = *STI.getInstrInfo();
 
   // Insert following codes here as epilogue
   //
-  //    or %sp, 0, %fp
-  //    ld %s17, 40(,%sp) iff this function is using s17 as BP
-  //    ld %plt, 32(,%sp)
-  //    ld %got, 24(,%sp)
-  //    ld %lr, 8(,%sp)
-  //    ld %fp, 0(,%sp)
-  BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX11).addReg(VE::SX9).addImm(0);
+  //    ld %s17, 40(, %sp) iff hasBP
+  //    ld %plt, 32(, %sp) iff hasGOT
+  //    ld %got, 24(, %sp) iff hasGOT
+  //    ld %lr, 8(, %sp)   iff !isLeafProc
+  //    ld %fp, 0(, %sp)   iff !isLeafProc
   if (hasBP(MF))
     BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17)
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(40);
+  if (hasGOT(MF)) {
     BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16)
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(32);
     BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15)
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(24);
+  }
+  if (!FuncInfo->isLeafProc()) {
     BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10)
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(8);
     BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9)
         .addReg(VE::SX11)
         .addImm(0)
         .addImm(0);
   }
+}
 
 void VEFrameLowering::emitSPAdjustment(MachineFunction &MF,
                                        MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MBBI,
                                        int64_t NumBytes,
                                        MaybeAlign MaybeAlign) const {
   DebugLoc DL;
   const VEInstrInfo &TII = *STI.getInstrInfo();
BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX11)
         .addReg(VE::SX11)
         .addImm(M1(64 - Log2_64(MaybeAlign.valueOrOne().value())));
   }
 }
 
 void VEFrameLowering::emitSPExtend(MachineFunction &MF, MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MBBI) const {
   DebugLoc DL;
-  const VEInstrInfo &TII =
-      *static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo());
+  const VEInstrInfo &TII = *STI.getInstrInfo();
 
   // Emit following codes.  It is not possible to insert multiple
   // BasicBlocks in PEI pass, so we emit two pseudo instructions here.
   //
   //   EXTEND_STACK                     // pseudo instrcution
   //   EXTEND_STACK_GUARD               // pseudo instrcution
   //
   // EXTEND_STACK pseudo will be converted by ExpandPostRA pass into
void VEFrameLowering::emitPrologue(MachineFunction &MF,
   // poor, but fixing that bogosity is going to be a large project.
   // For now, just see if it's lied, and report an error here.
   if (!NeedsStackRealignment && MFI.getMaxAlign() > getStackAlign())
     report_fatal_error("Function \"" + Twine(MF.getName()) +
                        "\" required "
                        "stack re-alignment, but LLVM couldn't handle it "
                        "(probably because it has a dynamic alloca).");
 
-  // Get the number of bytes to allocate from the FrameInfo
+  // Get the number of bytes to allocate from the FrameInfo.
+  // This number of bytes is already aligned to ABI stack alignment.
   uint64_t NumBytes = MFI.getStackSize();
 
-  // The VE ABI requires a reserved area at the top of stack as described
-  // in VESubtarget.cpp.  So, we adjust it here.
+  // Adjust stack size if this function is not a leaf function since the
+  // VE ABI requires a reserved area at the top of stack as described in
+  // VEFrameLowering.cpp.
+  if (!FuncInfo->isLeafProc()) {
+    // NOTE: The number is aligned to ABI stack alignment after adjustment.
     NumBytes = STI.getAdjustedFrameSize(NumBytes);
+  }
 
   // Finally, ensure that the size is sufficiently aligned for the
   // data on the stack.
   NumBytes = alignTo(NumBytes, MFI.getMaxAlign());
 
   // Update stack size with corrected value.
   MFI.setStackSize(NumBytes);
 
-  if (FuncInfo->isLeafProc())
-    return;
-
   // Emit Prologue instructions to save multiple registers.
   emitPrologueInsns(MF, MBB, MBBI, NumBytes, true);
 
+  // Emit instructions to save SP in FP as follows if this is not a leaf
+  // function:
+  //    or %fp, 0, %sp
+  if (!FuncInfo->isLeafProc())
+    BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX9)
+        .addReg(VE::SX11)
+        .addImm(0);
+
   // Emit stack adjust instructions
   MaybeAlign RuntimeAlign =
       NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : None;
+  assert((RuntimeAlign == None || !FuncInfo->isLeafProc()) &&
+         "SP has to be saved in order to align variable sized stack object!");
   emitSPAdjustment(MF, MBB, MBBI, -(int64_t)NumBytes, RuntimeAlign);
 
   if (hasBP(MF)) {
     // Copy SP to BP.
     BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX17)
         .addReg(VE::SX11)
         .addImm(0);
   }
 
   // Emit stack extend instructions
+  if (NumBytes != 0)
     emitSPExtend(MF, MBB, MBBI);
-
-  Register RegFP = RegInfo.getDwarfRegNum(VE::SX9, true);
-
-  // Emit ".cfi_def_cfa_register 30".
-  unsigned CFIIndex =
-      MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, RegFP));
-  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
-      .addCFIIndex(CFIIndex);
-
-  // Emit ".cfi_window_save".
-  CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
-  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
-      .addCFIIndex(CFIIndex);
 }
 
 MachineBasicBlock::iterator VEFrameLowering::eliminateCallFramePseudoInstr(
     MachineFunction &MF, MachineBasicBlock &MBB,
     MachineBasicBlock::iterator I) const {
   if (!hasReservedCallFrame(MF)) {
     MachineInstr &MI = *I;
     int64_t Size = MI.getOperand(0).getImm();
     if (MI.getOpcode() == VE::ADJCALLSTACKDOWN)
       Size = -Size;
 
     if (Size)
       emitSPAdjustment(MF, MBB, I, Size);
   }
   return MBB.erase(I);
 }
 
 void VEFrameLowering::emitEpilogue(MachineFunction &MF,
                                    MachineBasicBlock &MBB) const {
   const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
+  DebugLoc DL;
   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
   MachineFrameInfo &MFI = MF.getFrameInfo();
+  const VEInstrInfo &TII = *STI.getInstrInfo();
 
   uint64_t NumBytes = MFI.getStackSize();
 
-  if (FuncInfo->isLeafProc())
-    return;
+  // Emit instructions to retrieve original SP.
+  if (!FuncInfo->isLeafProc()) {
+    // If SP is saved in FP, retrieve it as follows:
+    //    or %sp, 0, %fp     iff !isLeafProc
+    BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX11)
+        .addReg(VE::SX9)
+        .addImm(0);
+  } else {
+    // Emit stack adjust instructions.
+    emitSPAdjustment(MF, MBB, MBBI, NumBytes, None);
+  }
 
   // Emit Epilogue instructions to restore multiple registers.
   emitEpilogueInsns(MF, MBB, MBBI, NumBytes, true);
 }
 
 // hasFP - Return true if the specified function should have a dedicated frame
 // pointer register.  This is true if the function has variable sized allocas
 // or if frame pointer elimination is disabled.
 bool VEFrameLowering::hasFP(const MachineFunction &MF) const {
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
 
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
          RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
          MFI.isFrameAddressTaken();
 }
 
 bool VEFrameLowering::hasBP(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
   return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);
 }
 
+bool VEFrameLowering::hasGOT(const MachineFunction &MF) const {
+  const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
+
+  // If a global base register is assigned (!= 0), GOT is used.
+  return FuncInfo->getGlobalBaseReg() != 0;
+}
+
 StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF,
                                                     int FI,
                                                     Register &FrameReg) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const VERegisterInfo *RegInfo = STI.getRegisterInfo();
   bool isFixed = MFI.isFixedObjectIndex(FI);
 
   int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI);
return !MFI.hasCalls()                 // No calls
          && !MRI.isPhysRegUsed(VE::SX11) // %sp un-used
          && !hasFP(MF);                  // Don't need %fp
 }
 
 void VEFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                            BitVector &SavedRegs,
                                            RegScavenger *RS) const {
   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
-  const MachineFrameInfo &MFI = MF.getFrameInfo();
 
   // Functions having BP or stack objects need to emit prologue and epilogue
   // to allocate local buffer on the stack.
-  if (isLeafProc(MF) && !hasBP(MF) && !MFI.hasStackObjects()) {
+  if (isLeafProc(MF) && !hasBP(MF)) {
     VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
     FuncInfo->setLeafProc(true);
   }
 }

llvm/test/CodeGen/VE/Scalar/callee.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define i32 @stack_stack_arg_i32_r9(i1 %0, i8 %1, i16 %2, i32 %3, i64 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9) {
 ; CHECK-LABEL: stack_stack_arg_i32_r9:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 424(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ldl.sx %s0, 248(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret i32 %9
 }
 
 define i64 @stack_stack_arg_i64_r9(i1 %0, i8 %1, i16 %2, i32 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8, i64 %9) {
 ; CHECK-LABEL: stack_stack_arg_i64_r9:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 424(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ld %s0, 248(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret i64 %9
 }
 
 define float @stack_stack_arg_f32_r9(float %p0, float %p1, float %p2, float %p3, float %p4, float %p5, float %p6, float %p7, float %s0, float %s1) {
 ; CHECK-LABEL: stack_stack_arg_f32_r9:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldu %s0, 428(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ldu %s0, 252(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret float %s1
 }
 
 define i32 @stack_stack_arg_i32f32_r8(i32 %p0, float %p1, i32 %p2, float %p3, i32 %p4, float %p5, i32 %p6, float %p7, i32 %s0, float %s1) {
 ; CHECK-LABEL: stack_stack_arg_i32f32_r8:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 416(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ldl.sx %s0, 240(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret i32 %s0
 }
 
 define float @stack_stack_arg_i32f32_r9(i32 %p0, float %p1, i32 %p2, float %p3, i32 %p4, float %p5, i32 %p6, float %p7, i32 %s0, float %s1) {
 ; CHECK-LABEL: stack_stack_arg_i32f32_r9:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldu %s0, 428(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ldu %s0, 252(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret float %s1
 }

llvm/test/CodeGen/VE/Scalar/fabs.ll

 
 ; Function Attrs: nounwind readnone speculatable willreturn
 declare double @llvm.fabs.f64(double)
 
 ; Function Attrs: nounwind readnone
 define fp128 @fabs_quad_var(fp128 %0) {
 ; CHECK-LABEL: fabs_quad_var:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s1, 176(, %s11)
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
+; CHECK-NEXT:    st %s1, (, %s11)
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
 ; CHECK-NEXT:    and %s0, %s0, (57)0
-; CHECK-NEXT:    st1b %s0, 191(, %s11)
-; CHECK-NEXT:    ld %s1, 176(, %s11)
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, 15(, %s11)
+; CHECK-NEXT:    ld %s1, (, %s11)
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %2 = tail call fast fp128 @llvm.fabs.f128(fp128 %0)
   ret fp128 %2
 }
 
 ; Function Attrs: nounwind readnone speculatable willreturn
 declare fp128 @llvm.fabs.f128(fp128)
 
 ; Function Attrs: norecurse nounwind readnone

llvm/test/CodeGen/VE/Scalar/fcopysign.ll

 
 ; Function Attrs: nounwind readnone speculatable willreturn
 declare double @llvm.copysign.f64(double, double)
 
 ; Function Attrs: nounwind readnone
 define fp128 @copysign_quad_var(fp128 %0, fp128 %1) {
 ; CHECK-LABEL: copysign_quad_var:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s3, 192(, %s11)
-; CHECK-NEXT:    st %s2, 200(, %s11)
-; CHECK-NEXT:    st %s1, 176(, %s11)
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    ld1b.zx %s0, 207(, %s11)
-; CHECK-NEXT:    ld1b.zx %s1, 191(, %s11)
+; CHECK-NEXT:    st %s3, 16(, %s11)
+; CHECK-NEXT:    st %s2, 24(, %s11)
+; CHECK-NEXT:    st %s1, (, %s11)
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 31(, %s11)
+; CHECK-NEXT:    ld1b.zx %s1, 15(, %s11)
 ; CHECK-NEXT:    lea %s2, 128
 ; CHECK-NEXT:    and %s0, %s0, %s2
 ; CHECK-NEXT:    and %s1, %s1, (57)0
 ; CHECK-NEXT:    or %s0, %s1, %s0
-; CHECK-NEXT:    st1b %s0, 191(, %s11)
-; CHECK-NEXT:    ld %s1, 176(, %s11)
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, 15(, %s11)
+; CHECK-NEXT:    ld %s1, (, %s11)
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 32, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %3 = tail call fast fp128 @llvm.copysign.f128(fp128 %0, fp128 %1)
   ret fp128 %3
 }
 
 ; Function Attrs: nounwind readnone speculatable willreturn
 declare fp128 @llvm.copysign.f128(fp128, fp128)
 
 ; Function Attrs: nounwind readnone

 define fp128 @copysign_quad_zero(fp128 %0) {
 ; CHECK-LABEL: copysign_quad_zero:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, .LCPI{{[0-9]+}}_0@lo
 ; CHECK-NEXT:    and %s2, %s2, (32)0
 ; CHECK-NEXT:    lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
 ; CHECK-NEXT:    ld %s4, 8(, %s2)
 ; CHECK-NEXT:    ld %s5, (, %s2)
-; CHECK-NEXT:    st %s1, 192(, %s11)
-; CHECK-NEXT:    st %s0, 200(, %s11)
-; CHECK-NEXT:    st %s5, 176(, %s11)
-; CHECK-NEXT:    st %s4, 184(, %s11)
-; CHECK-NEXT:    ld1b.zx %s0, 207(, %s11)
-; CHECK-NEXT:    ld1b.zx %s1, 191(, %s11)
+; CHECK-NEXT:    st %s1, 16(, %s11)
+; CHECK-NEXT:    st %s0, 24(, %s11)
+; CHECK-NEXT:    st %s5, (, %s11)
+; CHECK-NEXT:    st %s4, 8(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 31(, %s11)
+; CHECK-NEXT:    ld1b.zx %s1, 15(, %s11)
 ; CHECK-NEXT:    lea %s2, 128
 ; CHECK-NEXT:    and %s0, %s0, %s2
 ; CHECK-NEXT:    and %s1, %s1, (57)0
 ; CHECK-NEXT:    or %s0, %s1, %s0
-; CHECK-NEXT:    st1b %s0, 191(, %s11)
-; CHECK-NEXT:    ld %s1, 176(, %s11)
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, 15(, %s11)
+; CHECK-NEXT:    ld %s1, (, %s11)
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 32, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %2 = tail call fast fp128 @llvm.copysign.f128(fp128 0xL00000000000000000000000000000000, fp128 %0)
   ret fp128 %2
 }
 
 ; Function Attrs: nounwind readnone
 define float @copysign_float_const(float %0) {
 ; CHECK-LABEL: copysign_float_const:
 ; CHECK:       # %bb.0:

 define fp128 @copysign_quad_const(fp128 %0) {
 ; CHECK-LABEL: copysign_quad_const:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s2, .LCPI{{[0-9]+}}_0@lo
 ; CHECK-NEXT:    and %s2, %s2, (32)0
 ; CHECK-NEXT:    lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
 ; CHECK-NEXT:    ld %s4, 8(, %s2)
 ; CHECK-NEXT:    ld %s5, (, %s2)
-; CHECK-NEXT:    st %s1, 192(, %s11)
-; CHECK-NEXT:    st %s0, 200(, %s11)
-; CHECK-NEXT:    st %s5, 176(, %s11)
-; CHECK-NEXT:    st %s4, 184(, %s11)
-; CHECK-NEXT:    ld1b.zx %s0, 207(, %s11)
-; CHECK-NEXT:    ld1b.zx %s1, 191(, %s11)
+; CHECK-NEXT:    st %s1, 16(, %s11)
+; CHECK-NEXT:    st %s0, 24(, %s11)
+; CHECK-NEXT:    st %s5, (, %s11)
+; CHECK-NEXT:    st %s4, 8(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 31(, %s11)
+; CHECK-NEXT:    ld1b.zx %s1, 15(, %s11)
 ; CHECK-NEXT:    lea %s2, 128
 ; CHECK-NEXT:    and %s0, %s0, %s2
 ; CHECK-NEXT:    and %s1, %s1, (57)0
 ; CHECK-NEXT:    or %s0, %s1, %s0
-; CHECK-NEXT:    st1b %s0, 191(, %s11)
-; CHECK-NEXT:    ld %s1, 176(, %s11)
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, 15(, %s11)
+; CHECK-NEXT:    ld %s1, (, %s11)
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 32, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %2 = tail call fast fp128 @llvm.copysign.f128(fp128 0xL0000000000000000C000000000000000, fp128 %0)
   ret fp128 %2
 }

llvm/test/CodeGen/VE/Scalar/fp_fneg.ll

; CHECK-NEXT:    b.l.t (, %s10)
   %2 = fneg double %0
   ret double %2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @fneg_quad(fp128 %0) {
 ; CHECK-LABEL: fneg_quad:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s1, 176(, %s11)
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
+; CHECK-NEXT:    st %s1, (, %s11)
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
 ; CHECK-NEXT:    lea %s1, 128
 ; CHECK-NEXT:    xor %s0, %s0, %s1
-; CHECK-NEXT:    st1b %s0, 191(, %s11)
-; CHECK-NEXT:    ld %s1, 176(, %s11)
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, 15(, %s11)
+; CHECK-NEXT:    ld %s1, (, %s11)
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %2 = fneg fp128 %0
   ret fp128 %2
 }

llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll

; PIC-NEXT:    b.l.t (, %s10)
 
   %v = load i8, i8* @vi8, align 1
   ret i8 %v
 }
 
 define i32 @func_alloca(i32 signext %0) {
 ; CHECK-LABEL: func_alloca:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -192(, %s11)
+; CHECK-NEXT:    adds.l %s11, -16, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB2_2:
-; CHECK-NEXT:    stl %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    stl %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: func_alloca:
 ; PIC:       # %bb.0:
-; PIC-NEXT:    st %s9, (, %s11)
-; PIC-NEXT:    st %s10, 8(, %s11)
-; PIC-NEXT:    st %s15, 24(, %s11)
-; PIC-NEXT:    st %s16, 32(, %s11)
-; PIC-NEXT:    or %s9, 0, %s11
-; PIC-NEXT:    lea %s11, -192(, %s11)
+; PIC-NEXT:    adds.l %s11, -16, %s11
 ; PIC-NEXT:    brge.l.t %s11, %s8, .LBB2_2
 ; PIC-NEXT:  # %bb.1:
 ; PIC-NEXT:    ld %s61, 24(, %s14)
 ; PIC-NEXT:    or %s62, 0, %s0
 ; PIC-NEXT:    lea %s63, 315
 ; PIC-NEXT:    shm.l %s63, (%s61)
 ; PIC-NEXT:    shm.l %s8, 8(%s61)
 ; PIC-NEXT:    shm.l %s11, 16(%s61)
 ; PIC-NEXT:    monc
 ; PIC-NEXT:    or %s0, 0, %s62
 ; PIC-NEXT:  .LBB2_2:
-; PIC-NEXT:    stl %s0, 188(, %s11)
-; PIC-NEXT:    or %s11, 0, %s9
-; PIC-NEXT:    ld %s16, 32(, %s11)
-; PIC-NEXT:    ld %s15, 24(, %s11)
-; PIC-NEXT:    ld %s10, 8(, %s11)
-; PIC-NEXT:    ld %s9, (, %s11)
+; PIC-NEXT:    stl %s0, 12(, %s11)
+; PIC-NEXT:    adds.l %s11, 16, %s11
 ; PIC-NEXT:    b.l.t (, %s10)
   %2 = alloca i32, align 4
   store i32 %0, i32* %2, align 4
   %3 = load i32, i32* %2, align 4
   ret i32 %3
 }

llvm/test/CodeGen/VE/Scalar/load-align1.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 @vi8 = common dso_local local_unnamed_addr global i8 0, align 1
 @vi16 = common dso_local local_unnamed_addr global i16 0, align 1
 @vi32 = common dso_local local_unnamed_addr global i32 0, align 1
 @vi64 = common dso_local local_unnamed_addr global i64 0, align 1
 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 1
 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 1
 
 ; Function Attrs: norecurse nounwind readonly
 define double @loadf64stk() {
 ; CHECK-LABEL: loadf64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 1
   %1 = load double, double* %addr, align 1
   ret double %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define float @loadf32stk() {
 ; CHECK-LABEL: loadf32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldu %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldu %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 1
   %1 = load float, float* %addr, align 1
   ret float %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i64 @loadi64stk() {
 ; CHECK-LABEL: loadi64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 1
   %1 = load i64, i64* %addr, align 1
   ret i64 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i32 @loadi32stk() {
 ; CHECK-LABEL: loadi32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldl.sx %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 1
   %1 = load i32, i32* %addr, align 1
   ret i32 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i16 @loadi16stk() {
 ; CHECK-LABEL: loadi16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 1
   %1 = load i16, i16* %addr, align 1
   ret i16 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i8 @loadi8stk() {
 ; CHECK-LABEL: loadi8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 1
   %1 = load i8, i8* %addr, align 1
   ret i8 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define double @loadf64com() {
 ; CHECK-LABEL: loadf64com:

llvm/test/CodeGen/VE/Scalar/load-align2.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 @vi8 = common dso_local local_unnamed_addr global i8 0, align 2
 @vi16 = common dso_local local_unnamed_addr global i16 0, align 2
 @vi32 = common dso_local local_unnamed_addr global i32 0, align 2
 @vi64 = common dso_local local_unnamed_addr global i64 0, align 2
 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 2
 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 2
 
 ; Function Attrs: norecurse nounwind readonly
 define double @loadf64stk() {
 ; CHECK-LABEL: loadf64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 2
   %1 = load double, double* %addr, align 2
   ret double %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define float @loadf32stk() {
 ; CHECK-LABEL: loadf32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldu %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldu %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 2
   %1 = load float, float* %addr, align 2
   ret float %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i64 @loadi64stk() {
 ; CHECK-LABEL: loadi64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 2
   %1 = load i64, i64* %addr, align 2
   ret i64 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i32 @loadi32stk() {
 ; CHECK-LABEL: loadi32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldl.sx %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 2
   %1 = load i32, i32* %addr, align 2
   ret i32 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i16 @loadi16stk() {
 ; CHECK-LABEL: loadi16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 2
   %1 = load i16, i16* %addr, align 2
   ret i16 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i8 @loadi8stk() {
 ; CHECK-LABEL: loadi8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 2
   %1 = load i8, i8* %addr, align 2
   ret i8 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define double @loadf64com() {
 ; CHECK-LABEL: loadf64com:

llvm/test/CodeGen/VE/Scalar/load-align4.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 @vi8 = common dso_local local_unnamed_addr global i8 0, align 4
 @vi16 = common dso_local local_unnamed_addr global i16 0, align 4
 @vi32 = common dso_local local_unnamed_addr global i32 0, align 4
 @vi64 = common dso_local local_unnamed_addr global i64 0, align 4
 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 4
 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 4
 
 ; Function Attrs: norecurse nounwind readonly
 define double @loadf64stk() {
 ; CHECK-LABEL: loadf64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 4
   %1 = load double, double* %addr, align 4
   ret double %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define float @loadf32stk() {
 ; CHECK-LABEL: loadf32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldu %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldu %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 4
   %1 = load float, float* %addr, align 4
   ret float %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i64 @loadi64stk() {
 ; CHECK-LABEL: loadi64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 4
   %1 = load i64, i64* %addr, align 4
   ret i64 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i32 @loadi32stk() {
 ; CHECK-LABEL: loadi32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldl.sx %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 4
   %1 = load i32, i32* %addr, align 4
   ret i32 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i16 @loadi16stk() {
 ; CHECK-LABEL: loadi16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 4
   %1 = load i16, i16* %addr, align 4
   ret i16 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i8 @loadi8stk() {
 ; CHECK-LABEL: loadi8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 4
   %1 = load i8, i8* %addr, align 4
   ret i8 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define double @loadf64com() {
 ; CHECK-LABEL: loadf64com:

llvm/test/CodeGen/VE/Scalar/load-align8.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 @vi8 = common dso_local local_unnamed_addr global i8 0, align 8
 @vi16 = common dso_local local_unnamed_addr global i16 0, align 8
 @vi32 = common dso_local local_unnamed_addr global i32 0, align 8
 @vi64 = common dso_local local_unnamed_addr global i64 0, align 8
 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 8
 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 8
 
 ; Function Attrs: norecurse nounwind readonly
 define double @loadf64stk() {
 ; CHECK-LABEL: loadf64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 8
   %1 = load double, double* %addr, align 8
   ret double %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define float @loadf32stk() {
 ; CHECK-LABEL: loadf32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldu %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldu %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 8
   %1 = load float, float* %addr, align 8
   ret float %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i64 @loadi64stk() {
 ; CHECK-LABEL: loadi64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 8
   %1 = load i64, i64* %addr, align 8
   ret i64 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i32 @loadi32stk() {
 ; CHECK-LABEL: loadi32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldl.sx %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 8
   %1 = load i32, i32* %addr, align 8
   ret i32 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i16 @loadi16stk() {
 ; CHECK-LABEL: loadi16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 8
   %1 = load i16, i16* %addr, align 8
   ret i16 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i8 @loadi8stk() {
 ; CHECK-LABEL: loadi8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 8
   %1 = load i8, i8* %addr, align 8
   ret i8 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define double @loadf64com() {
 ; CHECK-LABEL: loadf64com:

llvm/test/CodeGen/VE/Scalar/load.ll

; CHECK-NEXT:    b.l.t (, %s10)
   %3 = zext i8 %2 to i64
   ret i64 %3
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @loadf128stk() {
 ; CHECK-LABEL: loadf128stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s1, 176(, %s11)
-; CHECK-NEXT:    ld %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s1, (, %s11)
+; CHECK-NEXT:    ld %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca fp128, align 16
   %1 = load fp128, fp128* %addr, align 16
   ret fp128 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define double @loadf64stk() {
 ; CHECK-LABEL: loadf64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 16
   %1 = load double, double* %addr, align 16
   ret double %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define float @loadf32stk() {
 ; CHECK-LABEL: loadf32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldu %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldu %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 16
   %1 = load float, float* %addr, align 16
   ret float %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i128 @loadi128stk() {
 ; CHECK-LABEL: loadi128stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 176(, %s11)
-; CHECK-NEXT:    ld %s1, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, (, %s11)
+; CHECK-NEXT:    ld %s1, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i128, align 16
   %1 = load i128, i128* %addr, align 16
   ret i128 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i64 @loadi64stk() {
 ; CHECK-LABEL: loadi64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 16
   %1 = load i64, i64* %addr, align 16
   ret i64 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i32 @loadi32stk() {
 ; CHECK-LABEL: loadi32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldl.sx %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 16
   %1 = load i32, i32* %addr, align 16
   ret i32 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i16 @loadi16stk() {
 ; CHECK-LABEL: loadi16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 16
   %1 = load i16, i16* %addr, align 16
   ret i16 %1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define i8 @loadi8stk() {
 ; CHECK-LABEL: loadi8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 16
   %1 = load i8, i8* %addr, align 16
   ret i8 %1
 }

llvm/test/CodeGen/VE/Scalar/loadrri.ll

 }
 
 ; Function Attrs: nounwind
 define signext i8 @func_fr(%struct.data* readonly %0, i32 signext %1) {
 ; CHECK-LABEL: func_fr:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sll %s1, %s1, 2
 ; CHECK-NEXT:    ldl.sx %s0, (%s1, %s0)
-; CHECK-NEXT:    stl %s0, 184(%s1, %s11)
-; CHECK-NEXT:    ld1b.sx %s0, 184(%s1, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stl %s0, 8(%s1, %s11)
+; CHECK-NEXT:    ld1b.sx %s0, 8(%s1, %s11)
+; CHECK-NEXT:    adds.l %s11, 48, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %3 = alloca [10 x %struct.data], align 1
   %4 = getelementptr inbounds [10 x %struct.data], [10 x %struct.data]* %3, i64 0, i64 0, i32 0, i64 0
   call void @llvm.lifetime.start.p0i8(i64 40, i8* nonnull %4)
   %5 = sext i32 %1 to i64
   %6 = getelementptr inbounds [10 x %struct.data], [10 x %struct.data]* %3, i64 0, i64 %5, i32 0, i64 0
   %7 = getelementptr inbounds %struct.data, %struct.data* %0, i64 %5, i32 0, i64 0
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 %6, i8* align 1 %7, i64 4, i1 true)
   %8 = load volatile i8, i8* %6, align 1
   call void @llvm.lifetime.end.p0i8(i64 40, i8* nonnull %4)
   ret i8 %8
 }
 
 declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
 declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
 
 %"basic_string" = type { %union.anon.3, [23 x i8] }
 %union.anon.3 = type { i8 }
 
 define signext i8 @func_rf(i8* readonly %0, i64 %1, i32 signext %2) {
 ; CHECK-LABEL: func_rf:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.sx %s0, 184(%s1, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.sx %s0, 8(%s1, %s11)
+; CHECK-NEXT:    adds.l %s11, 32, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %buf = alloca %"basic_string", align 8
 
   %sub631 = add nsw i64 %1, -1
   %add.ptr.i = getelementptr inbounds %"basic_string", %"basic_string"* %buf, i64 0, i32 1, i64 %sub631
   %ret = load i8, i8* %add.ptr.i, align 1
   ret i8 %ret
 }

llvm/test/CodeGen/VE/Scalar/sext_zext_load.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define signext i16 @func1() {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.sx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.sx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = sext i8 %a.val to i16
   ret i16 %a.conv
 }
 
 define i32 @func2() {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.sx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.sx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = sext i8 %a.val to i32
   ret i32 %a.conv
 }
 
 define i64 @func3() {
 ; CHECK-LABEL: func3:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.sx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.sx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = sext i8 %a.val to i64
   ret i64 %a.conv
 }
 
 define zeroext i16 @func5() {
 ; CHECK-LABEL: func5:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.sx %s0, 191(, %s11)
+; CHECK-NEXT:    ld1b.sx %s0, 15(, %s11)
 ; CHECK-NEXT:    and %s0, %s0, (48)0
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = sext i8 %a.val to i16
   ret i16 %a.conv
 }
 
 define i32 @func6() {
 ; CHECK-LABEL: func6:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.sx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.sx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = sext i8 %a.val to i32
   ret i32 %a.conv
 }
 
 define i64 @func7() {
 ; CHECK-LABEL: func7:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.sx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.sx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = sext i8 %a.val to i64
   ret i64 %a.conv
 }
 
 define signext i16 @func9() {
 ; CHECK-LABEL: func9:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = zext i8 %a.val to i16
   ret i16 %a.conv
 }
 
 define i32 @func10() {
 ; CHECK-LABEL: func10:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = zext i8 %a.val to i32
   ret i32 %a.conv
 }
 
 define i64 @func11() {
 ; CHECK-LABEL: func11:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = zext i8 %a.val to i64
   ret i64 %a.conv
 }
 
 define zeroext i16 @func13() {
 ; CHECK-LABEL: func13:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = zext i8 %a.val to i16
   ret i16 %a.conv
 }
 
 define zeroext i16 @func14() {
 ; CHECK-LABEL: func14:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = zext i8 %a.val to i16
   ret i16 %a.conv
 }
 
 define i64 @func15() {
 ; CHECK-LABEL: func15:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i8, align 1
   %a.val = load i8, i8* %a, align 1
   %a.conv = zext i8 %a.val to i64
   ret i64 %a.conv
 }
 
 define i32 @func17() {
 ; CHECK-LABEL: func17:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.sx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.sx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i16, align 2
   %a.val = load i16, i16* %a, align 2
   %a.conv = sext i16 %a.val to i32
   ret i32 %a.conv
 }
 
 define i64 @func18() {
 ; CHECK-LABEL: func18:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.sx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.sx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i16, align 2
   %a.val = load i16, i16* %a, align 2
   %a.conv = sext i16 %a.val to i64
   ret i64 %a.conv
 }
 
 define zeroext i16 @func20() {
 ; CHECK-LABEL: func20:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i16, align 2
   %a.conv = load i16, i16* %a, align 2
   ret i16 %a.conv
 }
 
 define i64 @func21() {
 ; CHECK-LABEL: func21:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.sx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.sx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i16, align 2
   %a.val = load i16, i16* %a, align 2
   %a.conv = sext i16 %a.val to i64
   ret i64 %a.conv
 }
 
 define i32 @func23() {
 ; CHECK-LABEL: func23:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i16, align 2
   %a.val = load i16, i16* %a, align 2
   %a.conv = zext i16 %a.val to i32
   ret i32 %a.conv
 }
 
 define i64 @func24() {
 ; CHECK-LABEL: func24:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i16, align 2
   %a.val = load i16, i16* %a, align 2
   %a.conv = zext i16 %a.val to i64
   ret i64 %a.conv
 }
 
 define zeroext i16 @func26() {
 ; CHECK-LABEL: func26:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i16, align 2
   %a.conv = load i16, i16* %a, align 2
   ret i16 %a.conv
 }
 
 define i64 @func27() {
 ; CHECK-LABEL: func27:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld2b.zx %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld2b.zx %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i16, align 2
   %a.val = load i16, i16* %a, align 2
   %a.conv = zext i16 %a.val to i64
   ret i64 %a.conv
 }
 
 define i64 @func29() {
 ; CHECK-LABEL: func29:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldl.sx %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i32, align 4
   %a.val = load i32, i32* %a, align 4
   %a.conv = sext i32 %a.val to i64
   ret i64 %a.conv
 }
 
 define i64 @func31() {
 ; CHECK-LABEL: func31:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldl.sx %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i32, align 4
   %a.val = load i32, i32* %a, align 4
   %a.conv = sext i32 %a.val to i64
   ret i64 %a.conv
 }
 
 define i64 @func33() {
 ; CHECK-LABEL: func33:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.zx %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldl.zx %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i32, align 4
   %a.val = load i32, i32* %a, align 4
   %a.conv = zext i32 %a.val to i64
   ret i64 %a.conv
 }
 
 define i64 @func35() {
 ; CHECK-LABEL: func35:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.zx %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ldl.zx %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i32, align 4
   %a.val = load i32, i32* %a, align 4
   %a.conv = zext i32 %a.val to i64
   ret i64 %a.conv
 }
 
 define signext i8 @func37() {
 ; CHECK-LABEL: func37:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
 ; CHECK-NEXT:    sll %s0, %s0, 63
 ; CHECK-NEXT:    sra.l %s0, %s0, 63
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i1, align 1
   %a.val = load i1, i1* %a, align 1
   %a.conv = sext i1 %a.val to i8
   ret i8 %a.conv
 }
 
 define signext i16 @func38() {
 ; CHECK-LABEL: func38:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
 ; CHECK-NEXT:    sll %s0, %s0, 63
 ; CHECK-NEXT:    sra.l %s0, %s0, 63
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i1, align 1
   %a.val = load i1, i1* %a, align 1
   %a.conv = sext i1 %a.val to i16
   ret i16 %a.conv
 }
 
 define signext i32 @func39() {
 ; CHECK-LABEL: func39:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
 ; CHECK-NEXT:    sll %s0, %s0, 63
 ; CHECK-NEXT:    sra.l %s0, %s0, 63
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i1, align 1
   %a.val = load i1, i1* %a, align 1
   %a.conv = sext i1 %a.val to i32
   ret i32 %a.conv
 }
 
 define signext i64 @func40() {
 ; CHECK-LABEL: func40:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
 ; CHECK-NEXT:    sll %s0, %s0, 63
 ; CHECK-NEXT:    sra.l %s0, %s0, 63
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i1, align 1
   %a.val = load i1, i1* %a, align 1
   %a.conv = sext i1 %a.val to i64
   ret i64 %a.conv
 }
 
 define signext i8 @func42() {
 ; CHECK-LABEL: func42:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i1, align 1
   %a.val = load i1, i1* %a, align 1
   %a.conv = zext i1 %a.val to i8
   ret i8 %a.conv
 }
 
 define signext i16 @func43() {
 ; CHECK-LABEL: func43:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i1, align 1
   %a.val = load i1, i1* %a, align 1
   %a.conv = zext i1 %a.val to i16
   ret i16 %a.conv
 }
 
 define signext i32 @func44() {
 ; CHECK-LABEL: func44:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i1, align 1
   %a.val = load i1, i1* %a, align 1
   %a.conv = zext i1 %a.val to i32
   ret i32 %a.conv
 }
 
 define signext i64 @func45() {
 ; CHECK-LABEL: func45:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld1b.zx %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %a = alloca i1, align 1
   %a.val = load i1, i1* %a, align 1
   %a.conv = zext i1 %a.val to i64
   ret i64 %a.conv
 }

llvm/test/CodeGen/VE/Scalar/stackframe_align.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=ve | FileCheck %s
 ; RUN: llc < %s -mtriple=ve --frame-pointer=all \
 ; RUN:     | FileCheck %s --check-prefix=CHECKFP
 
 ;;; Check stack frame allocation with static and dynamic stack object with
 ;;; alignments as a test of getFrameIndexReference().
 
 ;; Allocated buffer places from 9 to 15 bytes in 16 bytes local vars area.
 
 ; Function Attrs: nounwind
 define i8* @test_frame7(i8* %0) {
 ; CHECK-LABEL: test_frame7:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -192(, %s11)
+; CHECK-NEXT:    adds.l %s11, -16, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 185(, %s11)
-; CHECK-NEXT:    st1b %s1, 185(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, 9(, %s11)
+; CHECK-NEXT:    st1b %s1, 9(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; CHECKFP-LABEL: test_frame7:
 ; CHECKFP:       # %bb.0:
 ; CHECKFP-NEXT:    st %s9, (, %s11)
 ; CHECKFP-NEXT:    st %s10, 8(, %s11)
-; CHECKFP-NEXT:    st %s15, 24(, %s11)
-; CHECKFP-NEXT:    st %s16, 32(, %s11)
 ; CHECKFP-NEXT:    or %s9, 0, %s11
 ; CHECKFP-NEXT:    lea %s11, -192(, %s11)
 ; CHECKFP-NEXT:    brge.l.t %s11, %s8, .LBB0_2
 ; CHECKFP-NEXT:  # %bb.1:
 ; CHECKFP-NEXT:    ld %s61, 24(, %s14)
 ; CHECKFP-NEXT:    or %s62, 0, %s0
 ; CHECKFP-NEXT:    lea %s63, 315
 ; CHECKFP-NEXT:    shm.l %s63, (%s61)
 ; CHECKFP-NEXT:    shm.l %s8, 8(%s61)
 ; CHECKFP-NEXT:    shm.l %s11, 16(%s61)
 ; CHECKFP-NEXT:    monc
 ; CHECKFP-NEXT:    or %s0, 0, %s62
 ; CHECKFP-NEXT:  .LBB0_2:
 ; CHECKFP-NEXT:    ld1b.zx %s1, (, %s0)
 ; CHECKFP-NEXT:    lea %s0, -7(, %s9)
 ; CHECKFP-NEXT:    st1b %s1, -7(, %s9)
 ; CHECKFP-NEXT:    or %s11, 0, %s9
-; CHECKFP-NEXT:    ld %s16, 32(, %s11)
-; CHECKFP-NEXT:    ld %s15, 24(, %s11)
 ; CHECKFP-NEXT:    ld %s10, 8(, %s11)
 ; CHECKFP-NEXT:    ld %s9, (, %s11)
 ; CHECKFP-NEXT:    b.l.t (, %s10)
   %2 = alloca [7 x i8], align 1
   %3 = getelementptr inbounds [7 x i8], [7 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ;; Allocated buffer is aligned by 8, so it places from 8 to 14 bytes in 16
 ;; bytes local vars area.
 
 ; Function Attrs: nounwind
 define i8* @test_frame7_align8(i8* %0) {
 ; CHECK-LABEL: test_frame7_align8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -192(, %s11)
+; CHECK-NEXT:    adds.l %s11, -16, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 184(, %s11)
-; CHECK-NEXT:    st1b %s1, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, 8(, %s11)
+; CHECK-NEXT:    st1b %s1, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; CHECKFP-LABEL: test_frame7_align8:
 ; CHECKFP:       # %bb.0:
 ; CHECKFP-NEXT:    st %s9, (, %s11)
 ; CHECKFP-NEXT:    st %s10, 8(, %s11)
-; CHECKFP-NEXT:    st %s15, 24(, %s11)
-; CHECKFP-NEXT:    st %s16, 32(, %s11)
 ; CHECKFP-NEXT:    or %s9, 0, %s11
 ; CHECKFP-NEXT:    lea %s11, -192(, %s11)
 ; CHECKFP-NEXT:    brge.l.t %s11, %s8, .LBB1_2
 ; CHECKFP-NEXT:  # %bb.1:
 ; CHECKFP-NEXT:    ld %s61, 24(, %s14)
 ; CHECKFP-NEXT:    or %s62, 0, %s0
 ; CHECKFP-NEXT:    lea %s63, 315
 ; CHECKFP-NEXT:    shm.l %s63, (%s61)
 ; CHECKFP-NEXT:    shm.l %s8, 8(%s61)
 ; CHECKFP-NEXT:    shm.l %s11, 16(%s61)
 ; CHECKFP-NEXT:    monc
 ; CHECKFP-NEXT:    or %s0, 0, %s62
 ; CHECKFP-NEXT:  .LBB1_2:
 ; CHECKFP-NEXT:    ld1b.zx %s1, (, %s0)
 ; CHECKFP-NEXT:    lea %s0, -8(, %s9)
 ; CHECKFP-NEXT:    st1b %s1, -8(, %s9)
 ; CHECKFP-NEXT:    or %s11, 0, %s9
-; CHECKFP-NEXT:    ld %s16, 32(, %s11)
-; CHECKFP-NEXT:    ld %s15, 24(, %s11)
 ; CHECKFP-NEXT:    ld %s10, 8(, %s11)
 ; CHECKFP-NEXT:    ld %s9, (, %s11)
 ; CHECKFP-NEXT:    b.l.t (, %s10)
   %2 = alloca [7 x i8], align 8
   %3 = getelementptr inbounds [7 x i8], [7 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ;; Allocated buffer is aligned by 16, so it places from 0 to 15 bytes in 16
 ;; bytes local vars area.
 
 ; Function Attrs: nounwind
 define i8* @test_frame16_align16(i8* %0) {
 ; CHECK-LABEL: test_frame16_align16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -192(, %s11)
+; CHECK-NEXT:    adds.l %s11, -16, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 176(, %s11)
-; CHECK-NEXT:    st1b %s1, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, (, %s11)
+; CHECK-NEXT:    st1b %s1, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; CHECKFP-LABEL: test_frame16_align16:
 ; CHECKFP:       # %bb.0:
 ; CHECKFP-NEXT:    st %s9, (, %s11)
 ; CHECKFP-NEXT:    st %s10, 8(, %s11)
-; CHECKFP-NEXT:    st %s15, 24(, %s11)
-; CHECKFP-NEXT:    st %s16, 32(, %s11)
 ; CHECKFP-NEXT:    or %s9, 0, %s11
 ; CHECKFP-NEXT:    lea %s11, -192(, %s11)
 ; CHECKFP-NEXT:    brge.l.t %s11, %s8, .LBB2_2
 ; CHECKFP-NEXT:  # %bb.1:
 ; CHECKFP-NEXT:    ld %s61, 24(, %s14)
 ; CHECKFP-NEXT:    or %s62, 0, %s0
 ; CHECKFP-NEXT:    lea %s63, 315
 ; CHECKFP-NEXT:    shm.l %s63, (%s61)
 ; CHECKFP-NEXT:    shm.l %s8, 8(%s61)
 ; CHECKFP-NEXT:    shm.l %s11, 16(%s61)
 ; CHECKFP-NEXT:    monc
 ; CHECKFP-NEXT:    or %s0, 0, %s62
 ; CHECKFP-NEXT:  .LBB2_2:
 ; CHECKFP-NEXT:    ld1b.zx %s1, (, %s0)
 ; CHECKFP-NEXT:    lea %s0, -16(, %s9)
 ; CHECKFP-NEXT:    st1b %s1, -16(, %s9)
 ; CHECKFP-NEXT:    or %s11, 0, %s9
-; CHECKFP-NEXT:    ld %s16, 32(, %s11)
-; CHECKFP-NEXT:    ld %s15, 24(, %s11)
 ; CHECKFP-NEXT:    ld %s10, 8(, %s11)
 ; CHECKFP-NEXT:    ld %s9, (, %s11)
 ; CHECKFP-NEXT:    b.l.t (, %s10)
   %2 = alloca [16 x i8], align 16
   %3 = getelementptr inbounds [16 x i8], [16 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ;; Allocated buffer is aligned by 32, so it places from 0 to 15 bytes in 48
 ;; bytes local vars area.  Or it places from 192 (aligned to 32 bytes) to
 ;; 207 bytes in 224 + alpha allocated local vars area.
 
 ; Function Attrs: nounwind
 define i8* @test_frame16_align32(i8* %0) {
 ; CHECK-LABEL: test_frame16_align32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -224(, %s11)
 ; CHECK-NEXT:    and %s11, %s11, (59)1
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
 ; CHECK-NEXT:    lea %s0, 192(, %s11)
 ; CHECK-NEXT:    st1b %s1, 192(, %s11)
 ; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; CHECKFP-LABEL: test_frame16_align32:
 ; CHECKFP:       # %bb.0:
 ; CHECKFP-NEXT:    st %s9, (, %s11)
 ; CHECKFP-NEXT:    st %s10, 8(, %s11)
-; CHECKFP-NEXT:    st %s15, 24(, %s11)
-; CHECKFP-NEXT:    st %s16, 32(, %s11)
 ; CHECKFP-NEXT:    or %s9, 0, %s11
 ; CHECKFP-NEXT:    lea %s11, -224(, %s11)
 ; CHECKFP-NEXT:    and %s11, %s11, (59)1
 ; CHECKFP-NEXT:    brge.l.t %s11, %s8, .LBB3_2
 ; CHECKFP-NEXT:  # %bb.1:
 ; CHECKFP-NEXT:    ld %s61, 24(, %s14)
 ; CHECKFP-NEXT:    or %s62, 0, %s0
 ; CHECKFP-NEXT:    lea %s63, 315
 ; CHECKFP-NEXT:    shm.l %s63, (%s61)
 ; CHECKFP-NEXT:    shm.l %s8, 8(%s61)
 ; CHECKFP-NEXT:    shm.l %s11, 16(%s61)
 ; CHECKFP-NEXT:    monc
 ; CHECKFP-NEXT:    or %s0, 0, %s62
 ; CHECKFP-NEXT:  .LBB3_2:
 ; CHECKFP-NEXT:    ld1b.zx %s1, (, %s0)
 ; CHECKFP-NEXT:    lea %s0, 192(, %s11)
 ; CHECKFP-NEXT:    st1b %s1, 192(, %s11)
 ; CHECKFP-NEXT:    or %s11, 0, %s9
-; CHECKFP-NEXT:    ld %s16, 32(, %s11)
-; CHECKFP-NEXT:    ld %s15, 24(, %s11)
 ; CHECKFP-NEXT:    ld %s10, 8(, %s11)
 ; CHECKFP-NEXT:    ld %s9, (, %s11)
 ; CHECKFP-NEXT:    b.l.t (, %s10)
   %2 = alloca [16 x i8], align 32
   %3 = getelementptr inbounds [16 x i8], [16 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ;; Allocated buffer is aligned by 32, so it places from 0 to 31 bytes in 48
 ;; + alpha bytes local vars area, or it places from 192 (32 bytes aligned 176)
 ;; to 223 in 224 + alpha bytes local vars area..
 
 ; Function Attrs: nounwind
 define i8* @test_frame32_align32(i8* %0) {
 ; CHECK-LABEL: test_frame32_align32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -224(, %s11)
 ; CHECK-NEXT:    and %s11, %s11, (59)1
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
 ; CHECK-NEXT:    lea %s0, 192(, %s11)
 ; CHECK-NEXT:    st1b %s1, 192(, %s11)
 ; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; CHECKFP-LABEL: test_frame32_align32:
 ; CHECKFP:       # %bb.0:
 ; CHECKFP-NEXT:    st %s9, (, %s11)
 ; CHECKFP-NEXT:    st %s10, 8(, %s11)
-; CHECKFP-NEXT:    st %s15, 24(, %s11)
-; CHECKFP-NEXT:    st %s16, 32(, %s11)
 ; CHECKFP-NEXT:    or %s9, 0, %s11
 ; CHECKFP-NEXT:    lea %s11, -224(, %s11)
 ; CHECKFP-NEXT:    and %s11, %s11, (59)1
 ; CHECKFP-NEXT:    brge.l.t %s11, %s8, .LBB4_2
 ; CHECKFP-NEXT:  # %bb.1:
 ; CHECKFP-NEXT:    ld %s61, 24(, %s14)
 ; CHECKFP-NEXT:    or %s62, 0, %s0
 ; CHECKFP-NEXT:    lea %s63, 315
 ; CHECKFP-NEXT:    shm.l %s63, (%s61)
 ; CHECKFP-NEXT:    shm.l %s8, 8(%s61)
 ; CHECKFP-NEXT:    shm.l %s11, 16(%s61)
 ; CHECKFP-NEXT:    monc
 ; CHECKFP-NEXT:    or %s0, 0, %s62
 ; CHECKFP-NEXT:  .LBB4_2:
 ; CHECKFP-NEXT:    ld1b.zx %s1, (, %s0)
 ; CHECKFP-NEXT:    lea %s0, 192(, %s11)
 ; CHECKFP-NEXT:    st1b %s1, 192(, %s11)
 ; CHECKFP-NEXT:    or %s11, 0, %s9
-; CHECKFP-NEXT:    ld %s16, 32(, %s11)
-; CHECKFP-NEXT:    ld %s15, 24(, %s11)
 ; CHECKFP-NEXT:    ld %s10, 8(, %s11)
 ; CHECKFP-NEXT:    ld %s9, (, %s11)
 ; CHECKFP-NEXT:    b.l.t (, %s10)
   %2 = alloca [32 x i8], align 32
   %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ;; Dynamically allocated buffer is aligned by 16, so it places from 0 to 31
 ;; bytes in allocated area, or it places from 240 (32 bytes aligned 176+64)
 ;; to 271 in allocated area (actually it places not newly allocated area
 ;; but in somewhere between newly allocated area and allocated area at the
 ;; prologue since VE ABI requires the reserved area at the top of stack).
 
 ;; FIXME: (size+15)/16*16 is not enough.
 
 ; Function Attrs: nounwind
 define i8* @test_frame_dynalign16(i8* %0, i64 %1) {
 ; CHECK-LABEL: test_frame_dynalign16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -240(, %s11)
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    or %s2, 0, %s0
 ; CHECK-NEXT:    lea %s0, 15(, %s1)
 ; CHECK-NEXT:    and %s0, -16, %s0
 ; CHECK-NEXT:    lea %s1, __ve_grow_stack@lo
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __ve_grow_stack@hi(, %s1)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    lea %s0, 240(, %s11)
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s2)
 ; CHECK-NEXT:    st1b %s1, (, %s0)
 ; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; CHECKFP-LABEL: test_frame_dynalign16:
 ; CHECKFP:       # %bb.0:
 ; CHECKFP-NEXT:    st %s9, (, %s11)
 ; CHECKFP-NEXT:    st %s10, 8(, %s11)
-; CHECKFP-NEXT:    st %s15, 24(, %s11)
-; CHECKFP-NEXT:    st %s16, 32(, %s11)
 ; CHECKFP-NEXT:    or %s9, 0, %s11
 ; CHECKFP-NEXT:    lea %s11, -240(, %s11)
 ; CHECKFP-NEXT:    brge.l.t %s11, %s8, .LBB5_2
 ; CHECKFP-NEXT:  # %bb.1:
 ; CHECKFP-NEXT:    ld %s61, 24(, %s14)
 ; CHECKFP-NEXT:    or %s62, 0, %s0
 ; CHECKFP-NEXT:    lea %s63, 315
 ; CHECKFP-NEXT:    shm.l %s63, (%s61)
 ; CHECKFP-NEXT:    shm.l %s8, 8(%s61)
 ; CHECKFP-NEXT:    shm.l %s11, 16(%s61)
 ; CHECKFP-NEXT:    monc
 ; CHECKFP-NEXT:    or %s0, 0, %s62
 ; CHECKFP-NEXT:  .LBB5_2:
 ; CHECKFP-NEXT:    or %s2, 0, %s0
 ; CHECKFP-NEXT:    lea %s0, 15(, %s1)
 ; CHECKFP-NEXT:    and %s0, -16, %s0
 ; CHECKFP-NEXT:    lea %s1, __ve_grow_stack@lo
 ; CHECKFP-NEXT:    and %s1, %s1, (32)0
 ; CHECKFP-NEXT:    lea.sl %s12, __ve_grow_stack@hi(, %s1)
 ; CHECKFP-NEXT:    bsic %s10, (, %s12)
 ; CHECKFP-NEXT:    lea %s0, 240(, %s11)
 ; CHECKFP-NEXT:    ld1b.zx %s1, (, %s2)
 ; CHECKFP-NEXT:    st1b %s1, (, %s0)
 ; CHECKFP-NEXT:    or %s11, 0, %s9
-; CHECKFP-NEXT:    ld %s16, 32(, %s11)
-; CHECKFP-NEXT:    ld %s15, 24(, %s11)
 ; CHECKFP-NEXT:    ld %s10, 8(, %s11)
 ; CHECKFP-NEXT:    ld %s9, (, %s11)
 ; CHECKFP-NEXT:    b.l.t (, %s10)
   %3 = alloca i8, i64 %1, align 16
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }

 ;; address between 240 and 271 from SP.
 
 ; Function Attrs: nounwind
 define i8* @test_frame16_align16_dynalign32(i8* %0, i64 %n) {
 ; CHECK-LABEL: test_frame16_align16_dynalign32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    st %s17, 40(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -288(, %s11)
 ; CHECK-NEXT:    and %s11, %s11, (59)1
 ; CHECK-NEXT:    or %s17, 0, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)

 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    lea %s0, 240(, %s11)
 ; CHECK-NEXT:    ld1b.zx %s1, 272(, %s17)
 ; CHECK-NEXT:    lea %s0, 31(, %s0)
 ; CHECK-NEXT:    and %s0, -32, %s0
 ; CHECK-NEXT:    st1b %s1, (, %s0)
 ; CHECK-NEXT:    or %s11, 0, %s9
 ; CHECK-NEXT:    ld %s17, 40(, %s11)
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; CHECKFP-LABEL: test_frame16_align16_dynalign32:
 ; CHECKFP:       # %bb.0:
 ; CHECKFP-NEXT:    st %s9, (, %s11)
 ; CHECKFP-NEXT:    st %s10, 8(, %s11)
-; CHECKFP-NEXT:    st %s15, 24(, %s11)
-; CHECKFP-NEXT:    st %s16, 32(, %s11)
 ; CHECKFP-NEXT:    st %s17, 40(, %s11)
 ; CHECKFP-NEXT:    or %s9, 0, %s11
 ; CHECKFP-NEXT:    lea %s11, -288(, %s11)
 ; CHECKFP-NEXT:    and %s11, %s11, (59)1
 ; CHECKFP-NEXT:    or %s17, 0, %s11
 ; CHECKFP-NEXT:    brge.l.t %s11, %s8, .LBB6_2
 ; CHECKFP-NEXT:  # %bb.1:
 ; CHECKFP-NEXT:    ld %s61, 24(, %s14)

 ; CHECKFP-NEXT:    bsic %s10, (, %s12)
 ; CHECKFP-NEXT:    lea %s0, 240(, %s11)
 ; CHECKFP-NEXT:    ld1b.zx %s1, 272(, %s17)
 ; CHECKFP-NEXT:    lea %s0, 31(, %s0)
 ; CHECKFP-NEXT:    and %s0, -32, %s0
 ; CHECKFP-NEXT:    st1b %s1, (, %s0)
 ; CHECKFP-NEXT:    or %s11, 0, %s9
 ; CHECKFP-NEXT:    ld %s17, 40(, %s11)
-; CHECKFP-NEXT:    ld %s16, 32(, %s11)
-; CHECKFP-NEXT:    ld %s15, 24(, %s11)
 ; CHECKFP-NEXT:    ld %s10, 8(, %s11)
 ; CHECKFP-NEXT:    ld %s9, (, %s11)
 ; CHECKFP-NEXT:    b.l.t (, %s10)
   %2 = alloca [16 x i8], align 16
   %3 = getelementptr inbounds [16 x i8], [16 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   %5 = alloca i8, i64 %n, align 32
   %6 = load i8, i8* %3, align 1
   store i8 %6, i8* %5, align 1
   ret i8* %5
 }
 

llvm/test/CodeGen/VE/Scalar/stackframe_call.ll

 @data = external global i8, align 1
 
 ; Function Attrs: nounwind
 define i8* @test_frame0(i8* %0, i8* %1) {
 ; CHECK-LABEL: test_frame0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -240(, %s11)
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    lea %s2, fun@lo
 ; CHECK-NEXT:    and %s2, %s2, (32)0
 ; CHECK-NEXT:    lea.sl %s12, fun@hi(, %s2)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_frame0:
 ; PIC:       # %bb.0:
 ; PIC-NEXT:    st %s9, (, %s11)
 ; PIC-NEXT:    st %s10, 8(, %s11)

 declare i8* @fun(i8*, i8*)
 
 ; Function Attrs: nounwind
 define i8* @test_frame32(i8* %0) {
 ; CHECK-LABEL: test_frame32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -272(, %s11)
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
 ; CHECK-NEXT:    lea %s0, fun@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, fun@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 240(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_frame32:
 ; PIC:       # %bb.0:
 ; PIC-NEXT:    st %s9, (, %s11)
 ; PIC-NEXT:    st %s10, 8(, %s11)

 declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
 
 ; Function Attrs: nounwind
 define i8* @test_align32(i32 signext %0, i8* nocapture readnone %1) {
 ; CHECK-LABEL: test_align32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    st %s17, 40(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -288(, %s11)
 ; CHECK-NEXT:    and %s11, %s11, (59)1
 ; CHECK-NEXT:    or %s17, 0, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)

 ; CHECK-NEXT:    and %s1, -32, %s0
 ; CHECK-NEXT:    lea %s0, fun@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, fun@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 256(, %s17)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
 ; CHECK-NEXT:    ld %s17, 40(, %s11)
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_align32:
 ; PIC:       # %bb.0:
 ; PIC-NEXT:    st %s9, (, %s11)
 ; PIC-NEXT:    st %s10, 8(, %s11)

 }
 
 ; Function Attrs: nounwind
 define i8* @test_frame0_var(i8* %0, i8* %1) {
 ; CHECK-LABEL: test_frame0_var:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -240(, %s11)
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    lea %s2, data@lo
 ; CHECK-NEXT:    and %s2, %s2, (32)0
 ; CHECK-NEXT:    lea.sl %s2, data@hi(, %s2)
 ; CHECK-NEXT:    ld1b.zx %s2, (, %s2)
 ; CHECK-NEXT:    st1b %s2, (, %s0)
 ; CHECK-NEXT:    lea %s2, fun@lo
 ; CHECK-NEXT:    and %s2, %s2, (32)0
 ; CHECK-NEXT:    lea.sl %s12, fun@hi(, %s2)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_frame0_var:
 ; PIC:       # %bb.0:
 ; PIC-NEXT:    st %s9, (, %s11)
 ; PIC-NEXT:    st %s10, 8(, %s11)

 }
 
 ; Function Attrs: nounwind
 define i8* @test_frame32_var(i8* %0) {
 ; CHECK-LABEL: test_frame32_var:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -272(, %s11)
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)

 ; CHECK-NEXT:    or %s1, 0, %s0
 ; CHECK-NEXT:    st1b %s2, 240(, %s11)
 ; CHECK-NEXT:    lea %s0, fun@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, fun@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 240(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_frame32_var:
 ; PIC:       # %bb.0:
 ; PIC-NEXT:    st %s9, (, %s11)
 ; PIC-NEXT:    st %s10, 8(, %s11)

 }
 
 ; Function Attrs: nounwind
 define i8* @test_align32_var(i32 signext %0, i8* nocapture readnone %1) {
 ; CHECK-LABEL: test_align32_var:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    st %s17, 40(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -288(, %s11)
 ; CHECK-NEXT:    and %s11, %s11, (59)1
 ; CHECK-NEXT:    or %s17, 0, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)

 ; CHECK-NEXT:    st1b %s2, (, %s1)
 ; CHECK-NEXT:    lea %s0, fun@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, fun@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 256(, %s17)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
 ; CHECK-NEXT:    ld %s17, 40(, %s11)
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_align32_var:
 ; PIC:       # %bb.0:
 ; PIC-NEXT:    st %s9, (, %s11)
 ; PIC-NEXT:    st %s10, 8(, %s11)

llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll

 ; PIC-NEXT:    b.l.t (, %s10)
   ret i8* %1
 }
 
 ; Function Attrs: nofree nounwind
 define nonnull i8* @test_frame32(i8* nocapture readonly %0) {
 ; CHECK-LABEL: test_frame32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -208(, %s11)
+; CHECK-NEXT:    adds.l %s11, -32, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 176(, %s11)
-; CHECK-NEXT:    st1b %s1, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, (, %s11)
+; CHECK-NEXT:    st1b %s1, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 32, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_frame32:
 ; PIC:       # %bb.0:
-; PIC-NEXT:    st %s9, (, %s11)
-; PIC-NEXT:    st %s10, 8(, %s11)
-; PIC-NEXT:    st %s15, 24(, %s11)
-; PIC-NEXT:    st %s16, 32(, %s11)
-; PIC-NEXT:    or %s9, 0, %s11
-; PIC-NEXT:    lea %s11, -208(, %s11)
+; PIC-NEXT:    adds.l %s11, -32, %s11
 ; PIC-NEXT:    brge.l.t %s11, %s8, .LBB1_2
 ; PIC-NEXT:  # %bb.1:
 ; PIC-NEXT:    ld %s61, 24(, %s14)
 ; PIC-NEXT:    or %s62, 0, %s0
 ; PIC-NEXT:    lea %s63, 315
 ; PIC-NEXT:    shm.l %s63, (%s61)
 ; PIC-NEXT:    shm.l %s8, 8(%s61)
 ; PIC-NEXT:    shm.l %s11, 16(%s61)
 ; PIC-NEXT:    monc
 ; PIC-NEXT:    or %s0, 0, %s62
 ; PIC-NEXT:  .LBB1_2:
 ; PIC-NEXT:    ld1b.zx %s1, (, %s0)
-; PIC-NEXT:    lea %s0, 176(, %s11)
-; PIC-NEXT:    st1b %s1, 176(, %s11)
-; PIC-NEXT:    or %s11, 0, %s9
-; PIC-NEXT:    ld %s16, 32(, %s11)
-; PIC-NEXT:    ld %s15, 24(, %s11)
-; PIC-NEXT:    ld %s10, 8(, %s11)
-; PIC-NEXT:    ld %s9, (, %s11)
+; PIC-NEXT:    lea %s0, (, %s11)
+; PIC-NEXT:    st1b %s1, (, %s11)
+; PIC-NEXT:    adds.l %s11, 32, %s11
 ; PIC-NEXT:    b.l.t (, %s10)
   %2 = alloca [32 x i8], align 1
   %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0
   call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %3)
   %4 = load i8, i8* %0, align 1
   store volatile i8 %4, i8* %3, align 1
   call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %3)
   ret i8* %3
 }
 
 ; Function Attrs: argmemonly nofree nosync nounwind willreturn
 declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
 
 ; Function Attrs: argmemonly nofree nosync nounwind willreturn
 declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
 
 ; Function Attrs: nofree nounwind
 define noalias nonnull i8* @test_align32(i32 signext %0, i8* nocapture readonly %1) {
 ; CHECK-LABEL: test_align32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    st %s17, 40(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -288(, %s11)
 ; CHECK-NEXT:    and %s11, %s11, (59)1
 ; CHECK-NEXT:    or %s17, 0, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)

 ; CHECK-NEXT:    lea %s0, 240(, %s11)
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s2)
 ; CHECK-NEXT:    lea %s0, 31(, %s0)
 ; CHECK-NEXT:    and %s2, -32, %s0
 ; CHECK-NEXT:    lea %s0, 256(, %s17)
 ; CHECK-NEXT:    st1b %s1, (, %s2)
 ; CHECK-NEXT:    or %s11, 0, %s9
 ; CHECK-NEXT:    ld %s17, 40(, %s11)
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_align32:
 ; PIC:       # %bb.0:
 ; PIC-NEXT:    st %s9, (, %s11)
 ; PIC-NEXT:    st %s10, 8(, %s11)
; PIC-NEXT:    b.l.t (, %s10)
   store i8 %3, i8* %0, align 1
   ret i8* %0
 }
 
 ; Function Attrs: nofree nounwind
 define nonnull i8* @test_frame32_var(i8* nocapture readnone %0) {
 ; CHECK-LABEL: test_frame32_var:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -208(, %s11)
+; CHECK-NEXT:    adds.l %s11, -32, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    lea %s0, data@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s0, data@hi(, %s0)
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 176(, %s11)
-; CHECK-NEXT:    st1b %s1, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, (, %s11)
+; CHECK-NEXT:    st1b %s1, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 32, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_frame32_var:
 ; PIC:       # %bb.0:
 ; PIC-NEXT:    st %s9, (, %s11)
 ; PIC-NEXT:    st %s10, 8(, %s11)
 ; PIC-NEXT:    st %s15, 24(, %s11)
 ; PIC-NEXT:    st %s16, 32(, %s11)

 }
 
 ; Function Attrs: nofree nounwind
 define noalias nonnull i8* @test_align32_var(i32 signext %0, i8* nocapture readonly %1) {
 ; CHECK-LABEL: test_align32_var:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    st %s9, (, %s11)
 ; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    st %s17, 40(, %s11)
 ; CHECK-NEXT:    or %s9, 0, %s11
 ; CHECK-NEXT:    lea %s11, -288(, %s11)
 ; CHECK-NEXT:    and %s11, %s11, (59)1
 ; CHECK-NEXT:    or %s17, 0, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)

 ; CHECK-NEXT:    lea %s0, 240(, %s11)
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s2)
 ; CHECK-NEXT:    lea %s0, 31(, %s0)
 ; CHECK-NEXT:    and %s2, -32, %s0
 ; CHECK-NEXT:    lea %s0, 256(, %s17)
 ; CHECK-NEXT:    st1b %s1, (, %s2)
 ; CHECK-NEXT:    or %s11, 0, %s9
 ; CHECK-NEXT:    ld %s17, 40(, %s11)
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
 ; CHECK-NEXT:    ld %s10, 8(, %s11)
 ; CHECK-NEXT:    ld %s9, (, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: test_align32_var:
 ; PIC:       # %bb.0:
 ; PIC-NEXT:    st %s9, (, %s11)
 ; PIC-NEXT:    st %s10, 8(, %s11)

llvm/test/CodeGen/VE/Scalar/stackframe_size.ll

; CHECK-NEXT:    b.l.t (, %s10)
   %2 = add nsw i32 %0, 3
   ret i32 %2
 }
 
 ; Function Attrs: nounwind
 define i8* @test_frame8(i8* %0) {
 ; CHECK-LABEL: test_frame8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -192(, %s11)
+; CHECK-NEXT:    adds.l %s11, -16, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 184(, %s11)
-; CHECK-NEXT:    st1b %s1, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, 8(, %s11)
+; CHECK-NEXT:    st1b %s1, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = alloca [8 x i8], align 1
   %3 = getelementptr inbounds [8 x i8], [8 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ; Function Attrs: nounwind
 define i8* @test_frame16(i8* %0) {
 ; CHECK-LABEL: test_frame16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -192(, %s11)
+; CHECK-NEXT:    adds.l %s11, -16, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 176(, %s11)
-; CHECK-NEXT:    st1b %s1, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, (, %s11)
+; CHECK-NEXT:    st1b %s1, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = alloca [16 x i8], align 1
   %3 = getelementptr inbounds [16 x i8], [16 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ; Function Attrs: nounwind
 define i8* @test_frame32(i8* %0) {
 ; CHECK-LABEL: test_frame32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -208(, %s11)
+; CHECK-NEXT:    adds.l %s11, -32, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 176(, %s11)
-; CHECK-NEXT:    st1b %s1, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, (, %s11)
+; CHECK-NEXT:    st1b %s1, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 32, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = alloca [32 x i8], align 1
   %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ; Function Attrs: nounwind
 define i8* @test_frame64(i8* %0) {
 ; CHECK-LABEL: test_frame64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -240(, %s11)
+; CHECK-NEXT:    adds.l %s11, -64, %s11
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 176(, %s11)
-; CHECK-NEXT:    st1b %s1, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, (, %s11)
+; CHECK-NEXT:    st1b %s1, (, %s11)
+; CHECK-NEXT:    lea %s11, 64(, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = alloca [64 x i8], align 1
   %3 = getelementptr inbounds [64 x i8], [64 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ; Function Attrs: nounwind
 define i8* @test_frame128(i8* %0) {
 ; CHECK-LABEL: test_frame128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -304(, %s11)
+; CHECK-NEXT:    lea %s11, -128(, %s11)
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 176(, %s11)
-; CHECK-NEXT:    st1b %s1, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, (, %s11)
+; CHECK-NEXT:    st1b %s1, (, %s11)
+; CHECK-NEXT:    lea %s11, 128(, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = alloca [128 x i8], align 1
   %3 = getelementptr inbounds [128 x i8], [128 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ; Function Attrs: nounwind
 define i8* @test_frame65536(i8* %0) {
 ; CHECK-LABEL: test_frame65536:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s11, -65712(, %s11)
+; CHECK-NEXT:    lea %s11, -65536(, %s11)
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB6_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 176(, %s11)
-; CHECK-NEXT:    st1b %s1, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, (, %s11)
+; CHECK-NEXT:    st1b %s1, (, %s11)
+; CHECK-NEXT:    lea %s11, 65536(, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = alloca [65536 x i8], align 1
   %3 = getelementptr inbounds [65536 x i8], [65536 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }
 
 ; Function Attrs: nounwind
 define i8* @test_frame4294967296(i8* %0) {
 ; CHECK-LABEL: test_frame4294967296:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    st %s9, (, %s11)
-; CHECK-NEXT:    st %s10, 8(, %s11)
-; CHECK-NEXT:    st %s15, 24(, %s11)
-; CHECK-NEXT:    st %s16, 32(, %s11)
-; CHECK-NEXT:    or %s9, 0, %s11
-; CHECK-NEXT:    lea %s13, -176
+; CHECK-NEXT:    lea %s13, 0
 ; CHECK-NEXT:    and %s13, %s13, (32)0
-; CHECK-NEXT:    lea.sl %s11, -2(%s13, %s11)
+; CHECK-NEXT:    lea.sl %s11, -1(%s13, %s11)
 ; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    ld %s61, 24(, %s14)
 ; CHECK-NEXT:    or %s62, 0, %s0
 ; CHECK-NEXT:    lea %s63, 315
 ; CHECK-NEXT:    shm.l %s63, (%s61)
 ; CHECK-NEXT:    shm.l %s8, 8(%s61)
 ; CHECK-NEXT:    shm.l %s11, 16(%s61)
 ; CHECK-NEXT:    monc
 ; CHECK-NEXT:    or %s0, 0, %s62
 ; CHECK-NEXT:  .LBB7_2:
 ; CHECK-NEXT:    ld1b.zx %s1, (, %s0)
-; CHECK-NEXT:    lea %s0, 176(, %s11)
-; CHECK-NEXT:    st1b %s1, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
-; CHECK-NEXT:    ld %s16, 32(, %s11)
-; CHECK-NEXT:    ld %s15, 24(, %s11)
-; CHECK-NEXT:    ld %s10, 8(, %s11)
-; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    lea %s0, (, %s11)
+; CHECK-NEXT:    st1b %s1, (, %s11)
+; CHECK-NEXT:    lea %s13, 0
+; CHECK-NEXT:    and %s13, %s13, (32)0
+; CHECK-NEXT:    lea.sl %s11, 1(%s13, %s11)
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = alloca [4294967296 x i8], align 1
   %3 = getelementptr inbounds [4294967296 x i8], [4294967296 x i8]* %2, i64 0, i64 0
   %4 = load i8, i8* %0, align 1
   store i8 %4, i8* %3, align 1
   ret i8* %3
 }

llvm/test/CodeGen/VE/Scalar/store-align1.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 @vi8 = common dso_local local_unnamed_addr global i8 0, align 1
 @vi16 = common dso_local local_unnamed_addr global i16 0, align 1
 @vi32 = common dso_local local_unnamed_addr global i32 0, align 1
 @vi64 = common dso_local local_unnamed_addr global i64 0, align 1
 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 1
 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 1
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef64stk(double %0) {
 ; CHECK-LABEL: storef64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 1
   store double %0, double* %addr, align 1
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef32stk(float %0) {
 ; CHECK-LABEL: storef32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stu %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stu %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 1
   store float %0, float* %addr, align 1
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei64stk(i64 %0) {
 ; CHECK-LABEL: storei64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 1
   store i64 %0, i64* %addr, align 1
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei32stk(i32 %0) {
 ; CHECK-LABEL: storei32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stl %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stl %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 1
   store i32 %0, i32* %addr, align 1
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei16stk(i16 %0) {
 ; CHECK-LABEL: storei16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st2b %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st2b %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 1
   store i16 %0, i16* %addr, align 1
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei8stk(i8 %0) {
 ; CHECK-LABEL: storei8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st1b %s0, 191(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, 15(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 1
   store i8 %0, i8* %addr, align 1
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef64com(double %0) {
 ; CHECK-LABEL: storef64com:

llvm/test/CodeGen/VE/Scalar/store-align2.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 @vi8 = common dso_local local_unnamed_addr global i8 0, align 2
 @vi16 = common dso_local local_unnamed_addr global i16 0, align 2
 @vi32 = common dso_local local_unnamed_addr global i32 0, align 2
 @vi64 = common dso_local local_unnamed_addr global i64 0, align 2
 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 2
 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 2
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef64stk(double %0) {
 ; CHECK-LABEL: storef64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 2
   store double %0, double* %addr, align 2
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef32stk(float %0) {
 ; CHECK-LABEL: storef32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stu %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stu %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 2
   store float %0, float* %addr, align 2
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei64stk(i64 %0) {
 ; CHECK-LABEL: storei64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 2
   store i64 %0, i64* %addr, align 2
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei32stk(i32 %0) {
 ; CHECK-LABEL: storei32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stl %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stl %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 2
   store i32 %0, i32* %addr, align 2
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei16stk(i16 %0) {
 ; CHECK-LABEL: storei16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st2b %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st2b %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 2
   store i16 %0, i16* %addr, align 2
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei8stk(i8 %0) {
 ; CHECK-LABEL: storei8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st1b %s0, 190(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, 14(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 2
   store i8 %0, i8* %addr, align 2
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef64com(double %0) {
 ; CHECK-LABEL: storef64com:

llvm/test/CodeGen/VE/Scalar/store-align4.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 @vi8 = common dso_local local_unnamed_addr global i8 0, align 4
 @vi16 = common dso_local local_unnamed_addr global i16 0, align 4
 @vi32 = common dso_local local_unnamed_addr global i32 0, align 4
 @vi64 = common dso_local local_unnamed_addr global i64 0, align 4
 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 4
 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 4
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef64stk(double %0) {
 ; CHECK-LABEL: storef64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 4
   store double %0, double* %addr, align 4
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef32stk(float %0) {
 ; CHECK-LABEL: storef32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stu %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stu %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 4
   store float %0, float* %addr, align 4
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei64stk(i64 %0) {
 ; CHECK-LABEL: storei64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 4
   store i64 %0, i64* %addr, align 4
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei32stk(i32 %0) {
 ; CHECK-LABEL: storei32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stl %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stl %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 4
   store i32 %0, i32* %addr, align 4
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei16stk(i16 %0) {
 ; CHECK-LABEL: storei16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st2b %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st2b %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 4
   store i16 %0, i16* %addr, align 4
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei8stk(i8 %0) {
 ; CHECK-LABEL: storei8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st1b %s0, 188(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, 12(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 4
   store i8 %0, i8* %addr, align 4
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef64com(double %0) {
 ; CHECK-LABEL: storef64com:

llvm/test/CodeGen/VE/Scalar/store-align8.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 @vi8 = common dso_local local_unnamed_addr global i8 0, align 8
 @vi16 = common dso_local local_unnamed_addr global i16 0, align 8
 @vi32 = common dso_local local_unnamed_addr global i32 0, align 8
 @vi64 = common dso_local local_unnamed_addr global i64 0, align 8
 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 8
 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 8
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef64stk(double %0) {
 ; CHECK-LABEL: storef64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 8
   store double %0, double* %addr, align 8
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef32stk(float %0) {
 ; CHECK-LABEL: storef32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stu %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stu %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 8
   store float %0, float* %addr, align 8
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei64stk(i64 %0) {
 ; CHECK-LABEL: storei64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 8
   store i64 %0, i64* %addr, align 8
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei32stk(i32 %0) {
 ; CHECK-LABEL: storei32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stl %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stl %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 8
   store i32 %0, i32* %addr, align 8
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei16stk(i16 %0) {
 ; CHECK-LABEL: storei16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st2b %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st2b %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 8
   store i16 %0, i16* %addr, align 8
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei8stk(i8 %0) {
 ; CHECK-LABEL: storei8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st1b %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 8
   store i8 %0, i8* %addr, align 8
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef64com(double %0) {
 ; CHECK-LABEL: storef64com:

llvm/test/CodeGen/VE/Scalar/store.ll

; CHECK-NEXT:    b.l.t (, %s10)
   store i8 %3, i8* %0, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef128stk(fp128 %0) {
 ; CHECK-LABEL: storef128stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s1, 176(, %s11)
-; CHECK-NEXT:    st %s0, 184(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s1, (, %s11)
+; CHECK-NEXT:    st %s0, 8(, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca fp128, align 16
   store fp128 %0, fp128* %addr, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef64stk(double %0) {
 ; CHECK-LABEL: storef64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca double, align 16
   store double %0, double* %addr, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storef32stk(float %0) {
 ; CHECK-LABEL: storef32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stu %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stu %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca float, align 16
   store float %0, float* %addr, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei128stk(i128 %0) {
 ; CHECK-LABEL: storei128stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s1, 184(, %s11)
-; CHECK-NEXT:    st %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s1, 8(, %s11)
+; CHECK-NEXT:    st %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i128, align 16
   store i128 %0, i128* %addr, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei64stk(i64 %0) {
 ; CHECK-LABEL: storei64stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i64, align 16
   store i64 %0, i64* %addr, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei32stk(i32 %0) {
 ; CHECK-LABEL: storei32stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    stl %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    stl %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i32, align 16
   store i32 %0, i32* %addr, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei16stk(i16 %0) {
 ; CHECK-LABEL: storei16stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st2b %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st2b %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i16, align 16
   store i16 %0, i16* %addr, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define void @storei8stk(i8 %0) {
 ; CHECK-LABEL: storei8stk:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st1b %s0, 176(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    st1b %s0, (, %s11)
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
   %addr = alloca i8, align 16
   store i8 %0, i8* %addr, align 16
   ret void
 }

llvm/test/CodeGen/VE/Vector/fastcc_callee.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
 
 ; Scalar argument passing must not change (same tests as in VE/Scalar/callee.ll below - this time with +vpu)
 
 define fastcc i32 @stack_stack_arg_i32_r9(i1 %0, i8 %1, i16 %2, i32 %3, i64 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9) {
 ; CHECK-LABEL: stack_stack_arg_i32_r9:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 424(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ldl.sx %s0, 248(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret i32 %9
 }
 
 define fastcc i64 @stack_stack_arg_i64_r9(i1 %0, i8 %1, i16 %2, i32 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8, i64 %9) {
 ; CHECK-LABEL: stack_stack_arg_i64_r9:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ld %s0, 424(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ld %s0, 248(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret i64 %9
 }
 
 define fastcc float @stack_stack_arg_f32_r9(float %p0, float %p1, float %p2, float %p3, float %p4, float %p5, float %p6, float %p7, float %s0, float %s1) {
 ; CHECK-LABEL: stack_stack_arg_f32_r9:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldu %s0, 428(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ldu %s0, 252(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret float %s1
 }
 
 define fastcc i32 @stack_stack_arg_i32f32_r8(i32 %p0, float %p1, i32 %p2, float %p3, i32 %p4, float %p5, i32 %p6, float %p7, i32 %s0, float %s1) {
 ; CHECK-LABEL: stack_stack_arg_i32f32_r8:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldl.sx %s0, 416(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ldl.sx %s0, 240(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret i32 %s0
 }
 
 define fastcc float @stack_stack_arg_i32f32_r9(i32 %p0, float %p1, i32 %p2, float %p3, i32 %p4, float %p5, i32 %p6, float %p7, i32 %s0, float %s1) {
 ; CHECK-LABEL: stack_stack_arg_i32f32_r9:
-; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    ldu %s0, 428(, %s11)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ldu %s0, 252(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
   ret float %s1
 }
 
 ; Vector argument passing (fastcc feature)
 
 ; v0-to-v0 passthrough case without vreg copy.
 define fastcc <256 x i32> @vreg_arg_v256i32_r0(<256 x i32> %p0) {
 ; CHECK-LABEL: vreg_arg_v256i32_r0: