[Hexagon] Add HVX support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns

[RKSimon]

Summary

Followup to D92112 now that I've learnt about hvx type splitting.

This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876.

[kparzysz]

LGTM, Thanks!

llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

for (MVT T : LegalV) {
     setOperationAction(ISD::SELECT,         T, Legal);
     setOperationAction(ISD::SPLAT_VECTOR,   T, Legal);
     if (T != ByteV) {
       setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
       setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal);
       setOperationAction(ISD::BSWAP,                    T, Legal);
     }
 
+    setOperationAction(ISD::SMIN,           T, Legal);
+    setOperationAction(ISD::SMAX,           T, Legal);
+    if (T.getScalarType() != MVT::i32) {
+      setOperationAction(ISD::UMIN,         T, Legal);
+      setOperationAction(ISD::UMAX,         T, Legal);
+    }
+
     setOperationAction(ISD::CTTZ,               T, Custom);
     setOperationAction(ISD::LOAD,               T, Custom);
     setOperationAction(ISD::MLOAD,              T, Custom);
     setOperationAction(ISD::MSTORE,             T, Custom);
     setOperationAction(ISD::MULHS,              T, Custom);
     setOperationAction(ISD::MULHU,              T, Custom);
     setOperationAction(ISD::BUILD_VECTOR,       T, Custom);
     // Make concat-vectors custom to handle concats of more than 2 vectors.
for (MVT T : LegalW) {
     if (T != ByteW) {
       setOperationAction(ISD::SRA,      T, Custom);
       setOperationAction(ISD::SHL,      T, Custom);
       setOperationAction(ISD::SRL,      T, Custom);
 
       // Promote all shuffles to operate on vectors of bytes.
       setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW);
     }
+
+    setOperationAction(ISD::SMIN,     T, Custom);
+    setOperationAction(ISD::SMAX,     T, Custom);
+    if (T.getScalarType() != MVT::i32) {
+      setOperationAction(ISD::UMIN,   T, Custom);
+      setOperationAction(ISD::UMAX,   T, Custom);
+    }
   }
 
   // Boolean vectors.
 
   for (MVT T : LegalW) {
     // Boolean types for vector pairs will overlap with the boolean
     // types for single vectors, e.g.
     //   v64i8  -> v64i1 (single)
switch (Opc) {
       case ISD::MULHS:
       case ISD::MULHU:
       case ISD::AND:
       case ISD::OR:
       case ISD::XOR:
       case ISD::SRA:
       case ISD::SHL:
       case ISD::SRL:
+      case ISD::SMIN:
+      case ISD::SMAX:
+      case ISD::UMIN:
+      case ISD::UMAX:
       case ISD::SETCC:
       case ISD::VSELECT:
       case ISD::SIGN_EXTEND:
       case ISD::ZERO_EXTEND:
       case ISD::SIGN_EXTEND_INREG:
       case ISD::SPLAT_VECTOR:
         return SplitHvxPairOp(Op, DAG);
     }

llvm/lib/Target/Hexagon/HexagonPatternsHVX.td

 
 class Vneg1<ValueType VecTy>
   : PatFrag<(ops), (VecTy (splat_vector (i32 -1)))>;
 
 class Vnot<ValueType VecTy>
   : PatFrag<(ops node:$Vs), (xor $Vs, Vneg1<VecTy>)>;
 
 let Predicates = [UseHVX] in {
-  let AddedComplexity = 220 in {
-    defm: MinMax_pats<V6_vminb,  V6_vmaxb,  vselect,  setgt,  VecQ8,  HVI8>;
-    defm: MinMax_pats<V6_vminb,  V6_vmaxb,  vselect,  setge,  VecQ8,  HVI8>;
-    defm: MinMax_pats<V6_vminub, V6_vmaxub, vselect, setugt,  VecQ8,  HVI8>;
-    defm: MinMax_pats<V6_vminub, V6_vmaxub, vselect, setuge,  VecQ8,  HVI8>;
-    defm: MinMax_pats<V6_vminh,  V6_vmaxh,  vselect,  setgt, VecQ16, HVI16>;
-    defm: MinMax_pats<V6_vminh,  V6_vmaxh,  vselect,  setge, VecQ16, HVI16>;
-    defm: MinMax_pats<V6_vminuh, V6_vmaxuh, vselect, setugt, VecQ16, HVI16>;
-    defm: MinMax_pats<V6_vminuh, V6_vmaxuh, vselect, setuge, VecQ16, HVI16>;
-    defm: MinMax_pats<V6_vminw,  V6_vmaxw,  vselect,  setgt, VecQ32, HVI32>;
-    defm: MinMax_pats<V6_vminw,  V6_vmaxw,  vselect,  setge, VecQ32, HVI32>;
-  }
-}
-
-let Predicates = [UseHVX] in {
   let AddedComplexity = 200 in {
     def: Pat<(Vnot<VecI8>   HVI8:$Vs), (V6_vnot HvxVR:$Vs)>;
     def: Pat<(Vnot<VecI16> HVI16:$Vs), (V6_vnot HvxVR:$Vs)>;
     def: Pat<(Vnot<VecI32> HVI32:$Vs), (V6_vnot HvxVR:$Vs)>;
   }
 
   def: OpR_RR_pat<V6_vaddb,    Add,   VecI8,  HVI8>;
   def: OpR_RR_pat<V6_vaddh,    Add,  VecI16, HVI16>;
let Predicates = [UseHVX] in {
   def: OpR_RR_pat<V6_vand,     And,  VecI32, HVI32>;
   def: OpR_RR_pat<V6_vor,       Or,   VecI8,  HVI8>;
   def: OpR_RR_pat<V6_vor,       Or,  VecI16, HVI16>;
   def: OpR_RR_pat<V6_vor,       Or,  VecI32, HVI32>;
   def: OpR_RR_pat<V6_vxor,     Xor,   VecI8,  HVI8>;
   def: OpR_RR_pat<V6_vxor,     Xor,  VecI16, HVI16>;
   def: OpR_RR_pat<V6_vxor,     Xor,  VecI32, HVI32>;
 
+  def: OpR_RR_pat<V6_vminb,   Smin,   VecI8,  HVI8>;
+  def: OpR_RR_pat<V6_vmaxb,   Smax,   VecI8,  HVI8>;
+  def: OpR_RR_pat<V6_vminub,  Umin,   VecI8,  HVI8>;
+  def: OpR_RR_pat<V6_vmaxub,  Umax,   VecI8,  HVI8>;
+  def: OpR_RR_pat<V6_vminh,   Smin,  VecI16, HVI16>;
+  def: OpR_RR_pat<V6_vmaxh,   Smax,  VecI16, HVI16>;
+  def: OpR_RR_pat<V6_vminuh,  Umin,  VecI16, HVI16>;
+  def: OpR_RR_pat<V6_vmaxuh,  Umax,  VecI16, HVI16>;
+  def: OpR_RR_pat<V6_vminw,   Smin,  VecI32, HVI32>;
+  def: OpR_RR_pat<V6_vmaxw,   Smax,  VecI32, HVI32>;
+
   def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
            (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),
            (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
            (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
 
   def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt),

llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; minb
 
 ; CHECK: test_00:
-; CHECK: v0.b = vmin(v1.b,v0.b)
+; CHECK: v0.b = vmin(v0.b,v1.b)
 define <128 x i8> @test_00(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp slt <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_01:
 ; CHECK: v0.b = vmin(v0.b,v1.b)
 define <128 x i8> @test_01(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp sle <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_02:
 ; CHECK: v0.b = vmin(v0.b,v1.b)
 define <128 x i8> @test_02(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp sgt <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_03:
-; CHECK: v0.b = vmin(v1.b,v0.b)
+; CHECK: v0.b = vmin(v0.b,v1.b)
 define <128 x i8> @test_03(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp sge <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0
   ret <128 x i8> %t1
 }
 
 ; maxb
 
 ; CHECK: test_04:
-; CHECK: v0.b = vmax(v1.b,v0.b)
+; CHECK: v0.b = vmax(v0.b,v1.b)
 define <128 x i8> @test_04(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp slt <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_05:
 ; CHECK: v0.b = vmax(v0.b,v1.b)
 define <128 x i8> @test_05(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp sle <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_06:
 ; CHECK: v0.b = vmax(v0.b,v1.b)
 define <128 x i8> @test_06(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp sgt <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_07:
-; CHECK: v0.b = vmax(v1.b,v0.b)
+; CHECK: v0.b = vmax(v0.b,v1.b)
 define <128 x i8> @test_07(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp sge <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
   ret <128 x i8> %t1
 }
 
 ; minub
 
 ; CHECK: test_08:
-; CHECK: v0.ub = vmin(v1.ub,v0.ub)
+; CHECK: v0.ub = vmin(v0.ub,v1.ub)
 define <128 x i8> @test_08(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp ult <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_09:
 ; CHECK: v0.ub = vmin(v0.ub,v1.ub)
 define <128 x i8> @test_09(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp ule <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_0a:
 ; CHECK: v0.ub = vmin(v0.ub,v1.ub)
 define <128 x i8> @test_0a(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp ugt <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_0b:
-; CHECK: v0.ub = vmin(v1.ub,v0.ub)
+; CHECK: v0.ub = vmin(v0.ub,v1.ub)
 define <128 x i8> @test_0b(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp uge <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0
   ret <128 x i8> %t1
 }
 
 ; maxub
 
 ; CHECK: test_0c:
-; CHECK: v0.ub = vmax(v1.ub,v0.ub)
+; CHECK: v0.ub = vmax(v0.ub,v1.ub)
 define <128 x i8> @test_0c(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp ult <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_0d:
 ; CHECK: v0.ub = vmax(v0.ub,v1.ub)
 define <128 x i8> @test_0d(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp ule <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_0e:
 ; CHECK: v0.ub = vmax(v0.ub,v1.ub)
 define <128 x i8> @test_0e(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp ugt <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
   ret <128 x i8> %t1
 }
 
 ; CHECK: test_0f:
-; CHECK: v0.ub = vmax(v1.ub,v0.ub)
+; CHECK: v0.ub = vmax(v0.ub,v1.ub)
 define <128 x i8> @test_0f(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp uge <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
   ret <128 x i8> %t1
 }
 
 ; minh
 
 ; CHECK: test_10:
-; CHECK: v0.h = vmin(v1.h,v0.h)
+; CHECK: v0.h = vmin(v0.h,v1.h)
 define <64 x i16> @test_10(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp slt <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_11:
 ; CHECK: v0.h = vmin(v0.h,v1.h)
 define <64 x i16> @test_11(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp sle <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_12:
 ; CHECK: v0.h = vmin(v0.h,v1.h)
 define <64 x i16> @test_12(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp sgt <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_13:
-; CHECK: v0.h = vmin(v1.h,v0.h)
+; CHECK: v0.h = vmin(v0.h,v1.h)
 define <64 x i16> @test_13(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp sge <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0
   ret <64 x i16> %t1
 }
 
 ; maxh
 
 ; CHECK: test_14:
-; CHECK: v0.h = vmax(v1.h,v0.h)
+; CHECK: v0.h = vmax(v0.h,v1.h)
 define <64 x i16> @test_14(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp slt <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_15:
 ; CHECK: v0.h = vmax(v0.h,v1.h)
 define <64 x i16> @test_15(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp sle <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_16:
 ; CHECK: v0.h = vmax(v0.h,v1.h)
 define <64 x i16> @test_16(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp sgt <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_17:
-; CHECK: v0.h = vmax(v1.h,v0.h)
+; CHECK: v0.h = vmax(v0.h,v1.h)
 define <64 x i16> @test_17(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp sge <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
   ret <64 x i16> %t1
 }
 
 ; minuh
 
 ; CHECK: test_18:
-; CHECK: v0.uh = vmin(v1.uh,v0.uh)
+; CHECK: v0.uh = vmin(v0.uh,v1.uh)
 define <64 x i16> @test_18(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp ult <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_19:
 ; CHECK: v0.uh = vmin(v0.uh,v1.uh)
 define <64 x i16> @test_19(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp ule <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_1a:
 ; CHECK: v0.uh = vmin(v0.uh,v1.uh)
 define <64 x i16> @test_1a(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp ugt <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_1b:
-; CHECK: v0.uh = vmin(v1.uh,v0.uh)
+; CHECK: v0.uh = vmin(v0.uh,v1.uh)
 define <64 x i16> @test_1b(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp uge <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0
   ret <64 x i16> %t1
 }
 
 ; maxuh
 
 ; CHECK: test_1c:
-; CHECK: v0.uh = vmax(v1.uh,v0.uh)
+; CHECK: v0.uh = vmax(v0.uh,v1.uh)
 define <64 x i16> @test_1c(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp ult <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_1d:
 ; CHECK: v0.uh = vmax(v0.uh,v1.uh)
 define <64 x i16> @test_1d(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp ule <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_1e:
 ; CHECK: v0.uh = vmax(v0.uh,v1.uh)
 define <64 x i16> @test_1e(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp ugt <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
   ret <64 x i16> %t1
 }
 
 ; CHECK: test_1f:
-; CHECK: v0.uh = vmax(v1.uh,v0.uh)
+; CHECK: v0.uh = vmax(v0.uh,v1.uh)
 define <64 x i16> @test_1f(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp uge <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
   ret <64 x i16> %t1
 }
 
 ; minw
 
 ; CHECK: test_20:
-; CHECK: v0.w = vmin(v1.w,v0.w)
+; CHECK: v0.w = vmin(v0.w,v1.w)
 define <32 x i32> @test_20(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp slt <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
   ret <32 x i32> %t1
 }
 
 ; CHECK: test_21:
 ; CHECK: v0.w = vmin(v0.w,v1.w)
 define <32 x i32> @test_21(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp sle <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
   ret <32 x i32> %t1
 }
 
 ; CHECK: test_22:
 ; CHECK: v0.w = vmin(v0.w,v1.w)
 define <32 x i32> @test_22(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp sgt <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v1, <32 x i32> %v0
   ret <32 x i32> %t1
 }
 
 ; CHECK: test_23:
-; CHECK: v0.w = vmin(v1.w,v0.w)
+; CHECK: v0.w = vmin(v0.w,v1.w)
 define <32 x i32> @test_23(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp sge <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v1, <32 x i32> %v0
   ret <32 x i32> %t1
 }
 
 ; maxw
 
 ; CHECK: test_24:
-; CHECK: v0.w = vmax(v1.w,v0.w)
+; CHECK: v0.w = vmax(v0.w,v1.w)
 define <32 x i32> @test_24(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp slt <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v1, <32 x i32> %v0
   ret <32 x i32> %t1
 }
 
 ; CHECK: test_25:
 ; CHECK: v0.w = vmax(v0.w,v1.w)
 define <32 x i32> @test_25(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp sle <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v1, <32 x i32> %v0
   ret <32 x i32> %t1
 }
 
 ; CHECK: test_26:
 ; CHECK: v0.w = vmax(v0.w,v1.w)
 define <32 x i32> @test_26(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp sgt <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
   ret <32 x i32> %t1
 }
 
 ; CHECK: test_27:
-; CHECK: v0.w = vmax(v1.w,v0.w)
+; CHECK: v0.w = vmax(v0.w,v1.w)
 define <32 x i32> @test_27(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp sge <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
   ret <32 x i32> %t1
 }
 
 attributes #0 = { readnone nounwind "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length128b" }
 

llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; minb
 
 ; CHECK: test_00:
-; CHECK: v0.b = vmin(v1.b,v0.b)
+; CHECK: v0.b = vmin(v0.b,v1.b)
 define <64 x i8> @test_00(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp slt <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_01:
 ; CHECK: v0.b = vmin(v0.b,v1.b)
 define <64 x i8> @test_01(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp sle <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_02:
 ; CHECK: v0.b = vmin(v0.b,v1.b)
 define <64 x i8> @test_02(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp sgt <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_03:
-; CHECK: v0.b = vmin(v1.b,v0.b)
+; CHECK: v0.b = vmin(v0.b,v1.b)
 define <64 x i8> @test_03(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp sge <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0
   ret <64 x i8> %t1
 }
 
 ; maxb
 
 ; CHECK: test_04:
-; CHECK: v0.b = vmax(v1.b,v0.b)
+; CHECK: v0.b = vmax(v0.b,v1.b)
 define <64 x i8> @test_04(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp slt <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_05:
 ; CHECK: v0.b = vmax(v0.b,v1.b)
 define <64 x i8> @test_05(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp sle <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_06:
 ; CHECK: v0.b = vmax(v0.b,v1.b)
 define <64 x i8> @test_06(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp sgt <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_07:
-; CHECK: v0.b = vmax(v1.b,v0.b)
+; CHECK: v0.b = vmax(v0.b,v1.b)
 define <64 x i8> @test_07(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp sge <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
   ret <64 x i8> %t1
 }
 
 ; minub
 
 ; CHECK: test_08:
-; CHECK: v0.ub = vmin(v1.ub,v0.ub)
+; CHECK: v0.ub = vmin(v0.ub,v1.ub)
 define <64 x i8> @test_08(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp ult <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_09:
 ; CHECK: v0.ub = vmin(v0.ub,v1.ub)
 define <64 x i8> @test_09(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp ule <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_0a:
 ; CHECK: v0.ub = vmin(v0.ub,v1.ub)
 define <64 x i8> @test_0a(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp ugt <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_0b:
-; CHECK: v0.ub = vmin(v1.ub,v0.ub)
+; CHECK: v0.ub = vmin(v0.ub,v1.ub)
 define <64 x i8> @test_0b(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp uge <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0
   ret <64 x i8> %t1
 }
 
 ; maxub
 
 ; CHECK: test_0c:
-; CHECK: v0.ub = vmax(v1.ub,v0.ub)
+; CHECK: v0.ub = vmax(v0.ub,v1.ub)
 define <64 x i8> @test_0c(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp ult <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_0d:
 ; CHECK: v0.ub = vmax(v0.ub,v1.ub)
 define <64 x i8> @test_0d(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp ule <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_0e:
 ; CHECK: v0.ub = vmax(v0.ub,v1.ub)
 define <64 x i8> @test_0e(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp ugt <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
   ret <64 x i8> %t1
 }
 
 ; CHECK: test_0f:
-; CHECK: v0.ub = vmax(v1.ub,v0.ub)
+; CHECK: v0.ub = vmax(v0.ub,v1.ub)
 define <64 x i8> @test_0f(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp uge <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
   ret <64 x i8> %t1
 }
 
 ; minh
 
 ; CHECK: test_10:
-; CHECK: v0.h = vmin(v1.h,v0.h)
+; CHECK: v0.h = vmin(v0.h,v1.h)
 define <32 x i16> @test_10(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp slt <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_11:
 ; CHECK: v0.h = vmin(v0.h,v1.h)
 define <32 x i16> @test_11(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp sle <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_12:
 ; CHECK: v0.h = vmin(v0.h,v1.h)
 define <32 x i16> @test_12(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp sgt <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_13:
-; CHECK: v0.h = vmin(v1.h,v0.h)
+; CHECK: v0.h = vmin(v0.h,v1.h)
 define <32 x i16> @test_13(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp sge <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0
   ret <32 x i16> %t1
 }
 
 ; maxh
 
 ; CHECK: test_14:
-; CHECK: v0.h = vmax(v1.h,v0.h)
+; CHECK: v0.h = vmax(v0.h,v1.h)
 define <32 x i16> @test_14(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp slt <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_15:
 ; CHECK: v0.h = vmax(v0.h,v1.h)
 define <32 x i16> @test_15(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp sle <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_16:
 ; CHECK: v0.h = vmax(v0.h,v1.h)
 define <32 x i16> @test_16(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp sgt <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_17:
-; CHECK: v0.h = vmax(v1.h,v0.h)
+; CHECK: v0.h = vmax(v0.h,v1.h)
 define <32 x i16> @test_17(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp sge <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
   ret <32 x i16> %t1
 }
 
 ; minuh
 
 ; CHECK: test_18:
-; CHECK: v0.uh = vmin(v1.uh,v0.uh)
+; CHECK: v0.uh = vmin(v0.uh,v1.uh)
 define <32 x i16> @test_18(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp ult <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_19:
 ; CHECK: v0.uh = vmin(v0.uh,v1.uh)
 define <32 x i16> @test_19(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp ule <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_1a:
 ; CHECK: v0.uh = vmin(v0.uh,v1.uh)
 define <32 x i16> @test_1a(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp ugt <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_1b:
-; CHECK: v0.uh = vmin(v1.uh,v0.uh)
+; CHECK: v0.uh = vmin(v0.uh,v1.uh)
 define <32 x i16> @test_1b(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp uge <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0
   ret <32 x i16> %t1
 }
 
 ; maxuh
 
 ; CHECK: test_1c:
-; CHECK: v0.uh = vmax(v1.uh,v0.uh)
+; CHECK: v0.uh = vmax(v0.uh,v1.uh)
 define <32 x i16> @test_1c(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp ult <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_1d:
 ; CHECK: v0.uh = vmax(v0.uh,v1.uh)
 define <32 x i16> @test_1d(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp ule <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_1e:
 ; CHECK: v0.uh = vmax(v0.uh,v1.uh)
 define <32 x i16> @test_1e(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp ugt <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
   ret <32 x i16> %t1
 }
 
 ; CHECK: test_1f:
-; CHECK: v0.uh = vmax(v1.uh,v0.uh)
+; CHECK: v0.uh = vmax(v0.uh,v1.uh)
 define <32 x i16> @test_1f(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp uge <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
   ret <32 x i16> %t1
 }
 
 ; minw
 
 ; CHECK: test_20:
-; CHECK: v0.w = vmin(v1.w,v0.w)
+; CHECK: v0.w = vmin(v0.w,v1.w)
 define <16 x i32> @test_20(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp slt <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
   ret <16 x i32> %t1
 }
 
 ; CHECK: test_21:
 ; CHECK: v0.w = vmin(v0.w,v1.w)
 define <16 x i32> @test_21(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp sle <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
   ret <16 x i32> %t1
 }
 
 ; CHECK: test_22:
 ; CHECK: v0.w = vmin(v0.w,v1.w)
 define <16 x i32> @test_22(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp sgt <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v1, <16 x i32> %v0
   ret <16 x i32> %t1
 }
 
 ; CHECK: test_23:
-; CHECK: v0.w = vmin(v1.w,v0.w)
+; CHECK: v0.w = vmin(v0.w,v1.w)
 define <16 x i32> @test_23(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp sge <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v1, <16 x i32> %v0
   ret <16 x i32> %t1
 }
 
 ; maxw
 
 ; CHECK: test_24:
-; CHECK: v0.w = vmax(v1.w,v0.w)
+; CHECK: v0.w = vmax(v0.w,v1.w)
 define <16 x i32> @test_24(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp slt <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v1, <16 x i32> %v0
   ret <16 x i32> %t1
 }
 
 ; CHECK: test_25:
 ; CHECK: v0.w = vmax(v0.w,v1.w)
 define <16 x i32> @test_25(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp sle <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v1, <16 x i32> %v0
   ret <16 x i32> %t1
 }
 
 ; CHECK: test_26:
 ; CHECK: v0.w = vmax(v0.w,v1.w)
 define <16 x i32> @test_26(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp sgt <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
   ret <16 x i32> %t1
 }
 
 ; CHECK: test_27:
-; CHECK: v0.w = vmax(v1.w,v0.w)
+; CHECK: v0.w = vmax(v0.w,v1.w)
 define <16 x i32> @test_27(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp sge <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
   ret <16 x i32> %t1
 }
 
 attributes #0 = { readnone nounwind "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" }