[TableGen][SchedModels] Get rid of hasVariant. NFC

[evgeny777]

Summary

substituteVariantOperand already has the checking logic, so we don't really need this function. Subtarget files are unchanged by the patch.

[andreadb]

I've only skimmed through the code, but it looks like a nice improvement.

When you say that " Subtarget files are unchanged by the patch", does it mean that you have checked all the targets or just ARM?

[evgeny777]

When you say that " Subtarget files are unchanged by the patch", does it mean that you have checked all the targets or just ARM?

I checked ARM, AArch64 and X86. Does any other have scheduling enabled?

[andreadb]

In D92026#2413946, @evgeny777 wrote:

When you say that " Subtarget files are unchanged by the patch", does it mean that you have checked all the targets or just ARM?

I checked ARM, AArch64 and X86. Does any other have scheduling enabled?

I don't know to be honest.
A quick grep shows that Target/AMDGPU/SISchedule.td has a SchedReadVariant and a SchedWriteVariant.

[evgeny777]

@andreadb Built all targets, looks like none is touched (checked RISCV, AMDGPU, PPC, Lanai, etc)

[andreadb]

Thanks for checking.

LGTM

llvm/utils/TableGen/CodeGenSchedule.cpp

 class PredTransitions {
   CodeGenSchedModels &SchedModels;
 
 public:
   std::vector<PredTransition> TransVec;
 
   PredTransitions(CodeGenSchedModels &sm): SchedModels(sm) {}
 
-  void substituteVariantOperand(const SmallVectorImpl<unsigned> &RWSeq,
+  bool substituteVariantOperand(const SmallVectorImpl<unsigned> &RWSeq,
                                 bool IsRead, bool IsForAnyCPU,
                                 unsigned StartIdx);
 
-  void substituteVariants(const PredTransition &Trans);
+  bool substituteVariants(const PredTransition &Trans);
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 
 private:
   bool mutuallyExclusive(Record *PredDef, ArrayRef<Record *> Preds,
                          ArrayRef<PredCheck> Term);
if (AliasRW.IsSequence) {
                                SchedModels))
           return true;
       }
     }
   }
   return false;
 }
 
-static bool hasVariant(ArrayRef<PredTransition> Transitions,
-                       CodeGenSchedModels &SchedModels) {
-  for (const PredTransition &PTI : Transitions) {
-    for (const SmallVectorImpl<unsigned> &WSI : PTI.WriteSequences)
-      for (unsigned WI : WSI)
-        if (hasAliasedVariants(SchedModels.getSchedWrite(WI), SchedModels))
-          return true;
-
-    for (const SmallVectorImpl<unsigned> &RSI : PTI.ReadSequences)
-      for (unsigned RI : RSI)
-        if (hasAliasedVariants(SchedModels.getSchedRead(RI), SchedModels))
-          return true;
-  }
-  return false;
-}
-
 static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants,
                                               ArrayRef<unsigned> ProcIndices) {
   std::vector<Record *> Preds;
   for (auto &Variant : Variants) {
     assert(Variant.VarOrSeqDef->isSubClassOf("SchedVar"));
     if (ProcIndices[0] && Variant.ProcIdx)
       if (!llvm::count(ProcIndices, Variant.ProcIdx))
         continue;
else {
     Seq.insert(Seq.end(), ExpandedRWs.begin(), ExpandedRWs.end());
   }
 }
 
 // RWSeq is a sequence of all Reads or all Writes for the next read or write
 // operand. StartIdx is an index into TransVec where partial results
 // starts. RWSeq must be applied to all transitions between StartIdx and the end
 // of TransVec.
-void PredTransitions::substituteVariantOperand(
+bool PredTransitions::substituteVariantOperand(
     const SmallVectorImpl<unsigned> &RWSeq, bool IsRead, bool IsForAnyCPU,
     unsigned StartIdx) {
 
   auto CollectAndAddVariants = [&](unsigned TransIdx,
                                    const CodeGenSchedRW &SchedRW) {
     // Distribute this partial PredTransition across intersecting variants.
     // This will push a copies of TransVec[TransIdx] on the back of TransVec.
     std::vector<TransVariant> IntersectingVariants;
     getIntersectingVariants(SchedRW, TransIdx, IntersectingVariants);
     // Now expand each variant on top of its copy of the transition.
     for (const TransVariant &IV : IntersectingVariants)
       pushVariant(IV, IsRead);
     return !IntersectingVariants.empty();
   };
 
+  bool Subst = false;
   // Visit each original RW within the current sequence.
   for (SmallVectorImpl<unsigned>::const_iterator
          RWI = RWSeq.begin(), RWE = RWSeq.end(); RWI != RWE; ++RWI) {
     const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(*RWI, IsRead);
     // Push this RW on all partial PredTransitions or distribute variants.
     // New PredTransitions may be pushed within this loop which should not be
     // revisited (TransEnd must be loop invariant).
     bool HasAliases = false, WasPushed = false;
     for (unsigned TransIdx = StartIdx, TransEnd = TransVec.size();
          TransIdx != TransEnd; ++TransIdx) {
       // In the common case, push RW onto the current operand's sequence.
       if (!hasAliasedVariants(SchedRW, SchedModels)) {
         if (IsRead)
           TransVec[TransIdx].ReadSequences.back().push_back(*RWI);
         else
           TransVec[TransIdx].WriteSequences.back().push_back(*RWI);
         continue;
       }
       HasAliases = true;
       WasPushed |= CollectAndAddVariants(TransIdx, SchedRW);
+      Subst |= WasPushed;
     }
     if (IsRead && IsForAnyCPU && HasAliases && !WasPushed) {
       // If we're here this means that in some sched class:
       // a) We have read variant for CPU A
       // b) We have write variant for CPU B
       // b) We don't have write variant for CPU A
       // d) We must expand all read/write variants (IsForAnyCPU is true)
       // e) We couldn't expand SchedRW because TransVec doesn't have
       //    any transition with compatible CPU ID.
       // In such case we create new empty transition with zero (AnyCPU)
       // index.
       TransVec.reserve(TransVec.size() + 1);
       TransVec.emplace_back(TransVec[StartIdx].PredTerm);
       TransVec.back().ReadSequences.emplace_back();
-      CollectAndAddVariants(TransVec.size() - 1, SchedRW);
+      Subst |= CollectAndAddVariants(TransVec.size() - 1, SchedRW);
     }
   }
+  return Subst;
 }
 
 // For each variant of a Read/Write in Trans, substitute the sequence of
 // Read/Writes guarded by the variant. This is exponential in the number of
 // variant Read/Writes, but in practice detection of mutually exclusive
 // predicates should result in linear growth in the total number variants.
 //
 // This is one step in a breadth-first search of nested variants.
-void PredTransitions::substituteVariants(const PredTransition &Trans) {
+bool PredTransitions::substituteVariants(const PredTransition &Trans) {
   // Build up a set of partial results starting at the back of
   // PredTransitions. Remember the first new transition.
   unsigned StartIdx = TransVec.size();
+  bool Subst = false;
   TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndices);
 
   bool IsForAnyCPU = llvm::count(Trans.ProcIndices, 0);
   // Visit each original write sequence.
   for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
          WSI = Trans.WriteSequences.begin(), WSE = Trans.WriteSequences.end();
        WSI != WSE; ++WSI) {
     // Push a new (empty) write sequence onto all partial Transitions.
     for (std::vector<PredTransition>::iterator I =
            TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
       I->WriteSequences.emplace_back();
     }
-    substituteVariantOperand(*WSI, /*IsRead=*/false, IsForAnyCPU, StartIdx);
+    Subst |= substituteVariantOperand(*WSI, /*IsRead=*/false, IsForAnyCPU, StartIdx);
   }
   // Visit each original read sequence.
   for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
          RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end();
        RSI != RSE; ++RSI) {
     // Push a new (empty) read sequence onto all partial Transitions.
     for (std::vector<PredTransition>::iterator I =
            TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
       I->ReadSequences.emplace_back();
     }
-    substituteVariantOperand(*RSI, /*IsRead=*/true, IsForAnyCPU, StartIdx);
+    Subst |= substituteVariantOperand(*RSI, /*IsRead=*/true, IsForAnyCPU, StartIdx);
   }
+  return Subst;
 }
 
 static void addSequences(CodeGenSchedModels &SchedModels,
                          const SmallVectorImpl<SmallVector<unsigned, 4>> &Seqs,
                          IdxVec &Result, bool IsRead) {
   for (const auto &S : Seqs)
     if (!S.empty())
       Result.push_back(SchedModels.findOrInsertRW(S, IsRead));
for (unsigned ReadIdx : OperReads) {
     SmallVectorImpl<unsigned> &Seq = LastTransitions[0].ReadSequences.back();
     Seq.append(ReadSeq.begin(), ReadSeq.end());
     LLVM_DEBUG(dbgs() << "("; dumpIdxVec(Seq); dbgs() << ") ");
   }
   LLVM_DEBUG(dbgs() << '\n');
 
   // Collect all PredTransitions for individual operands.
   // Iterate until no variant writes remain.
-  while (hasVariant(LastTransitions, *this)) {
+  bool SubstitutedAny;
+  do {
+    SubstitutedAny = false;
     PredTransitions Transitions(*this);
     for (const PredTransition &Trans : LastTransitions)
-      Transitions.substituteVariants(Trans);
+      SubstitutedAny |= Transitions.substituteVariants(Trans);
     LLVM_DEBUG(Transitions.dump());
     LastTransitions.swap(Transitions.TransVec);
-  }
+  } while(SubstitutedAny);
   // If the first transition has no variants, nothing to do.
   if (LastTransitions[0].PredTerm.empty())
     return;
 
   // WARNING: We are about to mutate the SchedClasses vector. Do not refer to
   // OperWrites, OperReads, or ProcIndices after calling inferFromTransitions.
   inferFromTransitions(LastTransitions, FromClassIdx, *this);
 }