[AMDGPU][MC] Improved diagnostic messages

[dp]

Summary

Improved diagnostic messages, partially fixed bug 47518.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

private:
   SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;
   SMLoc getLitLoc(const OperandVector &Operands) const;
   SMLoc getConstLoc(const OperandVector &Operands) const;
 
   bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
   bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
   bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
   bool validateSOPLiteral(const MCInst &Inst) const;
-  bool validateConstantBusLimitations(const MCInst &Inst);
-  bool validateEarlyClobberLimitations(const MCInst &Inst);
+  bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);
+  bool validateEarlyClobberLimitations(const MCInst &Inst, const OperandVector &Operands);
   bool validateIntClampSupported(const MCInst &Inst);
   bool validateMIMGAtomicDMask(const MCInst &Inst);
   bool validateMIMGGatherDMask(const MCInst &Inst);
   bool validateMovrels(const MCInst &Inst);
   bool validateMIMGDataSize(const MCInst &Inst);
   bool validateMIMGAddrSize(const MCInst &Inst);
   bool validateMIMGD16(const MCInst &Inst);
   bool validateMIMGDim(const MCInst &Inst);
   bool validateLdsDirect(const MCInst &Inst);
   bool validateOpSel(const MCInst &Inst);
   bool validateVccOperand(unsigned Reg) const;
   bool validateVOP3Literal(const MCInst &Inst, const OperandVector &Operands);
-  bool validateMAIAccWrite(const MCInst &Inst);
+  bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
   bool validateDivScale(const MCInst &Inst);
   bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
                              const SMLoc &IDLoc);
   unsigned getConstantBusLimit(unsigned Opcode) const;
   bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
   bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
   unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
 
if (MO.isImm()) {
     const MCRegisterInfo *TRI = getContext().getRegisterInfo();
     auto PReg = mc2PseudoReg(Reg);
     return isSGPR(PReg, TRI) && PReg != SGPR_NULL;
   } else {
     return true;
   }
 }
 
-bool AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) {
+bool
+AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst,
+                                                const OperandVector &Operands) {
   const unsigned Opcode = Inst.getOpcode();
   const MCInstrDesc &Desc = MII.get(Opcode);
+  unsigned LastSGPR = AMDGPU::NoRegister;
   unsigned ConstantBusUseCount = 0;
   unsigned NumLiterals = 0;
   unsigned LiteralSize;
 
   if (Desc.TSFlags &
       (SIInstrFlags::VOPC |
        SIInstrFlags::VOP1 | SIInstrFlags::VOP2 |
        SIInstrFlags::VOP3 | SIInstrFlags::VOP3P |
if (Desc.TSFlags &
     const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
 
     for (int OpIdx : OpIndices) {
       if (OpIdx == -1) break;
 
       const MCOperand &MO = Inst.getOperand(OpIdx);
       if (usesConstantBus(Inst, OpIdx)) {
         if (MO.isReg()) {
-          const unsigned Reg = mc2PseudoReg(MO.getReg());
+          LastSGPR = mc2PseudoReg(MO.getReg());
           // Pairs of registers with a partial intersections like these
           //   s0, s[0:1]
           //   flat_scratch_lo, flat_scratch
           //   flat_scratch_lo, flat_scratch_hi
           // are theoretically valid but they are disabled anyway.
           // Note that this code mimics SIInstrInfo::verifyInstruction
-          if (!SGPRsUsed.count(Reg)) {
-            SGPRsUsed.insert(Reg);
+          if (!SGPRsUsed.count(LastSGPR)) {
+            SGPRsUsed.insert(LastSGPR);
             ++ConstantBusUseCount;
           }
         } else { // Expression or a literal
 
           if (Desc.OpInfo[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)
             continue; // special operand like VINTERP attr_chan
 
           // An instruction may use only one literal.
for (int OpIdx : OpIndices) {
             NumLiterals = 2;
           }
         }
       }
     }
   }
   ConstantBusUseCount += NumLiterals;
 
-  return ConstantBusUseCount <= getConstantBusLimit(Opcode);
+  if (ConstantBusUseCount <= getConstantBusLimit(Opcode))
+    return true;
+
+  SMLoc LitLoc = getLitLoc(Operands);
+  SMLoc RegLoc = getRegLoc(LastSGPR, Operands);
+  SMLoc Loc = (LitLoc.getPointer() < RegLoc.getPointer()) ? RegLoc : LitLoc;
+  Error(Loc, "invalid operand (violates constant bus restrictions)");
+  return false;
 }
 
-bool AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst) {
+bool
+AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst,
+                                                 const OperandVector &Operands) {
   const unsigned Opcode = Inst.getOpcode();
   const MCInstrDesc &Desc = MII.get(Opcode);
 
   const int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
   if (DstIdx == -1 ||
       Desc.getOperandConstraint(DstIdx, MCOI::EARLY_CLOBBER) == -1) {
     return true;
   }
AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst,
   const int SrcIndices[] = { Src0Idx, Src1Idx, Src2Idx };
 
   for (int SrcIdx : SrcIndices) {
     if (SrcIdx == -1) break;
     const MCOperand &Src = Inst.getOperand(SrcIdx);
     if (Src.isReg()) {
       const unsigned SrcReg = mc2PseudoReg(Src.getReg());
       if (isRegIntersect(DstReg, SrcReg, TRI)) {
+        Error(getRegLoc(SrcReg, Operands),
+          "destination must be different than all sources");
         return false;
       }
     }
   }
 
   return true;
 }
 
bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst) {
   if (!Src0.isReg())
     return false;
 
   auto Reg = Src0.getReg();
   const MCRegisterInfo *TRI = getContext().getRegisterInfo();
   return !isSGPR(mc2PseudoReg(Reg), TRI);
 }
 
-bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst) {
+bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,
+                                          const OperandVector &Operands) {
 
   const unsigned Opc = Inst.getOpcode();
 
   if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi)
     return true;
 
   const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
   assert(Src0Idx != -1);
 
   const MCOperand &Src0 = Inst.getOperand(Src0Idx);
   if (!Src0.isReg())
     return true;
 
   auto Reg = Src0.getReg();
   const MCRegisterInfo *TRI = getContext().getRegisterInfo();
   if (isSGPR(mc2PseudoReg(Reg), TRI)) {
-    Error(getLoc(), "source operand must be either a VGPR or an inline constant");
+    Error(getRegLoc(mc2PseudoReg(Reg), Operands),
+          "source operand must be either a VGPR or an inline constant");
     return false;
   }
 
   return true;
 }
 
 bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {
   switch (Inst.getOpcode()) {
bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
   if (!validateSOPLiteral(Inst)) {
     Error(getLitLoc(Operands),
       "only one literal operand is allowed");
     return false;
   }
   if (!validateVOP3Literal(Inst, Operands)) {
     return false;
   }
-  if (!validateConstantBusLimitations(Inst)) {
-    Error(IDLoc,
-      "invalid operand (violates constant bus restrictions)");
+  if (!validateConstantBusLimitations(Inst, Operands)) {
     return false;
   }
-  if (!validateEarlyClobberLimitations(Inst)) {
-    Error(IDLoc,
-      "destination must be different than all sources");
+  if (!validateEarlyClobberLimitations(Inst, Operands)) {
     return false;
   }
   if (!validateIntClampSupported(Inst)) {
     Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands),
       "integer clamping is not supported on this GPU");
     return false;
   }
   if (!validateOpSel(Inst)) {
if (!validateMovrels(Inst)) {
     return false;
   }
   if (!validateFlatOffset(Inst, Operands)) {
     return false;
   }
   if (!validateSMEMOffset(Inst, Operands)) {
     return false;
   }
-  if (!validateMAIAccWrite(Inst)) {
+  if (!validateMAIAccWrite(Inst, Operands)) {
     return false;
   }
   if (!validateDivScale(Inst)) {
     Error(IDLoc, "ABS not allowed in VOP3B instructions");
     return false;
   }
   if (!validateCoherencyBits(Inst, Operands, IDLoc)) {
     return false;

llvm/test/MC/AMDGPU/gfx10_err_pos.s

 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+WavefrontSize32,-WavefrontSize64 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
 
 //==============================================================================
 // destination must be different than all sources
 
 v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5]
 // CHECK: error: destination must be different than all sources
 // CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5]
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                          ^
 
+v_mqsad_pk_u16_u8 v[0:1], v[2:3], v0, v[4:5]
+// CHECK: error: destination must be different than all sources
+// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v0, v[4:5]
+// CHECK-NEXT:{{^}}                                  ^
+
+v_mqsad_pk_u16_u8 v[0:1], v[2:3], v1, v[4:5]
+// CHECK: error: destination must be different than all sources
+// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v1, v[4:5]
+// CHECK-NEXT:{{^}}                                  ^
+
+v_mqsad_pk_u16_u8 v[0:1], v[2:3], v9, v[0:1]
+// CHECK: error: destination must be different than all sources
+// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v9, v[0:1]
+// CHECK-NEXT:{{^}}                                      ^
+
 //==============================================================================
 // dim modifier is required on this GPU
 
 image_atomic_add v252, v2, s[8:15]
 // CHECK: error: dim modifier is required on this GPU
 // CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15]
 // CHECK-NEXT:{{^}}^
 

 // CHECK-NEXT:{{^}}                                ^
 
 //==============================================================================
 // invalid operand (violates constant bus restrictions)
 
 v_ashrrev_i64 v[0:1], 0x100, s[0:1]
 // CHECK: error: invalid operand (violates constant bus restrictions)
 // CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], 0x100, s[0:1]
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                             ^
 
+v_ashrrev_i64 v[0:1], s3, s[0:1]
+// CHECK: error: invalid operand (violates constant bus restrictions)
+// CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], s3, s[0:1]
+// CHECK-NEXT:{{^}}                          ^
+
 v_bfe_u32 v0, s1, 0x3039, s2
 // CHECK: error: invalid operand (violates constant bus restrictions)
 // CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, 0x3039, s2
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                          ^
 
+v_bfe_u32 v0, s1, s2, s3
+// CHECK: error: invalid operand (violates constant bus restrictions)
+// CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, s2, s3
+// CHECK-NEXT:{{^}}                      ^
+
 v_div_fmas_f32 v5, s3, 0x123, v3
 // CHECK: error: invalid operand (violates constant bus restrictions)
 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, 0x123, v3
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                       ^
 
+v_div_fmas_f32 v5, s3, v3, 0x123
+// CHECK: error: invalid operand (violates constant bus restrictions)
+// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, v3, 0x123
+// CHECK-NEXT:{{^}}                           ^
+
+v_div_fmas_f32 v5, 0x123, v3, s3
+// CHECK: error: invalid operand (violates constant bus restrictions)
+// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, 0x123, v3, s3
+// CHECK-NEXT:{{^}}                              ^
+
+v_div_fmas_f32 v5, s3, s4, v3
+// CHECK: error: invalid operand (violates constant bus restrictions)
+// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, s4, v3
+// CHECK-NEXT:{{^}}                       ^
+
 //==============================================================================
 // invalid operand for instruction
 
 buffer_load_dword v5, off, s[8:11], s3 tfe lds
 // CHECK: error: invalid operand for instruction
 // CHECK-NEXT:{{^}}buffer_load_dword v5, off, s[8:11], s3 tfe lds
 // CHECK-NEXT:{{^}}                                           ^
 

llvm/test/MC/AMDGPU/gfx908_err_pos.s

 // CHECK-NEXT:{{^}}                                         ^
 
 //==============================================================================
 // source operand must be either a VGPR or an inline constant
 
 v_accvgpr_write a2, execz
 // CHECK: error: source operand must be either a VGPR or an inline constant
 // CHECK-NEXT:{{^}}v_accvgpr_write a2, execz
-// CHECK-NEXT:{{^}}                         ^
+// CHECK-NEXT:{{^}}                    ^

llvm/test/MC/AMDGPU/gfx9_err_pos.s

 // CHECK-NEXT:{{^}}                     ^
 
 //==============================================================================
 // invalid operand (violates constant bus restrictions)
 
 v_add_f32_e64 v0, flat_scratch_hi, m0
 // CHECK: error: invalid operand (violates constant bus restrictions)
 // CHECK-NEXT:{{^}}v_add_f32_e64 v0, flat_scratch_hi, m0
-// CHECK-NEXT:{{^}}^
+// CHECK-NEXT:{{^}}                                   ^
 
+v_madak_f32 v5, s1, v2, 0xa1b1c1d1
+// CHECK: error: invalid operand (violates constant bus restrictions)
+// CHECK-NEXT:{{^}}v_madak_f32 v5, s1, v2, 0xa1b1c1d1
+// CHECK-NEXT:{{^}}                ^
+
+v_madmk_f32 v5, s1, 0x11213141, v255
+// CHECK: error: invalid operand (violates constant bus restrictions)
+// CHECK-NEXT:{{^}}v_madmk_f32 v5, s1, 0x11213141, v255
+// CHECK-NEXT:{{^}}                ^
+
 //==============================================================================
 // literal operands are not supported
 
 v_bfe_u32 v0, v2, v3, undef
 // CHECK: error: literal operands are not supported
 // CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, v3, undef
 // CHECK-NEXT:{{^}}                      ^