[AArch64] Add codegen for Armv8.3 Load-AcquirePC instructions

[al3xtjames]

Summary

Armv8.3 introduced support for Load-AcquirePC instructions to support
the weaker Release Consistency processor consistent (RCpc) model, which
corresponds to the Acquire/Release semantics used in LLVM. In
constrast, the existing Load-Acquire instructions in Armv8 support the
Release Consistency sequentially consistent (RCsc) model, which
corresponds to the SequentiallyConsistent semantics used in LLVM.

Use the Load-AcquirePC instructions for atomic loads with acquire
semantics when supported.

Please let me know if there's a better way to make these changes to
AArch64InstrAtomics.td, I'm not too familiar with TableGen.

llvm/lib/Target/AArch64/AArch64InstrAtomics.td

 //===----------------------------------
 // Atomic loads
 //===----------------------------------
 
 // When they're actually atomic, only one addressing mode (GPR64sp) is
 // supported, but when they're relaxed and anything can be used, all the
 // standard modes would be valid and may give efficiency gains.
 
-// A atomic load operation that actually needs acquire semantics.
+// An atomic load operation that needs sequential consistency.
+class seq_cst_load<PatFrag base>
+  : PatFrag<(ops node:$ptr), (base node:$ptr)> {
+  let IsAtomic = 1;
+  let IsAtomicOrderingSequentiallyConsistent = 1;
+}
+
+// An atomic load operation that needs acquire semantics.
 class acquiring_load<PatFrag base>
   : PatFrag<(ops node:$ptr), (base node:$ptr)> {
   let IsAtomic = 1;
-  let IsAtomicOrderingAcquireOrStronger = 1;
+  let IsAtomicOrderingAcquire = 1;
 }
 
 // An atomic load operation that does not need either acquire or release
 // semantics.
 class relaxed_load<PatFrag base>
   : PatFrag<(ops node:$ptr), (base node:$ptr)> {
   let IsAtomic = 1;
   let IsAtomicOrderingAcquireOrStronger = 0;
 }
 
+let Predicates = [HasRCPC] in {
+  // v8.3 Release Consistent Processor Consistent support, optional in v8.2.
+  // 8-bit loads
+  def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDAPRB GPR64sp:$ptr)>;
+  // 16-bit loads
+  def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDAPRH GPR64sp:$ptr)>;
+  // 32-bit loads
+  def : Pat<(acquiring_load<atomic_load_32> GPR64sp:$ptr), (LDAPRW GPR64sp:$ptr)>;
+  // 64-bit loads
+  def : Pat<(acquiring_load<atomic_load_64> GPR64sp:$ptr), (LDAPRX GPR64sp:$ptr)>;
+}
+
 // 8-bit loads
+def : Pat<(seq_cst_load<atomic_load_8>  GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
 def : Pat<(acquiring_load<atomic_load_8>  GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
                                                      ro_Wextend8:$offset)),
           (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
                                                      ro_Xextend8:$offset)),
           (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
                                                     uimm12s1:$offset)),
           (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
 def : Pat<(relaxed_load<atomic_load_8>
                (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
           (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
 
 // 16-bit loads
+def : Pat<(seq_cst_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
 def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
                                                        ro_Wextend16:$extend)),
           (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
                                                        ro_Xextend16:$extend)),
           (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
 def : Pat<(relaxed_load<atomic_load_16> (am_indexed16 GPR64sp:$Rn,
                                                       uimm12s2:$offset)),
           (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
 def : Pat<(relaxed_load<atomic_load_16>
                (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
           (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
 
 // 32-bit loads
+def : Pat<(seq_cst_load<atomic_load_32> GPR64sp:$ptr), (LDARW GPR64sp:$ptr)>;
 def : Pat<(acquiring_load<atomic_load_32> GPR64sp:$ptr), (LDARW GPR64sp:$ptr)>;
 def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
                                                        ro_Wextend32:$extend)),
           (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
 def : Pat<(relaxed_load<atomic_load_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
                                                        ro_Xextend32:$extend)),
           (LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
 def : Pat<(relaxed_load<atomic_load_32> (am_indexed32 GPR64sp:$Rn,
                                                       uimm12s4:$offset)),
           (LDRWui GPR64sp:$Rn, uimm12s4:$offset)>;
 def : Pat<(relaxed_load<atomic_load_32>
                (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
           (LDURWi GPR64sp:$Rn, simm9:$offset)>;
 
 // 64-bit loads
+def : Pat<(seq_cst_load<atomic_load_64> GPR64sp:$ptr), (LDARX GPR64sp:$ptr)>;
 def : Pat<(acquiring_load<atomic_load_64> GPR64sp:$ptr), (LDARX GPR64sp:$ptr)>;
 def : Pat<(relaxed_load<atomic_load_64> (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
                                                        ro_Wextend64:$extend)),
           (LDRXroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
 def : Pat<(relaxed_load<atomic_load_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
                                                        ro_Xextend64:$extend)),
           (LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
 def : Pat<(relaxed_load<atomic_load_64> (am_indexed64 GPR64sp:$Rn,

llvm/test/CodeGen/AArch64/atomics-rcpc.ll

+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+rcpc -verify-machineinstrs < %s | FileCheck %s
+
+define i8 @test_load_8_rcpc(i8* %addr) {
+; CHECK-LABEL: test_load_8_rcpc:
+; CHECK: ldaprb w0, [x0]
+  %val = load atomic i8, i8* %addr acquire, align 1
+  ret i8 %val
+}
+
+define i8 @test_load_8_rcsc(i8* %addr) {
+; CHECK-LABEL: test_load_8_rcsc:
+; CHECK: ldarb w0, [x0]
+  %val = load atomic i8, i8* %addr seq_cst, align 1
+  ret i8 %val
+}
+
+define i16 @test_load_16_rcpc(i16* %addr) {
+; CHECK-LABEL: test_load_16_rcpc:
+; CHECK: ldaprh w0, [x0]
+  %val = load atomic i16, i16* %addr acquire, align 2
+  ret i16 %val
+}
+
+define i16 @test_load_16_rcsc(i16* %addr) {
+; CHECK-LABEL: test_load_16_rcsc:
+; CHECK: ldarh w0, [x0]
+  %val = load atomic i16, i16* %addr seq_cst, align 2
+  ret i16 %val
+}
+
+define i32 @test_load_32_rcpc(i32* %addr) {
+; CHECK-LABEL: test_load_32_rcpc:
+; CHECK: ldapr w0, [x0]
+  %val = load atomic i32, i32* %addr acquire, align 4
+  ret i32 %val
+}
+
+define i32 @test_load_32_rcsc(i32* %addr) {
+; CHECK-LABEL: test_load_32_rcsc:
+; CHECK: ldar w0, [x0]
+  %val = load atomic i32, i32* %addr seq_cst, align 4
+  ret i32 %val
+}
+
+define i64 @test_load_64_rcpc(i64* %addr) {
+; CHECK-LABEL: test_load_64_rcpc:
+; CHECK: ldapr x0, [x0]
+  %val = load atomic i64, i64* %addr acquire, align 8
+  ret i64 %val
+}
+
+define i64 @test_load_64_rcsc(i64* %addr) {
+; CHECK-LABEL: test_load_64_rcsc:
+; CHECK: ldar x0, [x0]
+  %val = load atomic i64, i64* %addr seq_cst, align 8
+  ret i64 %val
+}