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Differential D91755

[GlobalISel] Combine icmp eq/ne (ext (icmp cc, x, y)), true/false)
Needs ReviewPublic

Authored by paquette on Nov 18 2020, 4:43 PM.

Details

Reviewers
aemerson
arsenm
Summary

This implements the following combines:

icmp ne ([sz]ext (icmp cc, x, y)), 0) -> icmp cc, x, y
icmp eq, ([sz]ext (icmp cc x, y)), 0) -> icmp inv(cc), x, y
icmp ne, (zext (icmp cc, x, y)), 1) -> icmp inv(cc), x, y
icmp eq, (zext (icmp cc, x, y)), 1) -> icmp cc, x, y
icmp ne, (sext (icmp cc, x, y)), -1) -> icmp inv(cc), x, y
icmp eq, (sext (icmp cc, x, y)), -1) -> icmp cc, x, y

This is similar to a combine in TargetLowering::SimplifySetCC.

IR example: https://godbolt.org/z/qzx81v

Diff Detail

Event Timeline

paquette created this revision.Nov 18 2020, 4:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 18 2020, 4:44 PM
Herald added subscribers: hiraditya, rovka. · View Herald Transcript
paquette requested review of this revision.Nov 18 2020, 4:44 PM
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paquette added parent revisions: D91754: [GlobalISel] Add isConstFalseVal helper to Utils, D91753: [GlobalISel] Add an isExtendedTrueVal helper..Nov 18 2020, 4:48 PM
aemerson added inline comments.Nov 18 2020, 11:15 PM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
3149–3150

I'm not convinced this is necessary. If legality is something that a target should care about then I think they shouldn't add this combine post-legalization.

3172

SrcCmp is a better name?

3188

Same here.

arsenm added inline comments.Sep 28 2022, 2:18 PM
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
101

BuildFnTy already exists

Herald added a project: Restricted Project. · View Herald TranscriptSep 28 2022, 2:18 PM

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
25 lines
Target/
GlobalISel/
16 lines
lib/
CodeGen/
GlobalISel/
83 lines
test/
CodeGen/
AArch64/
GlobalISel/
372 lines

Diff 306262

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Linesstruct InstructionStepsMatchInfo {
/// Describes instructions to be built during a combine. /// Describes instructions to be built during a combine.
SmallVector<InstructionBuildSteps, 2> InstrsToBuild; SmallVector<InstructionBuildSteps, 2> InstrsToBuild;
InstructionStepsMatchInfo() = default; InstructionStepsMatchInfo() = default;
InstructionStepsMatchInfo( InstructionStepsMatchInfo(
std::initializer_list<InstructionBuildSteps> InstrsToBuild) std::initializer_list<InstructionBuildSteps> InstrsToBuild)
: InstrsToBuild(InstrsToBuild) {} : InstrsToBuild(InstrsToBuild) {}
}; };
/// A general function to apply to complete a combine. Used with the
/// applyMIRBuilderFn convenience combine.
///
/// \example
/// MatchInfo = [=](MachineIRBuilder &MIB, MachineInstr &MI) {
/// MIB.buildAdd(MI.getOperand(0).getReg(), AddLHS, AddRHS);
/// MI.eraseFromParent();
/// return true;
/// };
/// \endexample
///
/// If the above example is passed into applyMIRBuilderFn, then it will build
/// an add, and erase the MachineInstr.
using MIRBuilderFn = std::function<bool(MachineIRBuilder &, MachineInstr &)>;
arsenmUnsubmitted
Not Done
ReplyInline Actions

BuildFnTy already exists

arsenm: BuildFnTy already exists
class CombinerHelper { class CombinerHelper {
protected: protected:
MachineIRBuilder &Builder; MachineIRBuilder &Builder;
MachineRegisterInfo &MRI; MachineRegisterInfo &MRI;
GISelChangeObserver &Observer; GISelChangeObserver &Observer;
GISelKnownBits *KB; GISelKnownBits *KB;
MachineDominatorTree *MDT; MachineDominatorTree *MDT;
const LegalizerInfo *LI; const LegalizerInfo *LI;
▲ Show 20 Lines • Show All 279 Lines • ▼ Show 20 Linespublic:
bool replaceInstWithUndef(MachineInstr &MI); bool replaceInstWithUndef(MachineInstr &MI);
/// Delete \p MI and replace all of its uses with its \p OpIdx-th operand. /// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx); bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
/// Delete \p MI and replace all of its uses with \p Replacement. /// Delete \p MI and replace all of its uses with \p Replacement.
bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement); bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement);
/// Apply the combine described in the function \p MatchInfo.
bool applyMIRBuilderFn(MachineInstr &MI, MIRBuilderFn &MatchInfo);
/// Return true if \p MOP1 and \p MOP2 are register operands are defined by /// Return true if \p MOP1 and \p MOP2 are register operands are defined by
/// equivalent instructions. /// equivalent instructions.
bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2); bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
/// Return true if \p MOP is defined by a G_CONSTANT with a value equal to /// Return true if \p MOP is defined by a G_CONSTANT with a value equal to
/// \p C. /// \p C.
bool matchConstantOp(const MachineOperand &MOP, int64_t C); bool matchConstantOp(const MachineOperand &MOP, int64_t C);
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Linespublic:
bool applyPtrAddZero(MachineInstr &MI); bool applyPtrAddZero(MachineInstr &MI);
bool matchCombineInsertVecElts(MachineInstr &MI, bool matchCombineInsertVecElts(MachineInstr &MI,
SmallVectorImpl<Register> &MatchInfo); SmallVectorImpl<Register> &MatchInfo);
bool applyCombineInsertVecElts(MachineInstr &MI, bool applyCombineInsertVecElts(MachineInstr &MI,
SmallVectorImpl<Register> &MatchInfo); SmallVectorImpl<Register> &MatchInfo);
/// Match patterns involving a G_ICMP which uses a second, extended G_ICMP.
///
/// E.g.
///
/// icmp ne ([sz]ext (icmp cc, x, y)), 0) -> icmp cc, x, y
bool matchExtICmp(MachineInstr &MI, MIRBuilderFn &MatchInfo);
/// Try to transform \p MI by using all of the above /// Try to transform \p MI by using all of the above
/// combine functions. Returns true if changed. /// combine functions. Returns true if changed.
bool tryCombine(MachineInstr &MI); bool tryCombine(MachineInstr &MI);
private: private:
// Memcpy family optimization helpers. // Memcpy family optimization helpers.
bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src, bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
unsigned KnownLen, Align DstAlign, Align SrcAlign, unsigned KnownLen, Align DstAlign, Align SrcAlign,
Show All 24 Lines

llvm/include/llvm/Target/GlobalISel/Combine.td

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
class GIDefMatchData<string type> : GIDefKind { class GIDefMatchData<string type> : GIDefKind {
/// A C++ type name indicating the storage type. /// A C++ type name indicating the storage type.
string Type = type; string Type = type;
} }
def extending_load_matchdata : GIDefMatchData<"PreferredTuple">; def extending_load_matchdata : GIDefMatchData<"PreferredTuple">;
def indexed_load_store_matchdata : GIDefMatchData<"IndexedLoadStoreMatchInfo">; def indexed_load_store_matchdata : GIDefMatchData<"IndexedLoadStoreMatchInfo">;
def instruction_steps_matchdata: GIDefMatchData<"InstructionStepsMatchInfo">; def instruction_steps_matchdata: GIDefMatchData<"InstructionStepsMatchInfo">;
def mirbuilder_fn_matchdata: GIDefMatchData<"MIRBuilderFn">;
/// The operator at the root of a GICombineRule.Match dag. /// The operator at the root of a GICombineRule.Match dag.
def match; def match;
/// All arguments of the match operator must be either: /// All arguments of the match operator must be either:
/// * A subclass of GIMatchKind /// * A subclass of GIMatchKind
/// * A subclass of GIMatchKindWithArgs /// * A subclass of GIMatchKindWithArgs
/// * A subclass of Instruction /// * A subclass of Instruction
/// * A MIR code block (deprecated) /// * A MIR code block (deprecated)
▲ Show 20 Lines • Show All 440 Lines • ▼ Show 20 Linesdef combine_insert_vec_elts_build_vector : GICombineRule<
(match (wip_match_opcode G_INSERT_VECTOR_ELT):$root, (match (wip_match_opcode G_INSERT_VECTOR_ELT):$root,
[{ return Helper.matchCombineInsertVecElts(*${root}, ${info}); }]), [{ return Helper.matchCombineInsertVecElts(*${root}, ${info}); }]),
(apply [{ return Helper.applyCombineInsertVecElts(*${root}, ${info}); }])>; (apply [{ return Helper.applyCombineInsertVecElts(*${root}, ${info}); }])>;
// Currently only the one combine above. // Currently only the one combine above.
def insert_vec_elt_combines : GICombineGroup< def insert_vec_elt_combines : GICombineGroup<
[combine_insert_vec_elts_build_vector]>; [combine_insert_vec_elts_build_vector]>;
// icmp ne ([sz]ext (icmp cc, x, y)), 0) -> icmp cc, x, y
// icmp eq, ([sz]ext (icmp cc x, y)), 0) -> icmp inv(cc), x, y
// icmp ne, (zext (icmp cc, x, y)), 1) -> icmp inv(cc), x, y
// icmp eq, (zext (icmp cc, x, y)), 1) -> icmp cc, x, y
// icmp ne, (sext (icmp cc, x, y)), -1) -> icmp inv(cc), x, y
// icmp eq, (sext (icmp cc, x, y)), -1) -> icmp cc, x, y
def ext_icmp : GICombineRule<
(defs root:$root, mirbuilder_fn_matchdata:$info),
(match (wip_match_opcode G_ICMP):$root,
[{ return Helper.matchExtICmp(*${root}, ${info}); }]),
(apply [{ return Helper.applyMIRBuilderFn(*${root}, ${info}); }])>;
def icmp_combines : GICombineGroup<[ext_icmp]>;
// FIXME: These should use the custom predicate feature once it lands. // FIXME: These should use the custom predicate feature once it lands.
def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero, def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
undef_to_negative_one, undef_to_negative_one,
binop_left_undef_to_zero, binop_left_undef_to_zero,
propagate_undef_any_op, propagate_undef_any_op,
propagate_undef_all_ops, propagate_undef_all_ops,
propagate_undef_shuffle_mask, propagate_undef_shuffle_mask,
erase_undef_store]>; erase_undef_store]>;
Show All 22 Linesdef all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
hoist_logic_op_with_same_opcode_hands, hoist_logic_op_with_same_opcode_hands,
shl_ashr_to_sext_inreg, sext_inreg_of_load, shl_ashr_to_sext_inreg, sext_inreg_of_load,
width_reduction_combines, select_combines, width_reduction_combines, select_combines,
known_bits_simplifications, ext_ext_fold, known_bits_simplifications, ext_ext_fold,
not_cmp_fold, opt_brcond_by_inverting_cond, not_cmp_fold, opt_brcond_by_inverting_cond,
unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc, unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc,
unmerge_zext_to_zext, trunc_ext_fold, trunc_shl, unmerge_zext_to_zext, trunc_ext_fold, trunc_shl,
const_combines, xor_of_and_with_same_reg, ptr_add_with_zero, const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
shift_immed_chain, shift_of_shifted_logic_chain]>; shift_immed_chain, shift_of_shifted_logic_chain, icmp_combines]>;

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 2,547 Lines • ▼ Show 20 Linesbool CombinerHelper::replaceSingleDefInstWithReg(MachineInstr &MI,
assert(MI.getNumExplicitDefs() == 1 && "Expected one explicit def?"); assert(MI.getNumExplicitDefs() == 1 && "Expected one explicit def?");
Register OldReg = MI.getOperand(0).getReg(); Register OldReg = MI.getOperand(0).getReg();
assert(canReplaceReg(OldReg, Replacement, MRI) && "Cannot replace register?"); assert(canReplaceReg(OldReg, Replacement, MRI) && "Cannot replace register?");
MI.eraseFromParent(); MI.eraseFromParent();
replaceRegWith(MRI, OldReg, Replacement); replaceRegWith(MRI, OldReg, Replacement);
return true; return true;
} }
bool CombinerHelper::applyMIRBuilderFn(
MachineInstr &MI, MIRBuilderFn &MatchInfo) {
Builder.setInstrAndDebugLoc(MI);
return MatchInfo(Builder, MI);
}
bool CombinerHelper::matchSelectSameVal(MachineInstr &MI) { bool CombinerHelper::matchSelectSameVal(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_SELECT); assert(MI.getOpcode() == TargetOpcode::G_SELECT);
// Match (cond ? x : x) // Match (cond ? x : x)
return matchEqualDefs(MI.getOperand(2), MI.getOperand(3)) && return matchEqualDefs(MI.getOperand(2), MI.getOperand(3)) &&
canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(2).getReg(), canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(2).getReg(),
MRI); MRI);
} }
▲ Show 20 Lines • Show All 560 Lines • ▼ Show 20 Lines
bool CombinerHelper::applyPtrAddZero(MachineInstr &MI) { bool CombinerHelper::applyPtrAddZero(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_PTR_ADD); assert(MI.getOpcode() == TargetOpcode::G_PTR_ADD);
Builder.setInstrAndDebugLoc(MI); Builder.setInstrAndDebugLoc(MI);
Builder.buildIntToPtr(MI.getOperand(0), MI.getOperand(2)); Builder.buildIntToPtr(MI.getOperand(0), MI.getOperand(2));
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
bool CombinerHelper::matchExtICmp(MachineInstr &MI, MIRBuilderFn &MatchInfo) {
// Fold the following:
// icmp ne ([sz]ext (icmp cc, x, y)), 0) -> icmp cc, x, y
// icmp eq, ([sz]ext (icmp cc x, y)), 0) -> icmp inv(cc), x, y
// icmp ne, (zext (icmp cc, x, y)), 1) -> icmp inv(cc), x, y
// icmp eq, (zext (icmp cc, x, y)), 1) -> icmp cc, x, y
// icmp ne, (sext (icmp cc, x, y)), -1) -> icmp inv(cc), x, y
// icmp eq, (sext (icmp cc, x, y)), -1) -> icmp cc, x, y
assert(MI.getOpcode() == TargetOpcode::G_ICMP);
// Only do this pre-legalization.
if (LI)
return false;
aemersonUnsubmitted
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I'm not convinced this is necessary. If legality is something that a target should care about then I think they shouldn't add this combine post-legalization.

aemerson: I'm not convinced this is necessary. If legality is something that a target should care about…
LLT s1 = LLT::scalar(1);
if (MRI.getType(MI.getOperand(0).getReg()) != s1)
return false;
auto Pred = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
if (!ICmpInst::isEquality(Pred))
return false;
// Need a constant on the RHS. Don't check the value yet; we need to know the
// type of extend.
Register CstReg = MI.getOperand(3).getReg();
int64_t Cst;
if (!mi_match(CstReg, MRI, m_ICst(Cst)))
return false;
// We want to guarantee that we'll at least eliminate the extend.
Register ExtReg = MI.getOperand(2).getReg();
if (!MRI.hasOneNonDBGUse(ExtReg))
return false;
// We're going to look for a second compare which feeds into the extend.
Register TopCmp;
aemersonUnsubmitted
Not Done
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SrcCmp is a better name?

aemerson: SrcCmp is a better name?
bool IsSignExtended = mi_match(ExtReg, MRI, m_GSExt(m_Reg(TopCmp)));
if (!IsSignExtended && !mi_match(ExtReg, MRI, m_GZExt(m_Reg(TopCmp))))
return false;
if (MRI.getType(TopCmp) != s1)
return false;
const auto &TLI = getTargetLowering();
bool IsConstFalse = isConstFalseVal(TLI, Cst, /*IsVector = */ false,
/*IsFP = */ false);
if (!IsConstFalse &&
!isExtendedTrueVal(TLI, Cst, /*ExtTy = */ MRI.getType(CstReg),
/* OrigTy = */ s1,
/* IsFP = */ false, IsSignExtended))
return false;
// Match: icmp cc, x, y
Register TopCmpLHS, TopCmpRHS;
aemersonUnsubmitted
Not Done
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Same here.

aemerson: Same here.
CmpInst::Predicate TopCmpPred;
if (!mi_match(
TopCmp, MRI,
m_GICmp(m_Pred(TopCmpPred), m_Reg(TopCmpLHS), m_Reg(TopCmpRHS))))
return false;
MatchInfo = [=](MachineIRBuilder &MIB, MachineInstr &MI) {
// icmp ne ([sz]ext (icmp cc, x, y)), 0) -> icmp cc, x, y
// icmp eq, (zext (icmp cc, x, y)), 1) -> icmp cc, x, y
// icmp eq, (sext (icmp cc, x, y)), -1) -> icmp cc, x, y
if ((IsConstFalse && Pred == CmpInst::Predicate::ICMP_NE) ||
(!IsConstFalse && Pred == CmpInst::Predicate::ICMP_EQ))
return replaceSingleDefInstWithReg(MI, TopCmp);
// icmp eq, ([sz]ext (icmp cc x, y)), 0) -> icmp inv(cc), x, y
// icmp ne, (zext (icmp cc, x, y)), 1) -> icmp inv(cc), x, y
// icmp ne, (sext (icmp cc, x, y)), -1) -> icmp inv(cc), x, y
Register InvTopCmp = MRI.cloneVirtualRegister(TopCmp);
MIB.buildICmp(CmpInst::getInversePredicate(TopCmpPred), InvTopCmp,
TopCmpLHS, TopCmpRHS);
return replaceSingleDefInstWithReg(MI, InvTopCmp);
};
return true;
}
bool CombinerHelper::tryCombine(MachineInstr &MI) { bool CombinerHelper::tryCombine(MachineInstr &MI) {
if (tryCombineCopy(MI)) if (tryCombineCopy(MI))
return true; return true;
if (tryCombineExtendingLoads(MI)) if (tryCombineExtendingLoads(MI))
return true; return true;
if (tryCombineIndexedLoadStore(MI)) if (tryCombineIndexedLoadStore(MI))
return true; return true;
return false; return false;
} }

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ext-icmp.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: ne_zext_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; icmp ne (zext (icmp cc, x, y)), 0) -> icmp cc, x, y
;
; CHECK-LABEL: name: ne_zext_0
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: %top_cmp:_(s1) = G_ICMP intpred(slt), %reg0(s32), %reg1
; CHECK: %ext_cmp:_(s32) = G_ANYEXT %top_cmp(s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 0
%cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: ne_sext_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; icmp ne (sext (icmp cc, x, y)), 0) -> icmp cc, x, y
;
; CHECK-LABEL: name: ne_sext_0
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: %top_cmp:_(s1) = G_ICMP intpred(slt), %reg0(s32), %reg1
; CHECK: %ext_cmp:_(s32) = G_ANYEXT %top_cmp(s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_SEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 0
%cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: eq_zext_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; icmp eq, (zext (icmp cc, x, y)), 1) -> icmp cc, x, y
;
; CHECK-LABEL: name: eq_zext_1
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: %top_cmp:_(s1) = G_ICMP intpred(slt), %reg0(s32), %reg1
; CHECK: %ext_cmp:_(s32) = G_ANYEXT %top_cmp(s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 1
%cmp:_(s1) = G_ICMP intpred(eq), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: eq_sext_negative_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; icmp eq, (sext (icmp cc, x, y)), -1) -> icmp cc, x, y
;
; CHECK-LABEL: name: eq_sext_negative_1
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: %top_cmp:_(s1) = G_ICMP intpred(slt), %reg0(s32), %reg1
; CHECK: %ext_cmp:_(s32) = G_ANYEXT %top_cmp(s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_SEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 -1
%cmp:_(s1) = G_ICMP intpred(eq), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: eq_zext_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; icmp eq, (zext (icmp cc x, y)), 0) -> icmp inv(cc), x, y
;
; CHECK-LABEL: name: eq_zext_0
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), %reg0(s32), %reg1
; CHECK: %ext_cmp:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 0
%cmp:_(s1) = G_ICMP intpred(eq), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: eq_sext_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; icmp eq, (sext (icmp cc x, y)), 0) -> icmp inv(cc), x, y
;
; CHECK-LABEL: name: eq_sext_0
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), %reg0(s32), %reg1
; CHECK: %ext_cmp:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_SEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 0
%cmp:_(s1) = G_ICMP intpred(eq), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: ne_zext_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; icmp ne, (zext (icmp cc, x, y)), 1) -> icmp inv(cc), x, y
;
; CHECK-LABEL: name: ne_zext_1
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), %reg0(s32), %reg1
; CHECK: %ext_cmp:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 1
%cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: ne_sext_negative_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; icmp ne, (sext (icmp cc, x, y)), -1) -> icmp inv(cc), x, y
;
; CHECK-LABEL: name: ne_sext_negative_1
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), %reg0(s32), %reg1
; CHECK: %ext_cmp:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_SEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 -1
%cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: bad_pred
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; Need ne or eq for the root cmp. Don't combine.
;
; CHECK-LABEL: name: bad_pred
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: %top_cmp:_(s1) = G_ICMP intpred(slt), %reg0(s32), %reg1
; CHECK: %ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
; CHECK: %cst:_(s32) = G_CONSTANT i32 0
; CHECK: %cmp:_(s1) = G_ICMP intpred(sge), %ext_top_cmp(s32), %cst
; CHECK: %ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 0
%cmp:_(s1) = G_ICMP intpred(sge), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: bad_cst_zext
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; With G_ZEXT, we need 1 or 0. Don't combine.
;
; CHECK-LABEL: name: bad_cst_zext
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: %top_cmp:_(s1) = G_ICMP intpred(slt), %reg0(s32), %reg1
; CHECK: %ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
; CHECK: %cst:_(s32) = G_CONSTANT i32 -1
; CHECK: %cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
; CHECK: %ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 -1
%cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: bad_cst_sext
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; With G_SEXT, we need -1 or 0. Don't combine.
;
; CHECK-LABEL: name: bad_cst_sext
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: %top_cmp:_(s1) = G_ICMP intpred(slt), %reg0(s32), %reg1
; CHECK: %ext_top_cmp:_(s32) = G_SEXT %top_cmp(s1)
; CHECK: %cst:_(s32) = G_CONSTANT i32 1
; CHECK: %cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
; CHECK: %ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
; CHECK: $w0 = COPY %ext_cmp(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_SEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 1
%cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
$w0 = COPY %ext_cmp(s32)
RET_ReallyLR implicit $w0
...
---
name: ext_more_than_one_use
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; When the extend has more than one use, don't combine.
;
; CHECK-LABEL: name: ext_more_than_one_use
; CHECK: liveins: $w0, $w1
; CHECK: %reg0:_(s32) = COPY $w0
; CHECK: %reg1:_(s32) = COPY $w1
; CHECK: %top_cmp:_(s1) = G_ICMP intpred(slt), %reg0(s32), %reg1
; CHECK: %ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
; CHECK: %cst:_(s32) = G_CONSTANT i32 0
; CHECK: %cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
; CHECK: %ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
; CHECK: %and:_(s32) = G_AND %ext_cmp, %ext_top_cmp
; CHECK: $w0 = COPY %and(s32)
; CHECK: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%top_cmp:_(s1) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(s32) = G_ZEXT %top_cmp(s1)
%cst:_(s32) = G_CONSTANT i32 0
%cmp:_(s1) = G_ICMP intpred(ne), %ext_top_cmp(s32), %cst
%ext_cmp:_(s32) = G_ANYEXT %cmp(s1)
%and:_(s32) = G_AND %ext_cmp(s32), %ext_top_cmp(s32)
$w0 = COPY %and(s32)
RET_ReallyLR implicit $w0
...
---
name: vector
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; Don't handle vectors.
;
; CHECK-LABEL: name: vector
; CHECK: liveins: $d0, $d1
; CHECK: %reg0:_(<2 x s32>) = COPY $d0
; CHECK: %reg1:_(<2 x s32>) = COPY $d0
; CHECK: %top_cmp:_(<2 x s1>) = G_ICMP intpred(slt), %reg0(<2 x s32>), %reg1
; CHECK: %ext_top_cmp:_(<2 x s32>) = G_ZEXT %top_cmp(<2 x s1>)
; CHECK: %cst:_(s32) = G_CONSTANT i32 0
; CHECK: %cst_vec:_(<2 x s32>) = G_BUILD_VECTOR %cst(s32), %cst(s32)
; CHECK: %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %ext_top_cmp(<2 x s32>), %cst_vec
; CHECK: %ext_cmp:_(<2 x s32>) = G_ANYEXT %cmp(<2 x s1>)
; CHECK: $d0 = COPY %ext_cmp(<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%reg0:_(<2 x s32>) = COPY $d0
%reg1:_(<2 x s32>) = COPY $d0
%top_cmp:_(<2 x s1>) = G_ICMP intpred(slt), %reg0, %reg1
%ext_top_cmp:_(<2 x s32>) = G_ZEXT %top_cmp(<2 x s1>)
%cst:_(s32) = G_CONSTANT i32 0
%cst_vec:_(<2 x s32>) = G_BUILD_VECTOR %cst(s32), %cst
%cmp:_(<2 x s1>) = G_ICMP intpred(ne), %ext_top_cmp(<2 x s32>), %cst_vec
%ext_cmp:_(<2 x s32>) = G_ANYEXT %cmp(<2 x s1>)
$d0 = COPY %ext_cmp(<2 x s32>)
RET_ReallyLR implicit $d0