This is an archive of the discontinued LLVM Phabricator instance.

Differential D91539

[VE] Optimize leaf functions
ClosedPublic

Authored by kaz7 on Nov 16 2020, 6:25 AM.

Details

Reviewers
simoll
k-ishizaka
Commits
rG44a4f9392546: [VE] Optimize leaf functions
Summary

Optimize leaf functions by not generating save/restore for callee saved
registers. Update regression tests also.

Diff Detail

Unit TestsFailed

TimeTest
390 mslinux > HWAddressSanitizer-x86_64.TestCases::sizes.cpp

Event Timeline

kaz7 created this revision.Nov 16 2020, 6:25 AM
Herald added subscribers: llvm-commits, hiraditya. · View Herald TranscriptNov 16 2020, 6:25 AM
kaz7 requested review of this revision.Nov 16 2020, 6:25 AM
Harbormaster completed remote builds in B78956: Diff 305492.Nov 16 2020, 6:58 AM
simoll accepted this revision.Nov 16 2020, 7:27 AM

LGTM.
We should upstream the utils/update_llc_test_checks.py changes that were used to generate these tests.

This revision is now accepted and ready to land.Nov 16 2020, 7:27 AM
kaz7 updated this revision to Diff 305513.Nov 16 2020, 7:37 AM

Rebase to the upstream/master and update newly added regression tests,
lsv.ll and fastcc_callee.ll.

This revision was landed with ongoing or failed builds.Nov 16 2020, 7:38 AM
Closed by commit rG44a4f9392546: [VE] Optimize leaf functions (authored by kaz7). · Explain Why
This revision was automatically updated to reflect the committed changes.
kaz7 added a commit: rG44a4f9392546: [VE] Optimize leaf functions.
Harbormaster completed remote builds in B78962: Diff 305513.Nov 16 2020, 8:46 AM

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
3 lines
34 lines
test/
CodeGen/
VE/
Scalar/
88 lines
64 lines
24 lines
144 lines
144 lines
16 lines
64 lines
4 lines
168 lines
37 lines
8 lines
11 lines
48 lines
8 lines
644 lines
168 lines
96 lines
64 lines
64 lines
64 lines
32 lines
24 lines
16 lines
48 lines
24 lines
28 lines
8 lines
52 lines
44 lines
64 lines
16 lines
16 lines
132 lines
20 lines
12 lines
64 lines
64 lines
24 lines
24 lines
24 lines
24 lines
56 lines
32 lines
52 lines
4 lines
68 lines
68 lines
76 lines
80 lines
64 lines
64 lines
64 lines
8 lines
8 lines
168 lines
784 lines
64 lines
28 lines
64 lines
64 lines
28 lines
64 lines
56 lines
28 lines
56 lines
56 lines
28 lines
56 lines
56 lines
64 lines
64 lines
64 lines
64 lines
40 lines
40 lines
40 lines
40 lines
104 lines
104 lines
24 lines
24 lines
24 lines
24 lines
44 lines
32 lines
88 lines
8 lines
20 lines
28 lines
68 lines
VELIntrinsics/
8 lines
16 lines
256 lines
384 lines

Diff 305492

llvm/lib/Target/VE/VEFrameLowering.h

Show All 33 Linespublic:
void emitEpilogueInsns(MachineFunction &MF, MachineBasicBlock &MBB, void emitEpilogueInsns(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, uint64_t NumBytes, MachineBasicBlock::iterator MBBI, uint64_t NumBytes,
bool RequireFPUpdate) const; bool RequireFPUpdate) const;
MachineBasicBlock::iterator MachineBasicBlock::iterator
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const override; MachineBasicBlock::iterator I) const override;
bool hasBP(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const override; bool hasFP(const MachineFunction &MF) const override;
bool hasBP(const MachineFunction &MF) const;
// VE reserves argument space always for call sites in the function // VE reserves argument space always for call sites in the function
// immediately on entry of the current function. // immediately on entry of the current function.
bool hasReservedCallFrame(const MachineFunction &MF) const override { bool hasReservedCallFrame(const MachineFunction &MF) const override {
return true; return true;
} }
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
RegScavenger *RS = nullptr) const override; RegScavenger *RS = nullptr) const override;
Show All 35 Lines

llvm/lib/Target/VE/VEFrameLowering.cpp

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Linesvoid VEFrameLowering::emitSPExtend(MachineFunction &MF, MachineBasicBlock &MBB,
// pass. This pseudo is required to be at the next of EXTEND_STACK // pass. This pseudo is required to be at the next of EXTEND_STACK
// pseudo in order to protect iteration loop in ExpandPostRA. // pseudo in order to protect iteration loop in ExpandPostRA.
BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK)); BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK));
BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK_GUARD)); BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK_GUARD));
} }
void VEFrameLowering::emitPrologue(MachineFunction &MF, void VEFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
const VEInstrInfo &TII = *STI.getInstrInfo(); const VEInstrInfo &TII = *STI.getInstrInfo();
const VERegisterInfo &RegInfo = *STI.getRegisterInfo(); const VERegisterInfo &RegInfo = *STI.getRegisterInfo();
MachineBasicBlock::iterator MBBI = MBB.begin(); MachineBasicBlock::iterator MBBI = MBB.begin();
bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
// Debug location must be unknown since the first debug location is used // Debug location must be unknown since the first debug location is used
Show All 20 Linesvoid VEFrameLowering::emitPrologue(MachineFunction &MF,
// Finally, ensure that the size is sufficiently aligned for the // Finally, ensure that the size is sufficiently aligned for the
// data on the stack. // data on the stack.
NumBytes = alignTo(NumBytes, MFI.getMaxAlign()); NumBytes = alignTo(NumBytes, MFI.getMaxAlign());
// Update stack size with corrected value. // Update stack size with corrected value.
MFI.setStackSize(NumBytes); MFI.setStackSize(NumBytes);
if (FuncInfo->isLeafProc())
return;
// Emit Prologue instructions to save multiple registers. // Emit Prologue instructions to save multiple registers.
emitPrologueInsns(MF, MBB, MBBI, NumBytes, true); emitPrologueInsns(MF, MBB, MBBI, NumBytes, true);
// Emit stack adjust instructions // Emit stack adjust instructions
MaybeAlign RuntimeAlign = MaybeAlign RuntimeAlign =
NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : None; NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : None;
emitSPAdjustment(MF, MBB, MBBI, -(int64_t)NumBytes, RuntimeAlign); emitSPAdjustment(MF, MBB, MBBI, -(int64_t)NumBytes, RuntimeAlign);
Show All 33 Lines if (!hasReservedCallFrame(MF)) {
if (Size) if (Size)
emitSPAdjustment(MF, MBB, I, Size); emitSPAdjustment(MF, MBB, I, Size);
} }
return MBB.erase(I); return MBB.erase(I);
} }
void VEFrameLowering::emitEpilogue(MachineFunction &MF, void VEFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
uint64_t NumBytes = MFI.getStackSize(); uint64_t NumBytes = MFI.getStackSize();
if (FuncInfo->isLeafProc())
return;
// Emit Epilogue instructions to restore multiple registers. // Emit Epilogue instructions to restore multiple registers.
emitEpilogueInsns(MF, MBB, MBBI, NumBytes, true); emitEpilogueInsns(MF, MBB, MBBI, NumBytes, true);
} }
// hasFP - Return true if the specified function should have a dedicated frame // hasFP - Return true if the specified function should have a dedicated frame
// pointer register. This is true if the function has variable sized allocas // pointer register. This is true if the function has variable sized allocas
// or if frame pointer elimination is disabled. For the case of VE, we don't // or if frame pointer elimination is disabled.
// implement FP eliminator yet, but we returns false from this function to
// not refer fp from generated code.
bool VEFrameLowering::hasFP(const MachineFunction &MF) const { bool VEFrameLowering::hasFP(const MachineFunction &MF) const {
const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
const MachineFrameInfo &MFI = MF.getFrameInfo(); const MachineFrameInfo &MFI = MF.getFrameInfo();
return MF.getTarget().Options.DisableFramePointerElim(MF) || return MF.getTarget().Options.DisableFramePointerElim(MF) ||
RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
MFI.isFrameAddressTaken(); MFI.isFrameAddressTaken();
} }
bool VEFrameLowering::hasBP(const MachineFunction &MF) const { bool VEFrameLowering::hasBP(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo(); const MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetRegisterInfo *TRI = STI.getRegisterInfo(); const TargetRegisterInfo *TRI = STI.getRegisterInfo();
return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);
} }
StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF, StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF,
int FI, int FI,
Register &FrameReg) const { Register &FrameReg) const {
const MachineFrameInfo &MFI = MF.getFrameInfo(); const MachineFrameInfo &MFI = MF.getFrameInfo();
const VERegisterInfo *RegInfo = STI.getRegisterInfo(); const VERegisterInfo *RegInfo = STI.getRegisterInfo();
const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
bool isFixed = MFI.isFixedObjectIndex(FI); bool isFixed = MFI.isFixedObjectIndex(FI);
int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI); int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI);
if (FuncInfo->isLeafProc()) { if (!hasFP(MF)) {
// If there's a leaf proc, all offsets need to be %sp-based, // If FP is not used, frame indexies are based on a %sp regiter.
// because we haven't caused %fp to actually point to our frame.
FrameReg = VE::SX11; // %sp FrameReg = VE::SX11; // %sp
return StackOffset::getFixed(FrameOffset + return StackOffset::getFixed(FrameOffset +
MF.getFrameInfo().getStackSize()); MF.getFrameInfo().getStackSize());
} }
if (RegInfo->needsStackRealignment(MF) && !isFixed) { if (RegInfo->needsStackRealignment(MF) && !isFixed) {
// If there is dynamic stack realignment, all local object // If data on stack require realignemnt, frame indexies are based on a %sp
// references need to be via %sp or %s17 (bp), to take account // or %s17 (bp) register. If there is a variable sized object, bp is used.
// of the re-alignment.
if (hasBP(MF)) if (hasBP(MF))
FrameReg = VE::SX17; // %bp FrameReg = VE::SX17; // %bp
else else
FrameReg = VE::SX11; // %sp FrameReg = VE::SX11; // %sp
return StackOffset::getFixed(FrameOffset + return StackOffset::getFixed(FrameOffset +
MF.getFrameInfo().getStackSize()); MF.getFrameInfo().getStackSize());
} }
// Finally, default to using %fp. // Use %fp by default.
FrameReg = RegInfo->getFrameRegister(MF); FrameReg = RegInfo->getFrameRegister(MF);
return StackOffset::getFixed(FrameOffset); return StackOffset::getFixed(FrameOffset);
} }
bool VEFrameLowering::isLeafProc(MachineFunction &MF) const { bool VEFrameLowering::isLeafProc(MachineFunction &MF) const {
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
return !MFI.hasCalls() // No calls return !MFI.hasCalls() // No calls
&& !MRI.isPhysRegUsed(VE::SX18) // Registers within limits && !MRI.isPhysRegUsed(VE::SX18) // Registers within limits
// (s18 is first CSR) // (s18 is first CSR)
&& !MRI.isPhysRegUsed(VE::SX11) // %sp un-used && !MRI.isPhysRegUsed(VE::SX11) // %sp un-used
&& !hasFP(MF); // Don't need %fp && !hasFP(MF); // Don't need %fp
} }
void VEFrameLowering::determineCalleeSaves(MachineFunction &MF, void VEFrameLowering::determineCalleeSaves(MachineFunction &MF,
BitVector &SavedRegs, BitVector &SavedRegs,
RegScavenger *RS) const { RegScavenger *RS) const {
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
const MachineFrameInfo &MFI = MF.getFrameInfo();
if (isLeafProc(MF)) { // Functions having BP or stack objects need to emit prologue and epilogue
VEMachineFunctionInfo *MFI = MF.getInfo<VEMachineFunctionInfo>(); // to allocate local buffer on the stack.
MFI->setLeafProc(true); if (isLeafProc(MF) && !hasBP(MF) && !MFI.hasStackObjects()) {
VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
FuncInfo->setLeafProc(true);
} }
} }

llvm/test/CodeGen/VE/Scalar/addition.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func8s(i8 signext %0, i8 signext %1) { define signext i8 @func8s(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add i8 %1, %0 %3 = add i8 %1, %0
ret i8 %3 ret i8 %3
} }
define signext i16 @func16s(i16 signext %0, i16 signext %1) { define signext i16 @func16s(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add i16 %1, %0 %3 = add i16 %1, %0
ret i16 %3 ret i16 %3
} }
define signext i32 @func32s(i32 signext %0, i32 signext %1) { define signext i32 @func32s(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add nsw i32 %1, %0 %3 = add nsw i32 %1, %0
ret i32 %3 ret i32 %3
} }
define i64 @func64s(i64 %0, i64 %1) { define i64 @func64s(i64 %0, i64 %1) {
; CHECK-LABEL: func64s: ; CHECK-LABEL: func64s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.l %s0, %s1, %s0 ; CHECK-NEXT: adds.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add nsw i64 %1, %0 %3 = add nsw i64 %1, %0
ret i64 %3 ret i64 %3
} }
define i128 @func128s(i128 %0, i128 %1) { define i128 @func128s(i128 %0, i128 %1) {
; CHECK-LABEL: func128s: ; CHECK-LABEL: func128s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.l %s1, %s3, %s1 ; CHECK-NEXT: adds.l %s1, %s3, %s1
; CHECK-NEXT: adds.l %s0, %s2, %s0 ; CHECK-NEXT: adds.l %s0, %s2, %s0
; CHECK-NEXT: cmpu.l %s2, %s0, %s2 ; CHECK-NEXT: cmpu.l %s2, %s0, %s2
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2 ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2
; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s2 ; CHECK-NEXT: adds.l %s1, %s1, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add nsw i128 %1, %0 %3 = add nsw i128 %1, %0
ret i128 %3 ret i128 %3
} }
define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) { define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add i8 %1, %0 %3 = add i8 %1, %0
ret i8 %3 ret i8 %3
} }
define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) { define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add i16 %1, %0 %3 = add i16 %1, %0
ret i16 %3 ret i16 %3
} }
define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) { define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add i32 %1, %0 %3 = add i32 %1, %0
ret i32 %3 ret i32 %3
} }
define i64 @func64z(i64 %0, i64 %1) { define i64 @func64z(i64 %0, i64 %1) {
; CHECK-LABEL: func64z: ; CHECK-LABEL: func64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.l %s0, %s1, %s0 ; CHECK-NEXT: adds.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add i64 %1, %0 %3 = add i64 %1, %0
ret i64 %3 ret i64 %3
} }
define i128 @func128z(i128 %0, i128 %1) { define i128 @func128z(i128 %0, i128 %1) {
; CHECK-LABEL: func128z: ; CHECK-LABEL: func128z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.l %s1, %s3, %s1 ; CHECK-NEXT: adds.l %s1, %s3, %s1
; CHECK-NEXT: adds.l %s0, %s2, %s0 ; CHECK-NEXT: adds.l %s0, %s2, %s0
; CHECK-NEXT: cmpu.l %s2, %s0, %s2 ; CHECK-NEXT: cmpu.l %s2, %s0, %s2
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2 ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2
; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s2 ; CHECK-NEXT: adds.l %s1, %s1, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = add i128 %1, %0 %3 = add i128 %1, %0
ret i128 %3 ret i128 %3
} }
define signext i8 @funci8s(i8 signext %0) { define signext i8 @funci8s(i8 signext %0) {
; CHECK-LABEL: funci8s: ; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add i8 %0, 5 %2 = add i8 %0, 5
ret i8 %2 ret i8 %2
} }
define signext i16 @funci16s(i16 signext %0) { define signext i16 @funci16s(i16 signext %0) {
; CHECK-LABEL: funci16s: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add i16 %0, 5 %2 = add i16 %0, 5
ret i16 %2 ret i16 %2
} }
define signext i32 @funci32s(i32 signext %0) { define signext i32 @funci32s(i32 signext %0) {
; CHECK-LABEL: funci32s: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i32 %0, 5 %2 = add nsw i32 %0, 5
ret i32 %2 ret i32 %2
} }
define i64 @funci64s(i64 %0) { define i64 @funci64s(i64 %0) {
; CHECK-LABEL: funci64s: ; CHECK-LABEL: funci64s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 5(, %s0) ; CHECK-NEXT: lea %s0, 5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i64 %0, 5 %2 = add nsw i64 %0, 5
ret i64 %2 ret i64 %2
} }
define i128 @funci128s(i128 %0) { define i128 @funci128s(i128 %0) {
; CHECK-LABEL: funci128s: ; CHECK-LABEL: funci128s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 5(, %s0) ; CHECK-NEXT: lea %s2, 5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s0 ; CHECK-NEXT: adds.l %s1, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i128 %0, 5 %2 = add nsw i128 %0, 5
ret i128 %2 ret i128 %2
} }
define zeroext i8 @funci8z(i8 zeroext %0) { define zeroext i8 @funci8z(i8 zeroext %0) {
; CHECK-LABEL: funci8z: ; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add i8 %0, 5 %2 = add i8 %0, 5
ret i8 %2 ret i8 %2
} }
define zeroext i16 @funci16z(i16 zeroext %0) { define zeroext i16 @funci16z(i16 zeroext %0) {
; CHECK-LABEL: funci16z: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add i16 %0, 5 %2 = add i16 %0, 5
ret i16 %2 ret i16 %2
} }
define zeroext i32 @funci32z(i32 zeroext %0) { define zeroext i32 @funci32z(i32 zeroext %0) {
; CHECK-LABEL: funci32z: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0 ; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add i32 %0, 5 %2 = add i32 %0, 5
ret i32 %2 ret i32 %2
} }
define i64 @funci64z(i64 %0) { define i64 @funci64z(i64 %0) {
; CHECK-LABEL: funci64z: ; CHECK-LABEL: funci64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 5(, %s0) ; CHECK-NEXT: lea %s0, 5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add i64 %0, 5 %2 = add i64 %0, 5
ret i64 %2 ret i64 %2
} }
define i128 @funci128z(i128 %0) { define i128 @funci128z(i128 %0) {
; CHECK-LABEL: funci128z: ; CHECK-LABEL: funci128z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 5(, %s0) ; CHECK-NEXT: lea %s2, 5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s0 ; CHECK-NEXT: adds.l %s1, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add i128 %0, 5 %2 = add i128 %0, 5
ret i128 %2 ret i128 %2
} }
define i64 @funci64_2(i64 %0) { define i64 @funci64_2(i64 %0) {
; CHECK-LABEL: funci64_2: ; CHECK-LABEL: funci64_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: adds.l %s0, %s0, %s1 ; CHECK-NEXT: adds.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i64 %0, 2147483648 %2 = add nsw i64 %0, 2147483648
ret i64 %2 ret i64 %2
} }
define i128 @funci128_2(i128 %0) { define i128 @funci128_2(i128 %0) {
; CHECK-LABEL: funci128_2: ; CHECK-LABEL: funci128_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, -2147483648 ; CHECK-NEXT: lea %s2, -2147483648
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: adds.l %s2, %s0, %s2 ; CHECK-NEXT: adds.l %s2, %s0, %s2
; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s0 ; CHECK-NEXT: adds.l %s1, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i128 %0, 2147483648 %2 = add nsw i128 %0, 2147483648
ret i128 %2 ret i128 %2
} }

llvm/test/CodeGen/VE/Scalar/and.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func8s(i8 signext %a, i8 signext %b) { define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i8 %a, %b %res = and i8 %a, %b
ret i8 %res ret i8 %res
} }
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s1, %s0 ; CHECK-NEXT: and %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i8 %b, %a %res = and i8 %b, %a
ret i8 %res ret i8 %res
} }
define signext i8 @funci8s(i8 signext %a) { define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s: ; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, 5, %s0 ; CHECK-NEXT: and %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i8 %a, 5 %res = and i8 %a, 5
ret i8 %res ret i8 %res
} }
define zeroext i8 @funci8z(i8 zeroext %a) { define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z: ; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 251 ; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i8 -5, %a %res = and i8 -5, %a
ret i8 %res ret i8 %res
} }
define signext i16 @func16s(i16 signext %a, i16 signext %b) { define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i16 %a, %b %res = and i16 %a, %b
ret i16 %res ret i16 %res
} }
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s1, %s0 ; CHECK-NEXT: and %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i16 %b, %a %res = and i16 %b, %a
ret i16 %res ret i16 %res
} }
define signext i16 @funci16s(i16 signext %a) { define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i16 %a, 65535 %res = and i16 %a, 65535
ret i16 %res ret i16 %res
} }
define zeroext i16 @funci16z(i16 zeroext %a) { define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (52)0 ; CHECK-NEXT: and %s0, %s0, (52)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i16 4095, %a %res = and i16 4095, %a
ret i16 %res ret i16 %res
} }
define signext i32 @func32s(i32 signext %a, i32 signext %b) { define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i32 %a, %b %res = and i32 %a, %b
ret i32 %res ret i32 %res
} }
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i32 %a, %b %res = and i32 %a, %b
ret i32 %res ret i32 %res
} }
define signext i32 @funci32s(i32 signext %a) { define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (36)0 ; CHECK-NEXT: and %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i32 %a, 268435455 %res = and i32 %a, 268435455
ret i32 %res ret i32 %res
} }
define zeroext i32 @funci32z(i32 zeroext %a) { define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (36)0 ; CHECK-NEXT: and %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i32 %a, 268435455 %res = and i32 %a, 268435455
ret i32 %res ret i32 %res
} }
define i64 @func64(i64 %a, i64 %b) { define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i64 %a, %b %res = and i64 %a, %b
ret i64 %res ret i64 %res
} }
define i64 @func64i(i64 %a) { define i64 @func64i(i64 %a) {
; CHECK-LABEL: func64i: ; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (24)0 ; CHECK-NEXT: and %s0, %s0, (24)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i64 %a, 1099511627775 %res = and i64 %a, 1099511627775
ret i64 %res ret i64 %res
} }
define i128 @func128(i128 %a, i128 %b) { define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s2, %s0 ; CHECK-NEXT: and %s0, %s2, %s0
; CHECK-NEXT: and %s1, %s3, %s1 ; CHECK-NEXT: and %s1, %s3, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i128 %b, %a %res = and i128 %b, %a
ret i128 %res ret i128 %res
} }
define i128 @funci128(i128 %a) { define i128 @funci128(i128 %a) {
; CHECK-LABEL: funci128: ; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, 5, %s0 ; CHECK-NEXT: and %s0, 5, %s0
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = and i128 %a, 5 %res = and i128 %a, 5
ret i128 %res ret i128 %res
} }

llvm/test/CodeGen/VE/Scalar/atomic_fence.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
;;; Test atomic fence for all memory order ;;; Test atomic fence for all memory order
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define void @_Z20atomic_fence_relaxedv() { define void @_Z20atomic_fence_relaxedv() {
; CHECK-LABEL: _Z20atomic_fence_relaxedv: ; CHECK-LABEL: _Z20atomic_fence_relaxedv:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_consumev() { define void @_Z20atomic_fence_consumev() {
; CHECK-LABEL: _Z20atomic_fence_consumev: ; CHECK-LABEL: _Z20atomic_fence_consumev:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
fence acquire fence acquire
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_acquirev() { define void @_Z20atomic_fence_acquirev() {
; CHECK-LABEL: _Z20atomic_fence_acquirev: ; CHECK-LABEL: _Z20atomic_fence_acquirev:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
fence acquire fence acquire
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_releasev() { define void @_Z20atomic_fence_releasev() {
; CHECK-LABEL: _Z20atomic_fence_releasev: ; CHECK-LABEL: _Z20atomic_fence_releasev:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
fence release fence release
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_acq_relv() { define void @_Z20atomic_fence_acq_relv() {
; CHECK-LABEL: _Z20atomic_fence_acq_relv: ; CHECK-LABEL: _Z20atomic_fence_acq_relv:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
fence acq_rel fence acq_rel
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_seq_cstv() { define void @_Z20atomic_fence_seq_cstv() {
; CHECK-LABEL: _Z20atomic_fence_seq_cstv: ; CHECK-LABEL: _Z20atomic_fence_seq_cstv:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
fence seq_cst fence seq_cst
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/atomic_load.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
%"struct.std::__1::__atomic_base.46" = type { %"struct.std::__1::__atomic_base.47" } %"struct.std::__1::__atomic_base.46" = type { %"struct.std::__1::__atomic_base.47" }
%"struct.std::__1::__atomic_base.47" = type { %"struct.std::__1::__cxx_atomic_impl.48" } %"struct.std::__1::__atomic_base.47" = type { %"struct.std::__1::__cxx_atomic_impl.48" }
%"struct.std::__1::__cxx_atomic_impl.48" = type { %"struct.std::__1::__cxx_atomic_base_impl.49" } %"struct.std::__1::__cxx_atomic_impl.48" = type { %"struct.std::__1::__cxx_atomic_base_impl.49" }
%"struct.std::__1::__cxx_atomic_base_impl.49" = type { i128 } %"struct.std::__1::__cxx_atomic_base_impl.49" = type { i128 }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i1 @_Z22atomic_load_relaxed_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { define zeroext i1 @_Z22atomic_load_relaxed_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_relaxed_i1RNSt3__16atomicIbEE: ; CHECK-LABEL: _Z22atomic_load_relaxed_i1RNSt3__16atomicIbEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: and %s0, 1, %s0 ; CHECK-NEXT: and %s0, 1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 monotonic, align 1 %3 = load atomic i8, i8* %2 monotonic, align 1
%4 = and i8 %3, 1 %4 = and i8 %3, 1
%5 = icmp ne i8 %4, 0 %5 = icmp ne i8 %4, 0
ret i1 %5 ret i1 %5
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define signext i8 @_Z22atomic_load_relaxed_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { define signext i8 @_Z22atomic_load_relaxed_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_relaxed_i8RNSt3__16atomicIcEE: ; CHECK-LABEL: _Z22atomic_load_relaxed_i8RNSt3__16atomicIcEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.sx %s0, (, %s0) ; CHECK-NEXT: ld1b.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 monotonic, align 1 %3 = load atomic i8, i8* %2 monotonic, align 1
ret i8 %3 ret i8 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i8 @_Z22atomic_load_relaxed_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { define zeroext i8 @_Z22atomic_load_relaxed_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_relaxed_u8RNSt3__16atomicIhEE: ; CHECK-LABEL: _Z22atomic_load_relaxed_u8RNSt3__16atomicIhEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 monotonic, align 1 %3 = load atomic i8, i8* %2 monotonic, align 1
ret i8 %3 ret i8 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define signext i16 @_Z23atomic_load_relaxed_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { define signext i16 @_Z23atomic_load_relaxed_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_i16RNSt3__16atomicIsEE: ; CHECK-LABEL: _Z23atomic_load_relaxed_i16RNSt3__16atomicIsEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.sx %s0, (, %s0) ; CHECK-NEXT: ld2b.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 monotonic, align 2 %3 = load atomic i16, i16* %2 monotonic, align 2
ret i16 %3 ret i16 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i16 @_Z23atomic_load_relaxed_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { define zeroext i16 @_Z23atomic_load_relaxed_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_u16RNSt3__16atomicItEE: ; CHECK-LABEL: _Z23atomic_load_relaxed_u16RNSt3__16atomicItEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 monotonic, align 2 %3 = load atomic i16, i16* %2 monotonic, align 2
ret i16 %3 ret i16 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define signext i32 @_Z23atomic_load_relaxed_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { define signext i32 @_Z23atomic_load_relaxed_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_i32RNSt3__16atomicIiEE: ; CHECK-LABEL: _Z23atomic_load_relaxed_i32RNSt3__16atomicIiEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 monotonic, align 4 %3 = load atomic i32, i32* %2 monotonic, align 4
ret i32 %3 ret i32 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i32 @_Z23atomic_load_relaxed_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { define zeroext i32 @_Z23atomic_load_relaxed_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_u32RNSt3__16atomicIjEE: ; CHECK-LABEL: _Z23atomic_load_relaxed_u32RNSt3__16atomicIjEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldl.zx %s0, (, %s0) ; CHECK-NEXT: ldl.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 monotonic, align 4 %3 = load atomic i32, i32* %2 monotonic, align 4
ret i32 %3 ret i32 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_relaxed_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { define i64 @_Z23atomic_load_relaxed_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_i64RNSt3__16atomicIlEE: ; CHECK-LABEL: _Z23atomic_load_relaxed_i64RNSt3__16atomicIlEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 monotonic, align 8 %3 = load atomic i64, i64* %2 monotonic, align 8
ret i64 %3 ret i64 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_relaxed_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { define i64 @_Z23atomic_load_relaxed_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_u64RNSt3__16atomicImEE: ; CHECK-LABEL: _Z23atomic_load_relaxed_u64RNSt3__16atomicImEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 monotonic, align 8 %3 = load atomic i64, i64* %2 monotonic, align 8
ret i64 %3 ret i64 %3
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define i128 @_Z24atomic_load_relaxed_i128RNSt3__16atomicInEE(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0) { define i128 @_Z24atomic_load_relaxed_i128RNSt3__16atomicInEE(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0) {
; CHECK-LABEL: _Z24atomic_load_relaxed_i128RNSt3__16atomicInEE: ; CHECK-LABEL: _Z24atomic_load_relaxed_i128RNSt3__16atomicInEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 0, %s0 ; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9) ; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, -16(, %s9) ; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16 %2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8* %3 = bitcast i128* %2 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)
%4 = bitcast %"struct.std::__1::atomic.40"* %0 to i8* %4 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 0) call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 0)
%5 = load i128, i128* %2, align 16, !tbaa !2 %5 = load i128, i128* %2, align 16, !tbaa !2
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3)
ret i128 %5 ret i128 %5
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define i128 @_Z24atomic_load_relaxed_u128RNSt3__16atomicIoEE(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0) { define i128 @_Z24atomic_load_relaxed_u128RNSt3__16atomicIoEE(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0) {
; CHECK-LABEL: _Z24atomic_load_relaxed_u128RNSt3__16atomicIoEE: ; CHECK-LABEL: _Z24atomic_load_relaxed_u128RNSt3__16atomicIoEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 0, %s0 ; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9) ; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, -16(, %s9) ; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16 %2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8* %3 = bitcast i128* %2 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)
%4 = bitcast %"struct.std::__1::atomic.45"* %0 to i8* %4 = bitcast %"struct.std::__1::atomic.45"* %0 to i8*
call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 0) call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 0)
%5 = load i128, i128* %2, align 16, !tbaa !2 %5 = load i128, i128* %2, align 16, !tbaa !2
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3)
ret i128 %5 ret i128 %5
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i1 @_Z22atomic_load_acquire_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { define zeroext i1 @_Z22atomic_load_acquire_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_acquire_i1RNSt3__16atomicIbEE: ; CHECK-LABEL: _Z22atomic_load_acquire_i1RNSt3__16atomicIbEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: and %s0, 1, %s0 ; CHECK-NEXT: and %s0, 1, %s0
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 acquire, align 1 %3 = load atomic i8, i8* %2 acquire, align 1
%4 = and i8 %3, 1 %4 = and i8 %3, 1
%5 = icmp ne i8 %4, 0 %5 = icmp ne i8 %4, 0
ret i1 %5 ret i1 %5
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define signext i8 @_Z22atomic_load_acquire_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { define signext i8 @_Z22atomic_load_acquire_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_acquire_i8RNSt3__16atomicIcEE: ; CHECK-LABEL: _Z22atomic_load_acquire_i8RNSt3__16atomicIcEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.sx %s0, (, %s0) ; CHECK-NEXT: ld1b.sx %s0, (, %s0)
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 acquire, align 1 %3 = load atomic i8, i8* %2 acquire, align 1
ret i8 %3 ret i8 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i8 @_Z22atomic_load_acquire_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { define zeroext i8 @_Z22atomic_load_acquire_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_acquire_u8RNSt3__16atomicIhEE: ; CHECK-LABEL: _Z22atomic_load_acquire_u8RNSt3__16atomicIhEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 acquire, align 1 %3 = load atomic i8, i8* %2 acquire, align 1
ret i8 %3 ret i8 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define signext i16 @_Z23atomic_load_acquire_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { define signext i16 @_Z23atomic_load_acquire_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_i16RNSt3__16atomicIsEE: ; CHECK-LABEL: _Z23atomic_load_acquire_i16RNSt3__16atomicIsEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.sx %s0, (, %s0) ; CHECK-NEXT: ld2b.sx %s0, (, %s0)
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 acquire, align 2 %3 = load atomic i16, i16* %2 acquire, align 2
ret i16 %3 ret i16 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i16 @_Z23atomic_load_acquire_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { define zeroext i16 @_Z23atomic_load_acquire_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_u16RNSt3__16atomicItEE: ; CHECK-LABEL: _Z23atomic_load_acquire_u16RNSt3__16atomicItEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 acquire, align 2 %3 = load atomic i16, i16* %2 acquire, align 2
ret i16 %3 ret i16 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define signext i32 @_Z23atomic_load_acquire_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { define signext i32 @_Z23atomic_load_acquire_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_i32RNSt3__16atomicIiEE: ; CHECK-LABEL: _Z23atomic_load_acquire_i32RNSt3__16atomicIiEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 acquire, align 4 %3 = load atomic i32, i32* %2 acquire, align 4
ret i32 %3 ret i32 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i32 @_Z23atomic_load_acquire_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { define zeroext i32 @_Z23atomic_load_acquire_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_u32RNSt3__16atomicIjEE: ; CHECK-LABEL: _Z23atomic_load_acquire_u32RNSt3__16atomicIjEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldl.zx %s0, (, %s0) ; CHECK-NEXT: ldl.zx %s0, (, %s0)
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 acquire, align 4 %3 = load atomic i32, i32* %2 acquire, align 4
ret i32 %3 ret i32 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_acquire_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { define i64 @_Z23atomic_load_acquire_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_i64RNSt3__16atomicIlEE: ; CHECK-LABEL: _Z23atomic_load_acquire_i64RNSt3__16atomicIlEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 acquire, align 8 %3 = load atomic i64, i64* %2 acquire, align 8
ret i64 %3 ret i64 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_acquire_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { define i64 @_Z23atomic_load_acquire_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_u64RNSt3__16atomicImEE: ; CHECK-LABEL: _Z23atomic_load_acquire_u64RNSt3__16atomicImEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: fencem 2 ; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 acquire, align 8 %3 = load atomic i64, i64* %2 acquire, align 8
ret i64 %3 ret i64 %3
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define i128 @_Z24atomic_load_acquire_i128RNSt3__16atomicInEE(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0) { define i128 @_Z24atomic_load_acquire_i128RNSt3__16atomicInEE(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0) {
; CHECK-LABEL: _Z24atomic_load_acquire_i128RNSt3__16atomicInEE: ; CHECK-LABEL: _Z24atomic_load_acquire_i128RNSt3__16atomicInEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 0, %s0 ; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 2, (0)1 ; CHECK-NEXT: or %s3, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9) ; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, -16(, %s9) ; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16 %2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8* %3 = bitcast i128* %2 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)
%4 = bitcast %"struct.std::__1::atomic.40"* %0 to i8* %4 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 2) call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 2)
%5 = load i128, i128* %2, align 16, !tbaa !2 %5 = load i128, i128* %2, align 16, !tbaa !2
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3)
ret i128 %5 ret i128 %5
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define i128 @_Z24atomic_load_acquire_u128RNSt3__16atomicIoEE(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0) { define i128 @_Z24atomic_load_acquire_u128RNSt3__16atomicIoEE(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0) {
; CHECK-LABEL: _Z24atomic_load_acquire_u128RNSt3__16atomicIoEE: ; CHECK-LABEL: _Z24atomic_load_acquire_u128RNSt3__16atomicIoEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 0, %s0 ; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 2, (0)1 ; CHECK-NEXT: or %s3, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9) ; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, -16(, %s9) ; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16 %2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8* %3 = bitcast i128* %2 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)
%4 = bitcast %"struct.std::__1::atomic.45"* %0 to i8* %4 = bitcast %"struct.std::__1::atomic.45"* %0 to i8*
call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 2) call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 2)
%5 = load i128, i128* %2, align 16, !tbaa !2 %5 = load i128, i128* %2, align 16, !tbaa !2
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3)
ret i128 %5 ret i128 %5
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i1 @_Z22atomic_load_seq_cst_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { define zeroext i1 @_Z22atomic_load_seq_cst_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_seq_cst_i1RNSt3__16atomicIbEE: ; CHECK-LABEL: _Z22atomic_load_seq_cst_i1RNSt3__16atomicIbEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: and %s0, 1, %s0 ; CHECK-NEXT: and %s0, 1, %s0
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 seq_cst, align 1 %3 = load atomic i8, i8* %2 seq_cst, align 1
%4 = and i8 %3, 1 %4 = and i8 %3, 1
%5 = icmp ne i8 %4, 0 %5 = icmp ne i8 %4, 0
ret i1 %5 ret i1 %5
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define signext i8 @_Z22atomic_load_seq_cst_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { define signext i8 @_Z22atomic_load_seq_cst_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_seq_cst_i8RNSt3__16atomicIcEE: ; CHECK-LABEL: _Z22atomic_load_seq_cst_i8RNSt3__16atomicIcEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.sx %s0, (, %s0) ; CHECK-NEXT: ld1b.sx %s0, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 seq_cst, align 1 %3 = load atomic i8, i8* %2 seq_cst, align 1
ret i8 %3 ret i8 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i8 @_Z22atomic_load_seq_cst_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) { define zeroext i8 @_Z22atomic_load_seq_cst_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_seq_cst_u8RNSt3__16atomicIhEE: ; CHECK-LABEL: _Z22atomic_load_seq_cst_u8RNSt3__16atomicIhEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 seq_cst, align 1 %3 = load atomic i8, i8* %2 seq_cst, align 1
ret i8 %3 ret i8 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define signext i16 @_Z23atomic_load_seq_cst_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { define signext i16 @_Z23atomic_load_seq_cst_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_i16RNSt3__16atomicIsEE: ; CHECK-LABEL: _Z23atomic_load_seq_cst_i16RNSt3__16atomicIsEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.sx %s0, (, %s0) ; CHECK-NEXT: ld2b.sx %s0, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 seq_cst, align 2 %3 = load atomic i16, i16* %2 seq_cst, align 2
ret i16 %3 ret i16 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i16 @_Z23atomic_load_seq_cst_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) { define zeroext i16 @_Z23atomic_load_seq_cst_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_u16RNSt3__16atomicItEE: ; CHECK-LABEL: _Z23atomic_load_seq_cst_u16RNSt3__16atomicItEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 seq_cst, align 2 %3 = load atomic i16, i16* %2 seq_cst, align 2
ret i16 %3 ret i16 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define signext i32 @_Z23atomic_load_seq_cst_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { define signext i32 @_Z23atomic_load_seq_cst_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_i32RNSt3__16atomicIiEE: ; CHECK-LABEL: _Z23atomic_load_seq_cst_i32RNSt3__16atomicIiEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 seq_cst, align 4 %3 = load atomic i32, i32* %2 seq_cst, align 4
ret i32 %3 ret i32 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define zeroext i32 @_Z23atomic_load_seq_cst_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) { define zeroext i32 @_Z23atomic_load_seq_cst_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_u32RNSt3__16atomicIjEE: ; CHECK-LABEL: _Z23atomic_load_seq_cst_u32RNSt3__16atomicIjEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldl.zx %s0, (, %s0) ; CHECK-NEXT: ldl.zx %s0, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 seq_cst, align 4 %3 = load atomic i32, i32* %2 seq_cst, align 4
ret i32 %3 ret i32 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_seq_cst_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { define i64 @_Z23atomic_load_seq_cst_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_i64RNSt3__16atomicIlEE: ; CHECK-LABEL: _Z23atomic_load_seq_cst_i64RNSt3__16atomicIlEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 seq_cst, align 8 %3 = load atomic i64, i64* %2 seq_cst, align 8
ret i64 %3 ret i64 %3
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_seq_cst_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) { define i64 @_Z23atomic_load_seq_cst_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_u64RNSt3__16atomicImEE: ; CHECK-LABEL: _Z23atomic_load_seq_cst_u64RNSt3__16atomicImEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 seq_cst, align 8 %3 = load atomic i64, i64* %2 seq_cst, align 8
ret i64 %3 ret i64 %3
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define i128 @_Z24atomic_load_seq_cst_i128RNSt3__16atomicInEE(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0) { define i128 @_Z24atomic_load_seq_cst_i128RNSt3__16atomicInEE(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0) {
; CHECK-LABEL: _Z24atomic_load_seq_cst_i128RNSt3__16atomicInEE: ; CHECK-LABEL: _Z24atomic_load_seq_cst_i128RNSt3__16atomicInEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 0, %s0 ; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 5, (0)1 ; CHECK-NEXT: or %s3, 5, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9) ; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, -16(, %s9) ; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16 %2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8* %3 = bitcast i128* %2 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)
%4 = bitcast %"struct.std::__1::atomic.40"* %0 to i8* %4 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 5) call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 5)
%5 = load i128, i128* %2, align 16, !tbaa !2 %5 = load i128, i128* %2, align 16, !tbaa !2
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3)
ret i128 %5 ret i128 %5
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define i128 @_Z24atomic_load_seq_cst_u128RNSt3__16atomicIoEE(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0) { define i128 @_Z24atomic_load_seq_cst_u128RNSt3__16atomicIoEE(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0) {
; CHECK-LABEL: _Z24atomic_load_seq_cst_u128RNSt3__16atomicIoEE: ; CHECK-LABEL: _Z24atomic_load_seq_cst_u128RNSt3__16atomicIoEE:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 0, %s0 ; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: lea %s0, __atomic_load@lo ; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 5, (0)1 ; CHECK-NEXT: or %s3, 5, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9) ; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, -16(, %s9) ; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16 %2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8* %3 = bitcast i128* %2 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %3)
%4 = bitcast %"struct.std::__1::atomic.45"* %0 to i8* %4 = bitcast %"struct.std::__1::atomic.45"* %0 to i8*
call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 5) call void @__atomic_load(i64 16, i8* nonnull %4, i8* nonnull %3, i32 signext 5)
%5 = load i128, i128* %2, align 16, !tbaa !2 %5 = load i128, i128* %2, align 16, !tbaa !2
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %3)
Show All 16 Lines

llvm/test/CodeGen/VE/Scalar/atomic_store.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
%"struct.std::__1::__atomic_base.46" = type { %"struct.std::__1::__atomic_base.47" } %"struct.std::__1::__atomic_base.46" = type { %"struct.std::__1::__atomic_base.47" }
%"struct.std::__1::__atomic_base.47" = type { %"struct.std::__1::__cxx_atomic_impl.48" } %"struct.std::__1::__atomic_base.47" = type { %"struct.std::__1::__cxx_atomic_impl.48" }
%"struct.std::__1::__cxx_atomic_impl.48" = type { %"struct.std::__1::__cxx_atomic_base_impl.49" } %"struct.std::__1::__cxx_atomic_impl.48" = type { %"struct.std::__1::__cxx_atomic_base_impl.49" }
%"struct.std::__1::__cxx_atomic_base_impl.49" = type { i128 } %"struct.std::__1::__cxx_atomic_base_impl.49" = type { i128 }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_relaxed_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) { define void @_Z23atomic_store_relaxed_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_relaxed_i1RNSt3__16atomicIbEEb: ; CHECK-LABEL: _Z23atomic_store_relaxed_i1RNSt3__16atomicIbEEb:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i1 %1 to i8 %3 = zext i1 %1 to i8
%4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 %4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %3, i8* %4 monotonic, align 1 store atomic i8 %3, i8* %4 monotonic, align 1
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_relaxed_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) { define void @_Z23atomic_store_relaxed_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) {
; CHECK-LABEL: _Z23atomic_store_relaxed_i8RNSt3__16atomicIcEEc: ; CHECK-LABEL: _Z23atomic_store_relaxed_i8RNSt3__16atomicIcEEc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 monotonic, align 1 store atomic i8 %1, i8* %3 monotonic, align 1
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_relaxed_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) { define void @_Z23atomic_store_relaxed_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_relaxed_u8RNSt3__16atomicIhEEh: ; CHECK-LABEL: _Z23atomic_store_relaxed_u8RNSt3__16atomicIhEEh:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 monotonic, align 1 store atomic i8 %1, i8* %3 monotonic, align 1
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) { define void @_Z24atomic_store_relaxed_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_i16RNSt3__16atomicIsEEs: ; CHECK-LABEL: _Z24atomic_store_relaxed_i16RNSt3__16atomicIsEEs:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 monotonic, align 2 store atomic i16 %1, i16* %3 monotonic, align 2
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) { define void @_Z24atomic_store_relaxed_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_u16RNSt3__16atomicItEEt: ; CHECK-LABEL: _Z24atomic_store_relaxed_u16RNSt3__16atomicItEEt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 monotonic, align 2 store atomic i16 %1, i16* %3 monotonic, align 2
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) { define void @_Z24atomic_store_relaxed_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_i32RNSt3__16atomicIiEEi: ; CHECK-LABEL: _Z24atomic_store_relaxed_i32RNSt3__16atomicIiEEi:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 monotonic, align 4 store atomic i32 %1, i32* %3 monotonic, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) { define void @_Z24atomic_store_relaxed_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_u32RNSt3__16atomicIjEEj: ; CHECK-LABEL: _Z24atomic_store_relaxed_u32RNSt3__16atomicIjEEj:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 monotonic, align 4 store atomic i32 %1, i32* %3 monotonic, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { define void @_Z24atomic_store_relaxed_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_i64RNSt3__16atomicIlEEl: ; CHECK-LABEL: _Z24atomic_store_relaxed_i64RNSt3__16atomicIlEEl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 monotonic, align 8 store atomic i64 %1, i64* %3 monotonic, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { define void @_Z24atomic_store_relaxed_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_u64RNSt3__16atomicImEEm: ; CHECK-LABEL: _Z24atomic_store_relaxed_u64RNSt3__16atomicImEEm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 monotonic, align 8 store atomic i64 %1, i64* %3 monotonic, align 8
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_Z25atomic_store_relaxed_i128RNSt3__16atomicInEEn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128 %1) { define void @_Z25atomic_store_relaxed_i128RNSt3__16atomicInEEn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z25atomic_store_relaxed_i128RNSt3__16atomicInEEn: ; CHECK-LABEL: _Z25atomic_store_relaxed_i128RNSt3__16atomicInEEn:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0 ; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9) ; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, -16(, %s9) ; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s1, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = alloca i128, align 16 %3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8* %4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
store i128 %1, i128* %3, align 16, !tbaa !2 store i128 %1, i128* %3, align 16, !tbaa !2
%5 = bitcast %"struct.std::__1::atomic.40"* %0 to i8* %5 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 0) call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 0)
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128 %1) { define void @_Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo: ; CHECK-LABEL: _Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0 ; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9) ; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, -16(, %s9) ; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s1, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = alloca i128, align 16 %3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8* %4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
store i128 %1, i128* %3, align 16, !tbaa !2 store i128 %1, i128* %3, align 16, !tbaa !2
%5 = bitcast %"struct.std::__1::atomic.45"* %0 to i8* %5 = bitcast %"struct.std::__1::atomic.45"* %0 to i8*
call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 0) call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 0)
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4)
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_release_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) { define void @_Z23atomic_store_release_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_release_i1RNSt3__16atomicIbEEb: ; CHECK-LABEL: _Z23atomic_store_release_i1RNSt3__16atomicIbEEb:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i1 %1 to i8 %3 = zext i1 %1 to i8
%4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 %4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %3, i8* %4 release, align 1 store atomic i8 %3, i8* %4 release, align 1
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_release_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) { define void @_Z23atomic_store_release_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) {
; CHECK-LABEL: _Z23atomic_store_release_i8RNSt3__16atomicIcEEc: ; CHECK-LABEL: _Z23atomic_store_release_i8RNSt3__16atomicIcEEc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 release, align 1 store atomic i8 %1, i8* %3 release, align 1
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_release_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) { define void @_Z23atomic_store_release_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_release_u8RNSt3__16atomicIhEEh: ; CHECK-LABEL: _Z23atomic_store_release_u8RNSt3__16atomicIhEEh:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 release, align 1 store atomic i8 %1, i8* %3 release, align 1
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) { define void @_Z24atomic_store_release_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) {
; CHECK-LABEL: _Z24atomic_store_release_i16RNSt3__16atomicIsEEs: ; CHECK-LABEL: _Z24atomic_store_release_i16RNSt3__16atomicIsEEs:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 release, align 2 store atomic i16 %1, i16* %3 release, align 2
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) { define void @_Z24atomic_store_release_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_release_u16RNSt3__16atomicItEEt: ; CHECK-LABEL: _Z24atomic_store_release_u16RNSt3__16atomicItEEt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 release, align 2 store atomic i16 %1, i16* %3 release, align 2
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) { define void @_Z24atomic_store_release_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) {
; CHECK-LABEL: _Z24atomic_store_release_i32RNSt3__16atomicIiEEi: ; CHECK-LABEL: _Z24atomic_store_release_i32RNSt3__16atomicIiEEi:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 release, align 4 store atomic i32 %1, i32* %3 release, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) { define void @_Z24atomic_store_release_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_release_u32RNSt3__16atomicIjEEj: ; CHECK-LABEL: _Z24atomic_store_release_u32RNSt3__16atomicIjEEj:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 release, align 4 store atomic i32 %1, i32* %3 release, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { define void @_Z24atomic_store_release_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_release_i64RNSt3__16atomicIlEEl: ; CHECK-LABEL: _Z24atomic_store_release_i64RNSt3__16atomicIlEEl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 release, align 8 store atomic i64 %1, i64* %3 release, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { define void @_Z24atomic_store_release_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_release_u64RNSt3__16atomicImEEm: ; CHECK-LABEL: _Z24atomic_store_release_u64RNSt3__16atomicImEEm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1 ; CHECK-NEXT: fencem 1
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 release, align 8 store atomic i64 %1, i64* %3 release, align 8
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_Z25atomic_store_release_i128RNSt3__16atomicInEEn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128 %1) { define void @_Z25atomic_store_release_i128RNSt3__16atomicInEEn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z25atomic_store_release_i128RNSt3__16atomicInEEn: ; CHECK-LABEL: _Z25atomic_store_release_i128RNSt3__16atomicInEEn:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0 ; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9) ; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, -16(, %s9) ; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 3, (0)1 ; CHECK-NEXT: or %s3, 3, (0)1
; CHECK-NEXT: or %s1, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = alloca i128, align 16 %3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8* %4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
store i128 %1, i128* %3, align 16, !tbaa !2 store i128 %1, i128* %3, align 16, !tbaa !2
%5 = bitcast %"struct.std::__1::atomic.40"* %0 to i8* %5 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 3) call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 3)
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_Z25atomic_store_release_u128RNSt3__16atomicIoEEo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128 %1) { define void @_Z25atomic_store_release_u128RNSt3__16atomicIoEEo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z25atomic_store_release_u128RNSt3__16atomicIoEEo: ; CHECK-LABEL: _Z25atomic_store_release_u128RNSt3__16atomicIoEEo:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0 ; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9) ; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, -16(, %s9) ; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 3, (0)1 ; CHECK-NEXT: or %s3, 3, (0)1
; CHECK-NEXT: or %s1, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = alloca i128, align 16 %3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8* %4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
store i128 %1, i128* %3, align 16, !tbaa !2 store i128 %1, i128* %3, align 16, !tbaa !2
%5 = bitcast %"struct.std::__1::atomic.45"* %0 to i8* %5 = bitcast %"struct.std::__1::atomic.45"* %0 to i8*
call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 3) call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 3)
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4)
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_seq_cst_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) { define void @_Z23atomic_store_seq_cst_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_seq_cst_i1RNSt3__16atomicIbEEb: ; CHECK-LABEL: _Z23atomic_store_seq_cst_i1RNSt3__16atomicIbEEb:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i1 %1 to i8 %3 = zext i1 %1 to i8
%4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0 %4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %3, i8* %4 seq_cst, align 1 store atomic i8 %3, i8* %4 seq_cst, align 1
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_seq_cst_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) { define void @_Z23atomic_store_seq_cst_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) {
; CHECK-LABEL: _Z23atomic_store_seq_cst_i8RNSt3__16atomicIcEEc: ; CHECK-LABEL: _Z23atomic_store_seq_cst_i8RNSt3__16atomicIcEEc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 seq_cst, align 1 store atomic i8 %1, i8* %3 seq_cst, align 1
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_seq_cst_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) { define void @_Z23atomic_store_seq_cst_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_seq_cst_u8RNSt3__16atomicIhEEh: ; CHECK-LABEL: _Z23atomic_store_seq_cst_u8RNSt3__16atomicIhEEh:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 seq_cst, align 1 store atomic i8 %1, i8* %3 seq_cst, align 1
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) { define void @_Z24atomic_store_seq_cst_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_i16RNSt3__16atomicIsEEs: ; CHECK-LABEL: _Z24atomic_store_seq_cst_i16RNSt3__16atomicIsEEs:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 seq_cst, align 2 store atomic i16 %1, i16* %3 seq_cst, align 2
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) { define void @_Z24atomic_store_seq_cst_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_u16RNSt3__16atomicItEEt: ; CHECK-LABEL: _Z24atomic_store_seq_cst_u16RNSt3__16atomicItEEt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 seq_cst, align 2 store atomic i16 %1, i16* %3 seq_cst, align 2
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) { define void @_Z24atomic_store_seq_cst_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_i32RNSt3__16atomicIiEEi: ; CHECK-LABEL: _Z24atomic_store_seq_cst_i32RNSt3__16atomicIiEEi:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 seq_cst, align 4 store atomic i32 %1, i32* %3 seq_cst, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) { define void @_Z24atomic_store_seq_cst_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_u32RNSt3__16atomicIjEEj: ; CHECK-LABEL: _Z24atomic_store_seq_cst_u32RNSt3__16atomicIjEEj:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 seq_cst, align 4 store atomic i32 %1, i32* %3 seq_cst, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { define void @_Z24atomic_store_seq_cst_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_i64RNSt3__16atomicIlEEl: ; CHECK-LABEL: _Z24atomic_store_seq_cst_i64RNSt3__16atomicIlEEl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 seq_cst, align 8 store atomic i64 %1, i64* %3 seq_cst, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind ; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { define void @_Z24atomic_store_seq_cst_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_u64RNSt3__16atomicImEEm: ; CHECK-LABEL: _Z24atomic_store_seq_cst_u64RNSt3__16atomicImEEm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: fencem 3 ; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0 %3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 seq_cst, align 8 store atomic i64 %1, i64* %3 seq_cst, align 8
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_Z25atomic_store_seq_cst_i128RNSt3__16atomicInEEn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128 %1) { define void @_Z25atomic_store_seq_cst_i128RNSt3__16atomicInEEn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z25atomic_store_seq_cst_i128RNSt3__16atomicInEEn: ; CHECK-LABEL: _Z25atomic_store_seq_cst_i128RNSt3__16atomicInEEn:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0 ; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9) ; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, -16(, %s9) ; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 5, (0)1 ; CHECK-NEXT: or %s3, 5, (0)1
; CHECK-NEXT: or %s1, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = alloca i128, align 16 %3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8* %4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
store i128 %1, i128* %3, align 16, !tbaa !2 store i128 %1, i128* %3, align 16, !tbaa !2
%5 = bitcast %"struct.std::__1::atomic.40"* %0 to i8* %5 = bitcast %"struct.std::__1::atomic.40"* %0 to i8*
call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 5) call void @__atomic_store(i64 16, i8* nonnull %5, i8* nonnull %4, i32 signext 5)
call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %4)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_Z25atomic_store_seq_cst_u128RNSt3__16atomicIoEEo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128 %1) { define void @_Z25atomic_store_seq_cst_u128RNSt3__16atomicIoEEo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z25atomic_store_seq_cst_u128RNSt3__16atomicIoEEo: ; CHECK-LABEL: _Z25atomic_store_seq_cst_u128RNSt3__16atomicIoEEo:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0 ; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9) ; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, -16(, %s9) ; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo ; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9) ; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 5, (0)1 ; CHECK-NEXT: or %s3, 5, (0)1
; CHECK-NEXT: or %s1, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = alloca i128, align 16 %3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8* %4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4) call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
Show All 20 Lines

llvm/test/CodeGen/VE/Scalar/bitcast.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local i64 @bitcastd2l(double %x) { define dso_local i64 @bitcastd2l(double %x) {
; CHECK-LABEL: bitcastd2l: ; CHECK-LABEL: bitcastd2l:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = bitcast double %x to i64 %r = bitcast double %x to i64
ret i64 %r ret i64 %r
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local double @bitcastl2d(i64 %x) { define dso_local double @bitcastl2d(i64 %x) {
; CHECK-LABEL: bitcastl2d: ; CHECK-LABEL: bitcastl2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = bitcast i64 %x to double %r = bitcast i64 %x to double
ret double %r ret double %r
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local float @bitcastw2f(i32 %x) { define dso_local float @bitcastw2f(i32 %x) {
; CHECK-LABEL: bitcastw2f: ; CHECK-LABEL: bitcastw2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 32 ; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = bitcast i32 %x to float %r = bitcast i32 %x to float
ret float %r ret float %r
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local i32 @bitcastf2w(float %x) { define dso_local i32 @bitcastf2w(float %x) {
; CHECK-LABEL: bitcastf2w: ; CHECK-LABEL: bitcastf2w:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = bitcast float %x to i32 %r = bitcast float %x to i32
ret i32 %r ret i32 %r
} }

llvm/test/CodeGen/VE/Scalar/bitreverse.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
declare i128 @llvm.bitreverse.i128(i128) declare i128 @llvm.bitreverse.i128(i128)
declare i64 @llvm.bitreverse.i64(i64) declare i64 @llvm.bitreverse.i64(i64)
declare i32 @llvm.bitreverse.i32(i32) declare i32 @llvm.bitreverse.i32(i32)
declare i16 @llvm.bitreverse.i16(i16) declare i16 @llvm.bitreverse.i16(i16)
declare i8 @llvm.bitreverse.i8(i8) declare i8 @llvm.bitreverse.i8(i8)
define i128 @func128(i128 %p) { define i128 @func128(i128 %p) {
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: brv %s2, %s1 ; CHECK-NEXT: brv %s2, %s1
; CHECK-NEXT: brv %s1, %s0 ; CHECK-NEXT: brv %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.bitreverse.i128(i128 %p) %r = tail call i128 @llvm.bitreverse.i128(i128 %p)
ret i128 %r ret i128 %r
} }
define i64 @func64(i64 %p) { define i64 @func64(i64 %p) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.bitreverse.i64(i64 %p) %r = tail call i64 @llvm.bitreverse.i64(i64 %p)
ret i64 %r ret i64 %r
} }
define signext i32 @func32s(i32 signext %p) { define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bitreverse.i32(i32 %p) %r = tail call i32 @llvm.bitreverse.i32(i32 %p)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32z(i32 zeroext %p) { define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 32 ; CHECK-NEXT: srl %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bitreverse.i32(i32 %p) %r = tail call i32 @llvm.bitreverse.i32(i32 %p)
ret i32 %r ret i32 %r
} }
define signext i16 @func16s(i16 signext %p) { define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bitreverse.i16(i16 %p) %r = tail call i16 @llvm.bitreverse.i16(i16 %p)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16z(i16 zeroext %p) { define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 48 ; CHECK-NEXT: srl %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bitreverse.i16(i16 %p) %r = tail call i16 @llvm.bitreverse.i16(i16 %p)
ret i16 %r ret i16 %r
} }
define signext i8 @func8s(i8 signext %p) { define signext i8 @func8s(i8 signext %p) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.bitreverse.i8(i8 %p) %r = tail call i8 @llvm.bitreverse.i8(i8 %p)
ret i8 %r ret i8 %r
} }
define zeroext i8 @func8z(i8 zeroext %p) { define zeroext i8 @func8z(i8 zeroext %p) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0 ; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 56 ; CHECK-NEXT: srl %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.bitreverse.i8(i8 %p) %r = tail call i8 @llvm.bitreverse.i8(i8 %p)
ret i8 %r ret i8 %r
} }
define i128 @func128i() { define i128 @func128i() {
; CHECK-LABEL: func128i: ; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: lea.sl %s1, -65536 ; CHECK-NEXT: lea.sl %s1, -65536
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.bitreverse.i128(i128 65535) %r = tail call i128 @llvm.bitreverse.i128(i128 65535)
ret i128 %r ret i128 %r
} }
define i64 @func64i() { define i64 @func64i() {
; CHECK-LABEL: func64i: ; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -65536 ; CHECK-NEXT: lea.sl %s0, -65536
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.bitreverse.i64(i64 65535) %r = tail call i64 @llvm.bitreverse.i64(i64 65535)
ret i64 %r ret i64 %r
} }
define signext i32 @func32is() { define signext i32 @func32is() {
; CHECK-LABEL: func32is: ; CHECK-LABEL: func32is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -65536 ; CHECK-NEXT: lea %s0, -65536
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bitreverse.i32(i32 65535) %r = tail call i32 @llvm.bitreverse.i32(i32 65535)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32iz() { define zeroext i32 @func32iz() {
; CHECK-LABEL: func32iz: ; CHECK-LABEL: func32iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -65536 ; CHECK-NEXT: lea %s0, -65536
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bitreverse.i32(i32 65535) %r = tail call i32 @llvm.bitreverse.i32(i32 65535)
ret i32 %r ret i32 %r
} }
define signext i16 @func16is() { define signext i16 @func16is() {
; CHECK-LABEL: func16is: ; CHECK-LABEL: func16is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -256 ; CHECK-NEXT: lea %s0, -256
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bitreverse.i16(i16 255) %r = tail call i16 @llvm.bitreverse.i16(i16 255)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16iz() { define zeroext i16 @func16iz() {
; CHECK-LABEL: func16iz: ; CHECK-LABEL: func16iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 65280 ; CHECK-NEXT: lea %s0, 65280
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bitreverse.i16(i16 255) %r = tail call i16 @llvm.bitreverse.i16(i16 255)
ret i16 %r ret i16 %r
} }
define signext i8 @func8is() { define signext i8 @func8is() {
; CHECK-LABEL: func8is: ; CHECK-LABEL: func8is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 15, (0)1 ; CHECK-NEXT: or %s0, 15, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.bitreverse.i8(i8 240) %r = tail call i8 @llvm.bitreverse.i8(i8 240)
ret i8 %r ret i8 %r
} }
define zeroext i8 @func8iz() { define zeroext i8 @func8iz() {
; CHECK-LABEL: func8iz: ; CHECK-LABEL: func8iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 15, (0)1 ; CHECK-NEXT: or %s0, 15, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.bitreverse.i8(i8 240) %r = tail call i8 @llvm.bitreverse.i8(i8 240)
ret i8 %r ret i8 %r
} }

llvm/test/CodeGen/VE/Scalar/blockaddress.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
@addr = global i8* null, align 8 @addr = global i8* null, align 8
; Function Attrs: nofree norecurse nounwind writeonly ; Function Attrs: nofree norecurse nounwind writeonly
define void @test() { define void @test() {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: .LBB0_3: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: .Ltmp0: # Block address taken ; CHECK-NEXT: .Ltmp0: # Block address taken
; CHECK-NEXT: # %bb.1: # %test1 ; CHECK-NEXT: # %bb.1: # %test1
; CHECK-NEXT: lea %s0, addr@lo ; CHECK-NEXT: lea %s0, addr@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, addr@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, addr@hi(, %s0)
; CHECK-NEXT: lea %s1, .Ltmp0@lo ; CHECK-NEXT: lea %s1, .Ltmp0@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .Ltmp0@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, .Ltmp0@hi(, %s1)
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
br label %test1 br label %test1
test1: test1:
store i8* blockaddress(@test, %test1), i8** @addr, align 8 store i8* blockaddress(@test, %test1), i8** @addr, align 8
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/br_cc.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) { define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: br_cc_i1_var: ; CHECK-LABEL: br_cc_i1_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, %1 %3 = xor i1 %0, %1
br i1 %3, label %5, label %4 br i1 %3, label %5, label %4
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i8_var(i8 signext %0, i8 signext %1) { define void @br_cc_i8_var(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: br_cc_i8_var: ; CHECK-LABEL: br_cc_i8_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1 %3 = icmp eq i8 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) { define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: br_cc_u8_var: ; CHECK-LABEL: br_cc_u8_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1 %3 = icmp eq i8 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i16_var(i16 signext %0, i16 signext %1) { define void @br_cc_i16_var(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: br_cc_i16_var: ; CHECK-LABEL: br_cc_i16_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1 %3 = icmp eq i16 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) { define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: br_cc_u16_var: ; CHECK-LABEL: br_cc_u16_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1 %3 = icmp eq i16 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i32_var(i32 signext %0, i32 signext %1) { define void @br_cc_i32_var(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: br_cc_i32_var: ; CHECK-LABEL: br_cc_i32_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1 %3 = icmp eq i32 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) { define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: br_cc_u32_var: ; CHECK-LABEL: br_cc_u32_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1 %3 = icmp eq i32 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i64_var(i64 %0, i64 %1) { define void @br_cc_i64_var(i64 %0, i64 %1) {
; CHECK-LABEL: br_cc_i64_var: ; CHECK-LABEL: br_cc_i64_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1 %3 = icmp eq i64 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u64_var(i64 %0, i64 %1) { define void @br_cc_u64_var(i64 %0, i64 %1) {
; CHECK-LABEL: br_cc_u64_var: ; CHECK-LABEL: br_cc_u64_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1 %3 = icmp eq i64 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i128_var(i128 %0, i128 %1) { define void @br_cc_i128_var(i128 %0, i128 %1) {
; CHECK-LABEL: br_cc_i128_var: ; CHECK-LABEL: br_cc_i128_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: brne.l 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.l 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1 %3 = icmp eq i128 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u128_var(i128 %0, i128 %1) { define void @br_cc_u128_var(i128 %0, i128 %1) {
; CHECK-LABEL: br_cc_u128_var: ; CHECK-LABEL: br_cc_u128_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: brne.l 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.l 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1 %3 = icmp eq i128 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_float_var(float %0, float %1) { define void @br_cc_float_var(float %0, float %1) {
; CHECK-LABEL: br_cc_float_var: ; CHECK-LABEL: br_cc_float_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.s %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.s %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq float %0, %1 %3 = fcmp fast oeq float %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_double_var(double %0, double %1) { define void @br_cc_double_var(double %0, double %1) {
; CHECK-LABEL: br_cc_double_var: ; CHECK-LABEL: br_cc_double_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.d %s0, %s1, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.d %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq double %0, %1 %3 = fcmp fast oeq double %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_quad_var(fp128 %0, fp128 %1) { define void @br_cc_quad_var(fp128 %0, fp128 %1) {
; CHECK-LABEL: br_cc_quad_var: ; CHECK-LABEL: br_cc_quad_var:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s2, %s0 ; CHECK-NEXT: fcmp.q %s0, %s2, %s0
; CHECK-NEXT: brne.d 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.d 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq fp128 %0, %1 %3 = fcmp fast oeq fp128 %0, %1
br i1 %3, label %4, label %5 br i1 %3, label %4, label %5
4: ; preds = %2 4: ; preds = %2
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %5 br label %5
5: ; preds = %4, %2 5: ; preds = %4, %2
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i1_imm(i1 zeroext %0) { define void @br_cc_i1_imm(i1 zeroext %0) {
; CHECK-LABEL: br_cc_i1_imm: ; CHECK-LABEL: br_cc_i1_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %3, label %2 br i1 %0, label %3, label %2
2: ; preds = %1 2: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %3 br label %3
3: ; preds = %2, %1 3: ; preds = %2, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i8_imm(i8 signext %0) { define void @br_cc_i8_imm(i8 signext %0) {
; CHECK-LABEL: br_cc_i8_imm: ; CHECK-LABEL: br_cc_i8_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brlt.w -10, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brlt.w -10, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i8 %0, -9 %2 = icmp slt i8 %0, -9
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u8_imm(i8 zeroext %0) { define void @br_cc_u8_imm(i8 zeroext %0) {
; CHECK-LABEL: br_cc_u8_imm: ; CHECK-LABEL: br_cc_u8_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 8, %s0 ; CHECK-NEXT: cmpu.w %s0, 8, %s0
; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i8 %0, 9 %2 = icmp ult i8 %0, 9
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i16_imm(i16 signext %0) { define void @br_cc_i16_imm(i16 signext %0) {
; CHECK-LABEL: br_cc_i16_imm: ; CHECK-LABEL: br_cc_i16_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brlt.w 62, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brlt.w 62, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i16 %0, 63 %2 = icmp slt i16 %0, 63
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u16_imm(i16 zeroext %0) { define void @br_cc_u16_imm(i16 zeroext %0) {
; CHECK-LABEL: br_cc_u16_imm: ; CHECK-LABEL: br_cc_u16_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 63, %s0 ; CHECK-NEXT: cmpu.w %s0, 63, %s0
; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i16 %0, 64 %2 = icmp ult i16 %0, 64
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i32_imm(i32 signext %0) { define void @br_cc_i32_imm(i32 signext %0) {
; CHECK-LABEL: br_cc_i32_imm: ; CHECK-LABEL: br_cc_i32_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brlt.w 63, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brlt.w 63, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i32 %0, 64 %2 = icmp slt i32 %0, 64
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u32_imm(i32 zeroext %0) { define void @br_cc_u32_imm(i32 zeroext %0) {
; CHECK-LABEL: br_cc_u32_imm: ; CHECK-LABEL: br_cc_u32_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 63, %s0 ; CHECK-NEXT: cmpu.w %s0, 63, %s0
; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i32 %0, 64 %2 = icmp ult i32 %0, 64
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i64_imm(i64 %0) { define void @br_cc_i64_imm(i64 %0) {
; CHECK-LABEL: br_cc_i64_imm: ; CHECK-LABEL: br_cc_i64_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brlt.l 63, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brlt.l 63, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i64 %0, 64 %2 = icmp slt i64 %0, 64
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u64_imm(i64 %0) { define void @br_cc_u64_imm(i64 %0) {
; CHECK-LABEL: br_cc_u64_imm: ; CHECK-LABEL: br_cc_u64_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, 63, %s0 ; CHECK-NEXT: cmpu.l %s0, 63, %s0
; CHECK-NEXT: brgt.l 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.l 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i64 %0, 64 %2 = icmp ult i64 %0, 64
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_i128_imm(i128 %0) { define void @br_cc_i128_imm(i128 %0) {
; CHECK-LABEL: br_cc_i128_imm: ; CHECK-LABEL: br_cc_i128_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, (0)1 ; CHECK-NEXT: cmps.l %s1, %s1, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1 ; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, (58)0 ; CHECK-NEXT: cmpu.l %s0, %s0, (58)0
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i128 %0, 64 %2 = icmp slt i128 %0, 64
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_u128_imm(i128 %0) { define void @br_cc_u128_imm(i128 %0) {
; CHECK-LABEL: br_cc_u128_imm: ; CHECK-LABEL: br_cc_u128_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, (0)1 ; CHECK-NEXT: cmps.l %s1, %s1, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1 ; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, (58)0 ; CHECK-NEXT: cmpu.l %s0, %s0, (58)0
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i128 %0, 64 %2 = icmp ult i128 %0, 64
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_float_imm(float %0) { define void @br_cc_float_imm(float %0) {
; CHECK-LABEL: br_cc_float_imm: ; CHECK-LABEL: br_cc_float_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brle.s 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brle.s 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast olt float %0, 0.000000e+00 %2 = fcmp fast olt float %0, 0.000000e+00
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_double_imm(double %0) { define void @br_cc_double_imm(double %0) {
; CHECK-LABEL: br_cc_double_imm: ; CHECK-LABEL: br_cc_double_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brle.d 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brle.d 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast olt double %0, 0.000000e+00 %2 = fcmp fast olt double %0, 0.000000e+00
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_quad_imm(fp128 %0) { define void @br_cc_quad_imm(fp128 %0) {
; CHECK-LABEL: br_cc_quad_imm: ; CHECK-LABEL: br_cc_quad_imm:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fcmp.q %s0, %s4, %s0 ; CHECK-NEXT: fcmp.q %s0, %s4, %s0
; CHECK-NEXT: brge.d 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brge.d 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast olt fp128 %0, 0xL00000000000000000000000000000000 %2 = fcmp fast olt fp128 %0, 0xL00000000000000000000000000000000
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_i1(i1 zeroext %0) { define void @br_cc_imm_i1(i1 zeroext %0) {
; CHECK-LABEL: br_cc_imm_i1: ; CHECK-LABEL: br_cc_imm_i1:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %2, label %3 br i1 %0, label %2, label %3
2: ; preds = %1 2: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %3 br label %3
3: ; preds = %2, %1 3: ; preds = %2, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_i8(i8 signext %0) { define void @br_cc_imm_i8(i8 signext %0) {
; CHECK-LABEL: br_cc_imm_i8: ; CHECK-LABEL: br_cc_imm_i8:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brgt.w -9, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.w -9, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i8 %0, -10 %2 = icmp sgt i8 %0, -10
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_u8(i8 zeroext %0) { define void @br_cc_imm_u8(i8 zeroext %0) {
; CHECK-LABEL: br_cc_imm_u8: ; CHECK-LABEL: br_cc_imm_u8:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 9, %s0 ; CHECK-NEXT: cmpu.w %s0, 9, %s0
; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i8 %0, 8 %2 = icmp ugt i8 %0, 8
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_i16(i16 signext %0) { define void @br_cc_imm_i16(i16 signext %0) {
; CHECK-LABEL: br_cc_imm_i16: ; CHECK-LABEL: br_cc_imm_i16:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brgt.w 63, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.w 63, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i16 %0, 62 %2 = icmp sgt i16 %0, 62
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_u16(i16 zeroext %0) { define void @br_cc_imm_u16(i16 zeroext %0) {
; CHECK-LABEL: br_cc_imm_u16: ; CHECK-LABEL: br_cc_imm_u16:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 64 ; CHECK-NEXT: lea %s1, 64
; CHECK-NEXT: cmpu.w %s0, %s1, %s0 ; CHECK-NEXT: cmpu.w %s0, %s1, %s0
; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i16 %0, 63 %2 = icmp ugt i16 %0, 63
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_i32(i32 signext %0) { define void @br_cc_imm_i32(i32 signext %0) {
; CHECK-LABEL: br_cc_imm_i32: ; CHECK-LABEL: br_cc_imm_i32:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brgt.w -64, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.w -64, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i32 %0, -65 %2 = icmp sgt i32 %0, -65
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_u32(i32 zeroext %0) { define void @br_cc_imm_u32(i32 zeroext %0) {
; CHECK-LABEL: br_cc_imm_u32: ; CHECK-LABEL: br_cc_imm_u32:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, -64, %s0 ; CHECK-NEXT: cmpu.w %s0, -64, %s0
; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i32 %0, -65 %2 = icmp ugt i32 %0, -65
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_i64(i64 %0) { define void @br_cc_imm_i64(i64 %0) {
; CHECK-LABEL: br_cc_imm_i64: ; CHECK-LABEL: br_cc_imm_i64:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brgt.l -64, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.l -64, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i64 %0, -65 %2 = icmp sgt i64 %0, -65
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_u64(i64 %0) { define void @br_cc_imm_u64(i64 %0) {
; CHECK-LABEL: br_cc_imm_u64: ; CHECK-LABEL: br_cc_imm_u64:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, -64, %s0 ; CHECK-NEXT: cmpu.l %s0, -64, %s0
; CHECK-NEXT: brlt.l 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brlt.l 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i64 %0, -65 %2 = icmp ugt i64 %0, -65
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_i128(i128 %0) { define void @br_cc_imm_i128(i128 %0) {
; CHECK-LABEL: br_cc_imm_i128: ; CHECK-LABEL: br_cc_imm_i128:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, (0)0 ; CHECK-NEXT: cmps.l %s1, %s1, (0)0
; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s1 ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, (58)1 ; CHECK-NEXT: cmpu.l %s0, %s0, (58)1
; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i128 %0, -65 %2 = icmp sgt i128 %0, -65
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_u128(i128 %0) { define void @br_cc_imm_u128(i128 %0) {
; CHECK-LABEL: br_cc_imm_u128: ; CHECK-LABEL: br_cc_imm_u128:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, (0)0 ; CHECK-NEXT: cmps.l %s1, %s1, (0)0
; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1 ; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, (58)1 ; CHECK-NEXT: cmpu.l %s0, %s0, (58)1
; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i128 %0, -65 %2 = icmp ugt i128 %0, -65
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_float(float %0) { define void @br_cc_imm_float(float %0) {
; CHECK-LABEL: br_cc_imm_float: ; CHECK-LABEL: br_cc_imm_float:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brgt.s 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.s 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast ult float %0, 0.000000e+00 %2 = fcmp fast ult float %0, 0.000000e+00
br i1 %2, label %4, label %3 br i1 %2, label %4, label %3
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_double(double %0) { define void @br_cc_imm_double(double %0) {
; CHECK-LABEL: br_cc_imm_double: ; CHECK-LABEL: br_cc_imm_double:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brgt.d 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brgt.d 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast ult double %0, 0.000000e+00 %2 = fcmp fast ult double %0, 0.000000e+00
br i1 %2, label %4, label %3 br i1 %2, label %4, label %3
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br_cc_imm_quad(fp128 %0) { define void @br_cc_imm_quad(fp128 %0) {
; CHECK-LABEL: br_cc_imm_quad: ; CHECK-LABEL: br_cc_imm_quad:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fcmp.q %s0, %s4, %s0 ; CHECK-NEXT: fcmp.q %s0, %s4, %s0
; CHECK-NEXT: brlt.d 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brlt.d 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast ult fp128 %0, 0xL00000000000000000000000000000000 %2 = fcmp fast ult fp128 %0, 0xL00000000000000000000000000000000
br i1 %2, label %4, label %3 br i1 %2, label %4, label %3
3: ; preds = %1 3: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %4 br label %4
4: ; preds = %3, %1 4: ; preds = %3, %1
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/br_jt.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @br_jt(i32 signext %0) { define signext i32 @br_jt(i32 signext %0) {
; CHECK-LABEL: br_jt: ; CHECK-LABEL: br_jt:
; CHECK: .LBB{{[0-9]+}}_11: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: brlt.w 2, %s0, .LBB{{[0-9]+}}_3 ; CHECK-NEXT: brlt.w 2, %s0, .LBB{{[0-9]+}}_4
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: breq.w 1, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: breq.w 1, %s0, .LBB{{[0-9]+}}_8
; CHECK-NEXT: # %bb.8: ; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: brne.w 2, %s0, .LBB{{[0-9]+}}_9 ; CHECK-NEXT: brne.w 2, %s0, .LBB{{[0-9]+}}_7
; CHECK-NEXT: # %bb.6: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_9 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: .LBB{{[0-9]+}}_3: ; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: breq.w 3, %s0, .LBB{{[0-9]+}}_7 ; CHECK-NEXT: .LBB{{[0-9]+}}_4:
; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: breq.w 3, %s0, .LBB{{[0-9]+}}_9
; CHECK-NEXT: brne.w 4, %s0, .LBB{{[0-9]+}}_9
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: brne.w 4, %s0, .LBB{{[0-9]+}}_7
; CHECK-NEXT: # %bb.6:
; CHECK-NEXT: or %s0, 7, (0)1 ; CHECK-NEXT: or %s0, 7, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_9
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_9
; CHECK-NEXT: .LBB{{[0-9]+}}_7: ; CHECK-NEXT: .LBB{{[0-9]+}}_7:
; CHECK-NEXT: or %s0, 4, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .LBB{{[0-9]+}}_8:
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .LBB{{[0-9]+}}_9: ; CHECK-NEXT: .LBB{{[0-9]+}}_9:
; CHECK-NEXT: or %s0, 4, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
switch i32 %0, label %5 [ switch i32 %0, label %5 [
i32 1, label %6 i32 1, label %6
i32 2, label %2 i32 2, label %2
i32 3, label %3 i32 3, label %3
i32 4, label %4 i32 4, label %4
] ]
2: ; preds = %1 2: ; preds = %1
Show All 15 Lines

llvm/test/CodeGen/VE/Scalar/brcond.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @brcond_then(i1 zeroext %0) { define void @brcond_then(i1 zeroext %0) {
; CHECK-LABEL: brcond_then: ; CHECK-LABEL: brcond_then:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %2, label %3 br i1 %0, label %2, label %3
2: ; preds = %1 2: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %3 br label %3
3: ; preds = %2, %1 3: ; preds = %2, %1
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @brcond_else(i1 zeroext %0) { define void @brcond_else(i1 zeroext %0) {
; CHECK-LABEL: brcond_else: ; CHECK-LABEL: brcond_else:
; CHECK: .LBB{{[0-9]+}}_4: ; CHECK: # %bb.0:
; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2 ; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %3, label %2 br i1 %0, label %3, label %2
2: ; preds = %1 2: ; preds = %1
tail call void asm sideeffect "nop", ""() tail call void asm sideeffect "nop", ""()
br label %3 br label %3
3: ; preds = %2, %1 3: ; preds = %2, %1
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/brind.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @brind(i32 signext %0) { define signext i32 @brind(i32 signext %0) {
; CHECK-LABEL: brind: ; CHECK-LABEL: brind:
; CHECK: .LBB{{[0-9]+}}_6: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 1, (0)1 ; CHECK-NEXT: or %s1, 1, (0)1
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: lea %s2, .Ltmp0@lo ; CHECK-NEXT: lea %s2, .Ltmp0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .Ltmp0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .Ltmp0@hi(, %s2)
; CHECK-NEXT: lea %s3, .Ltmp1@lo ; CHECK-NEXT: lea %s3, .Ltmp1@lo
; CHECK-NEXT: and %s3, %s3, (32)0 ; CHECK-NEXT: and %s3, %s3, (32)0
; CHECK-NEXT: lea.sl %s3, .Ltmp1@hi(, %s3) ; CHECK-NEXT: lea.sl %s3, .Ltmp1@hi(, %s3)
; CHECK-NEXT: cmov.w.eq %s2, %s3, %s1 ; CHECK-NEXT: cmov.w.eq %s2, %s3, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: lea %s1, .Ltmp2@lo ; CHECK-NEXT: lea %s1, .Ltmp2@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .Ltmp2@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, .Ltmp2@hi(, %s1)
; CHECK-NEXT: cmov.w.eq %s1, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s1, %s2, %s0
; CHECK-NEXT: b.l.t (, %s1) ; CHECK-NEXT: b.l.t (, %s1)
; CHECK-NEXT: .Ltmp0: # Block address taken ; CHECK-NEXT: .Ltmp0: # Block address taken
; CHECK-NEXT: .LBB{{[0-9]+}}_3: ; CHECK-NEXT: .LBB{{[0-9]+}}_3:
; CHECK-NEXT: or %s0, -1, (0)1 ; CHECK-NEXT: or %s0, -1, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_4 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .Ltmp2: # Block address taken ; CHECK-NEXT: .Ltmp2: # Block address taken
; CHECK-NEXT: .LBB{{[0-9]+}}_2: ; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 2, (0)1 ; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_4 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .Ltmp1: # Block address taken ; CHECK-NEXT: .Ltmp1: # Block address taken
; CHECK-NEXT: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: .LBB{{[0-9]+}}_4: # %.split
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp eq i32 %0, 1 %2 = icmp eq i32 %0, 1
%3 = select i1 %2, i8* blockaddress(@brind, %6), i8* blockaddress(@brind, %8) %3 = select i1 %2, i8* blockaddress(@brind, %6), i8* blockaddress(@brind, %8)
%4 = icmp eq i32 %0, 0 %4 = icmp eq i32 %0, 0
%5 = select i1 %4, i8* %3, i8* blockaddress(@brind, %7) %5 = select i1 %4, i8* %3, i8* blockaddress(@brind, %7)
indirectbr i8* %5, [label %8, label %6, label %7] indirectbr i8* %5, [label %8, label %6, label %7]
6: ; preds = %1 6: ; preds = %1
br label %8 br label %8
7: ; preds = %1 7: ; preds = %1
br label %8 br label %8
8: ; preds = %1, %7, %6 8: ; preds = %1, %7, %6
%9 = phi i32 [ 2, %7 ], [ 1, %6 ], [ -1, %1 ] %9 = phi i32 [ 2, %7 ], [ 1, %6 ], [ -1, %1 ]
ret i32 %9 ret i32 %9
} }

llvm/test/CodeGen/VE/Scalar/bswap.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
declare i128 @llvm.bswap.i128(i128) declare i128 @llvm.bswap.i128(i128)
declare i64 @llvm.bswap.i64(i64) declare i64 @llvm.bswap.i64(i64)
declare i32 @llvm.bswap.i32(i32) declare i32 @llvm.bswap.i32(i32)
declare i16 @llvm.bswap.i16(i16) declare i16 @llvm.bswap.i16(i16)
define i128 @func128(i128 %p) { define i128 @func128(i128 %p) {
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s2, %s1, 0 ; CHECK-NEXT: bswp %s2, %s1, 0
; CHECK-NEXT: bswp %s1, %s0, 0 ; CHECK-NEXT: bswp %s1, %s0, 0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.bswap.i128(i128 %p) %r = tail call i128 @llvm.bswap.i128(i128 %p)
ret i128 %r ret i128 %r
} }
define i64 @func64(i64 %p) { define i64 @func64(i64 %p) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 0 ; CHECK-NEXT: bswp %s0, %s0, 0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.bswap.i64(i64 %p) %r = tail call i64 @llvm.bswap.i64(i64 %p)
ret i64 %r ret i64 %r
} }
define signext i32 @func32s(i32 signext %p) { define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 1 ; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bswap.i32(i32 %p) %r = tail call i32 @llvm.bswap.i32(i32 %p)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32z(i32 zeroext %p) { define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 1 ; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bswap.i32(i32 %p) %r = tail call i32 @llvm.bswap.i32(i32 %p)
ret i32 %r ret i32 %r
} }
define signext i16 @func16s(i16 signext %p) { define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 1 ; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 16 ; CHECK-NEXT: srl %s0, %s0, 16
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bswap.i16(i16 %p) %r = tail call i16 @llvm.bswap.i16(i16 %p)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16z(i16 zeroext %p) { define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 1 ; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 16 ; CHECK-NEXT: srl %s0, %s0, 16
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bswap.i16(i16 %p) %r = tail call i16 @llvm.bswap.i16(i16 %p)
ret i16 %r ret i16 %r
} }
define i128 @func128i() { define i128 @func128i() {
; CHECK-LABEL: func128i: ; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: lea.sl %s1, -16777216 ; CHECK-NEXT: lea.sl %s1, -16777216
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.bswap.i128(i128 255) %r = tail call i128 @llvm.bswap.i128(i128 255)
ret i128 %r ret i128 %r
} }
define i64 @func64i() { define i64 @func64i() {
; CHECK-LABEL: func64i: ; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -16777216 ; CHECK-NEXT: lea.sl %s0, -16777216
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.bswap.i64(i64 255) %r = tail call i64 @llvm.bswap.i64(i64 255)
ret i64 %r ret i64 %r
} }
define signext i32 @func32si() { define signext i32 @func32si() {
; CHECK-LABEL: func32si: ; CHECK-LABEL: func32si:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -16777216 ; CHECK-NEXT: lea %s0, -16777216
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bswap.i32(i32 255) %r = tail call i32 @llvm.bswap.i32(i32 255)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32zi() { define zeroext i32 @func32zi() {
; CHECK-LABEL: func32zi: ; CHECK-LABEL: func32zi:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -16777216 ; CHECK-NEXT: lea %s0, -16777216
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bswap.i32(i32 255) %r = tail call i32 @llvm.bswap.i32(i32 255)
ret i32 %r ret i32 %r
} }
define signext i16 @func16si() { define signext i16 @func16si() {
; CHECK-LABEL: func16si: ; CHECK-LABEL: func16si:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -256 ; CHECK-NEXT: lea %s0, -256
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bswap.i16(i16 255) %r = tail call i16 @llvm.bswap.i16(i16 255)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16zi() { define zeroext i16 @func16zi() {
; CHECK-LABEL: func16zi: ; CHECK-LABEL: func16zi:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 65280 ; CHECK-NEXT: lea %s0, 65280
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bswap.i16(i16 255) %r = tail call i16 @llvm.bswap.i16(i16 255)
ret i16 %r ret i16 %r
} }

llvm/test/CodeGen/VE/Scalar/callstruct.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
%struct.a = type { i32, i32 } %struct.a = type { i32, i32 }
@A = common global %struct.a zeroinitializer, align 4 @A = common global %struct.a zeroinitializer, align 4
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @fun(%struct.a* noalias nocapture sret %a, i32 %p1, i32 %p2) { define void @fun(%struct.a* noalias nocapture sret %a, i32 %p1, i32 %p2) {
; CHECK-LABEL: fun: ; CHECK-LABEL: fun:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: stl %s2, 4(, %s0) ; CHECK-NEXT: stl %s2, 4(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%a.zero = getelementptr inbounds %struct.a, %struct.a* %a, i64 0, i32 0 %a.zero = getelementptr inbounds %struct.a, %struct.a* %a, i64 0, i32 0
store i32 %p1, i32* %a.zero, align 4 store i32 %p1, i32* %a.zero, align 4
%a.one = getelementptr inbounds %struct.a, %struct.a* %a, i64 0, i32 1 %a.one = getelementptr inbounds %struct.a, %struct.a* %a, i64 0, i32 1
store i32 %p2, i32* %a.one, align 4 store i32 %p2, i32* %a.one, align 4
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @caller() { define void @caller() {
; CHECK-LABEL: caller: ; CHECK-LABEL: caller:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, callee@lo ; CHECK-NEXT: lea %s0, callee@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, callee@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, callee@hi(, %s0)
; CHECK-NEXT: lea %s0, -8(, %s9) ; CHECK-NEXT: lea %s0, 248(, %s11)
; CHECK-NEXT: or %s1, 3, (0)1 ; CHECK-NEXT: or %s1, 3, (0)1
; CHECK-NEXT: or %s2, 4, (0)1 ; CHECK-NEXT: or %s2, 4, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s0, -8(, %s9) ; CHECK-NEXT: ld %s0, 248(, %s11)
; CHECK-NEXT: lea %s1, A@lo ; CHECK-NEXT: lea %s1, A@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, A@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, A@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i64, align 8 %a = alloca i64, align 8
%a.bc = bitcast i64* %a to %struct.a* %a.bc = bitcast i64* %a to %struct.a*
call void @callee(%struct.a* nonnull sret %a.bc, i32 3, i32 4) call void @callee(%struct.a* nonnull sret %a.bc, i32 3, i32 4)
%a.val = load i64, i64* %a, align 8 %a.val = load i64, i64* %a, align 8
store i64 %a.val, i64* bitcast (%struct.a* @A to i64*), align 4 store i64 %a.val, i64* bitcast (%struct.a* @A to i64*), align 4
ret void ret void
} }
declare void @callee(%struct.a* sret, i32, i32) declare void @callee(%struct.a* sret, i32, i32)

llvm/test/CodeGen/VE/Scalar/cast.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i32 @i() { define signext i32 @i() {
; CHECK-LABEL: i: ; CHECK-LABEL: i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 -2147483648 ret i32 -2147483648
} }
define zeroext i32 @ui() { define zeroext i32 @ui() {
; CHECK-LABEL: ui: ; CHECK-LABEL: ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 -2147483648 ret i32 -2147483648
} }
define i64 @ll() { define i64 @ll() {
; CHECK-LABEL: ll: ; CHECK-LABEL: ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 -2147483648 ret i64 -2147483648
} }
define i64 @ull() { define i64 @ull() {
; CHECK-LABEL: ull: ; CHECK-LABEL: ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 2147483648 ret i64 2147483648
} }
define signext i8 @d2c(double %x) { define signext i8 @d2c(double %x) {
; CHECK-LABEL: d2c: ; CHECK-LABEL: d2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptosi double %x to i8 %r = fptosi double %x to i8
ret i8 %r ret i8 %r
} }
define zeroext i8 @d2uc(double %x) { define zeroext i8 @d2uc(double %x) {
; CHECK-LABEL: d2uc: ; CHECK-LABEL: d2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptoui double %x to i8 %r = fptoui double %x to i8
ret i8 %r ret i8 %r
} }
define signext i16 @d2s(double %x) { define signext i16 @d2s(double %x) {
; CHECK-LABEL: d2s: ; CHECK-LABEL: d2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptosi double %x to i16 %r = fptosi double %x to i16
ret i16 %r ret i16 %r
} }
define zeroext i16 @d2us(double %x) { define zeroext i16 @d2us(double %x) {
; CHECK-LABEL: d2us: ; CHECK-LABEL: d2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptoui double %x to i16 %r = fptoui double %x to i16
ret i16 %r ret i16 %r
} }
define signext i32 @d2i(double %x) { define signext i32 @d2i(double %x) {
; CHECK-LABEL: d2i: ; CHECK-LABEL: d2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptosi double %x to i32 %r = fptosi double %x to i32
ret i32 %r ret i32 %r
} }
define zeroext i32 @d2ui(double %x) { define zeroext i32 @d2ui(double %x) {
; CHECK-LABEL: d2ui: ; CHECK-LABEL: d2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptoui double %x to i32 %r = fptoui double %x to i32
ret i32 %r ret i32 %r
} }
define i64 @d2ll(double %x) { define i64 @d2ll(double %x) {
; CHECK-LABEL: d2ll: ; CHECK-LABEL: d2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptosi double %x to i64 %r = fptosi double %x to i64
ret i64 %r ret i64 %r
} }
define i64 @d2ull(double %x) { define i64 @d2ull(double %x) {
; CHECK-LABEL: d2ull: ; CHECK-LABEL: d2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1138753536 ; CHECK-NEXT: lea.sl %s1, 1138753536
; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: fsub.d %s1, %s0, %s1 ; CHECK-NEXT: fsub.d %s1, %s0, %s1
; CHECK-NEXT: cvt.l.d.rz %s1, %s1 ; CHECK-NEXT: cvt.l.d.rz %s1, %s1
; CHECK-NEXT: xor %s1, %s1, (1)1 ; CHECK-NEXT: xor %s1, %s1, (1)1
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: cmov.d.lt %s1, %s0, %s2 ; CHECK-NEXT: cmov.d.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptoui double %x to i64 %r = fptoui double %x to i64
ret i64 %r ret i64 %r
} }
define float @d2f(double %x) { define float @d2f(double %x) {
; CHECK-LABEL: d2f: ; CHECK-LABEL: d2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.s.d %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptrunc double %x to float %r = fptrunc double %x to float
ret float %r ret float %r
} }
define double @d2d(double returned %0) { define double @d2d(double returned %0) {
; CHECK-LABEL: d2d: ; CHECK-LABEL: d2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double %0 ret double %0
} }
define fp128 @d2q(double) { define fp128 @d2q(double) {
; CHECK-LABEL: d2q: ; CHECK-LABEL: d2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fpext double %0 to fp128 %2 = fpext double %0 to fp128
ret fp128 %2 ret fp128 %2
} }
define signext i8 @q2c(fp128) { define signext i8 @q2c(fp128) {
; CHECK-LABEL: q2c: ; CHECK-LABEL: q2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.d.q %s0, %s0
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptosi fp128 %0 to i8 %2 = fptosi fp128 %0 to i8
ret i8 %2 ret i8 %2
} }
define zeroext i8 @q2uc(fp128) { define zeroext i8 @q2uc(fp128) {
; CHECK-LABEL: q2uc: ; CHECK-LABEL: q2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.d.q %s0, %s0
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptoui fp128 %0 to i8 %2 = fptoui fp128 %0 to i8
ret i8 %2 ret i8 %2
} }
define signext i16 @q2s(fp128) { define signext i16 @q2s(fp128) {
; CHECK-LABEL: q2s: ; CHECK-LABEL: q2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.d.q %s0, %s0
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptosi fp128 %0 to i16 %2 = fptosi fp128 %0 to i16
ret i16 %2 ret i16 %2
} }
define zeroext i16 @q2us(fp128) { define zeroext i16 @q2us(fp128) {
; CHECK-LABEL: q2us: ; CHECK-LABEL: q2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.d.q %s0, %s0
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptoui fp128 %0 to i16 %2 = fptoui fp128 %0 to i16
ret i16 %2 ret i16 %2
} }
define signext i32 @q2i(fp128) { define signext i32 @q2i(fp128) {
; CHECK-LABEL: q2i: ; CHECK-LABEL: q2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.d.q %s0, %s0
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptosi fp128 %0 to i32 %2 = fptosi fp128 %0 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i32 @q2ui(fp128) { define zeroext i32 @q2ui(fp128) {
; CHECK-LABEL: q2ui: ; CHECK-LABEL: q2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.d.q %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptoui fp128 %0 to i32 %2 = fptoui fp128 %0 to i32
ret i32 %2 ret i32 %2
} }
define i64 @q2ll(fp128) { define i64 @q2ll(fp128) {
; CHECK-LABEL: q2ll: ; CHECK-LABEL: q2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.d.q %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptosi fp128 %0 to i64 %2 = fptosi fp128 %0 to i64
ret i64 %2 ret i64 %2
} }
define i64 @q2ull(fp128) { define i64 @q2ull(fp128) {
; CHECK-LABEL: q2ull: ; CHECK-LABEL: q2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fcmp.q %s3, %s0, %s4 ; CHECK-NEXT: fcmp.q %s3, %s0, %s4
; CHECK-NEXT: fsub.q %s4, %s0, %s4 ; CHECK-NEXT: fsub.q %s4, %s0, %s4
; CHECK-NEXT: cvt.d.q %s2, %s4 ; CHECK-NEXT: cvt.d.q %s2, %s4
; CHECK-NEXT: cvt.l.d.rz %s2, %s2 ; CHECK-NEXT: cvt.l.d.rz %s2, %s2
; CHECK-NEXT: xor %s2, %s2, (1)1 ; CHECK-NEXT: xor %s2, %s2, (1)1
; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.d.q %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: cmov.d.lt %s2, %s0, %s3 ; CHECK-NEXT: cmov.d.lt %s2, %s0, %s3
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptoui fp128 %0 to i64 %2 = fptoui fp128 %0 to i64
ret i64 %2 ret i64 %2
} }
define float @q2f(fp128) { define float @q2f(fp128) {
; CHECK-LABEL: q2f: ; CHECK-LABEL: q2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.s.q %s0, %s0 ; CHECK-NEXT: cvt.s.q %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptrunc fp128 %0 to float %2 = fptrunc fp128 %0 to float
ret float %2 ret float %2
} }
define double @q2d(fp128) { define double @q2d(fp128) {
; CHECK-LABEL: q2d: ; CHECK-LABEL: q2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.q %s0, %s0 ; CHECK-NEXT: cvt.d.q %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fptrunc fp128 %0 to double %2 = fptrunc fp128 %0 to double
ret double %2 ret double %2
} }
define fp128 @q2q(fp128 returned) { define fp128 @q2q(fp128 returned) {
; CHECK-LABEL: q2q: ; CHECK-LABEL: q2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret fp128 %0 ret fp128 %0
} }
define signext i8 @f2c(float %x) { define signext i8 @f2c(float %x) {
; CHECK-LABEL: f2c: ; CHECK-LABEL: f2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptosi float %x to i8 %r = fptosi float %x to i8
ret i8 %r ret i8 %r
} }
define zeroext i8 @f2uc(float %x) { define zeroext i8 @f2uc(float %x) {
; CHECK-LABEL: f2uc: ; CHECK-LABEL: f2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptoui float %x to i8 %r = fptoui float %x to i8
ret i8 %r ret i8 %r
} }
define signext i16 @f2s(float %x) { define signext i16 @f2s(float %x) {
; CHECK-LABEL: f2s: ; CHECK-LABEL: f2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptosi float %x to i16 %r = fptosi float %x to i16
ret i16 %r ret i16 %r
} }
define zeroext i16 @f2us(float %x) { define zeroext i16 @f2us(float %x) {
; CHECK-LABEL: f2us: ; CHECK-LABEL: f2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptoui float %x to i16 %r = fptoui float %x to i16
ret i16 %r ret i16 %r
} }
define signext i32 @f2i(float %x) { define signext i32 @f2i(float %x) {
; CHECK-LABEL: f2i: ; CHECK-LABEL: f2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptosi float %x to i32 %r = fptosi float %x to i32
ret i32 %r ret i32 %r
} }
define zeroext i32 @f2ui(float %x) { define zeroext i32 @f2ui(float %x) {
; CHECK-LABEL: f2ui: ; CHECK-LABEL: f2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptoui float %x to i32 %r = fptoui float %x to i32
ret i32 %r ret i32 %r
} }
define i64 @f2ll(float %x) { define i64 @f2ll(float %x) {
; CHECK-LABEL: f2ll: ; CHECK-LABEL: f2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptosi float %x to i64 %r = fptosi float %x to i64
ret i64 %r ret i64 %r
} }
define i64 @f2ull(float %x) { define i64 @f2ull(float %x) {
; CHECK-LABEL: f2ull: ; CHECK-LABEL: f2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1593835520 ; CHECK-NEXT: lea.sl %s1, 1593835520
; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: fsub.s %s1, %s0, %s1 ; CHECK-NEXT: fsub.s %s1, %s0, %s1
; CHECK-NEXT: cvt.d.s %s1, %s1 ; CHECK-NEXT: cvt.d.s %s1, %s1
; CHECK-NEXT: cvt.l.d.rz %s1, %s1 ; CHECK-NEXT: cvt.l.d.rz %s1, %s1
; CHECK-NEXT: xor %s1, %s1, (1)1 ; CHECK-NEXT: xor %s1, %s1, (1)1
; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: cmov.s.lt %s1, %s0, %s2 ; CHECK-NEXT: cmov.s.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fptoui float %x to i64 %r = fptoui float %x to i64
ret i64 %r ret i64 %r
} }
define float @f2f(float returned %0) { define float @f2f(float returned %0) {
; CHECK-LABEL: f2f: ; CHECK-LABEL: f2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float %0 ret float %0
} }
define double @f2d(float %x) { define double @f2d(float %x) {
; CHECK-LABEL: f2d: ; CHECK-LABEL: f2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fpext float %x to double %r = fpext float %x to double
ret double %r ret double %r
} }
define fp128 @f2q(float) { define fp128 @f2q(float) {
; CHECK-LABEL: f2q: ; CHECK-LABEL: f2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.q.s %s0, %s0 ; CHECK-NEXT: cvt.q.s %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fpext float %0 to fp128 %2 = fpext float %0 to fp128
ret fp128 %2 ret fp128 %2
} }
define signext i8 @ll2c(i64 %0) { define signext i8 @ll2c(i64 %0) {
; CHECK-LABEL: ll2c: ; CHECK-LABEL: ll2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i8 %2 = trunc i64 %0 to i8
ret i8 %2 ret i8 %2
} }
define zeroext i8 @ll2uc(i64 %0) { define zeroext i8 @ll2uc(i64 %0) {
; CHECK-LABEL: ll2uc: ; CHECK-LABEL: ll2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i8 %2 = trunc i64 %0 to i8
ret i8 %2 ret i8 %2
} }
define signext i16 @ll2s(i64 %0) { define signext i16 @ll2s(i64 %0) {
; CHECK-LABEL: ll2s: ; CHECK-LABEL: ll2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i16 %2 = trunc i64 %0 to i16
ret i16 %2 ret i16 %2
} }
define zeroext i16 @ll2us(i64 %0) { define zeroext i16 @ll2us(i64 %0) {
; CHECK-LABEL: ll2us: ; CHECK-LABEL: ll2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i16 %2 = trunc i64 %0 to i16
ret i16 %2 ret i16 %2
} }
define signext i32 @ll2i(i64 %0) { define signext i32 @ll2i(i64 %0) {
; CHECK-LABEL: ll2i: ; CHECK-LABEL: ll2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i32 %2 = trunc i64 %0 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i32 @ll2ui(i64 %0) { define zeroext i32 @ll2ui(i64 %0) {
; CHECK-LABEL: ll2ui: ; CHECK-LABEL: ll2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i32 %2 = trunc i64 %0 to i32
ret i32 %2 ret i32 %2
} }
define i64 @ll2ll(i64 returned %0) { define i64 @ll2ll(i64 returned %0) {
; CHECK-LABEL: ll2ll: ; CHECK-LABEL: ll2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 %0 ret i64 %0
} }
define i64 @ll2ull(i64 returned %0) { define i64 @ll2ull(i64 returned %0) {
; CHECK-LABEL: ll2ull: ; CHECK-LABEL: ll2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 %0 ret i64 %0
} }
define float @ll2f(i64 %x) { define float @ll2f(i64 %x) {
; CHECK-LABEL: ll2f: ; CHECK-LABEL: ll2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sitofp i64 %x to float %r = sitofp i64 %x to float
ret float %r ret float %r
} }
define double @ll2d(i64 %x) { define double @ll2d(i64 %x) {
; CHECK-LABEL: ll2d: ; CHECK-LABEL: ll2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sitofp i64 %x to double %r = sitofp i64 %x to double
ret double %r ret double %r
} }
define fp128 @ll2q(i64) { define fp128 @ll2q(i64) {
; CHECK-LABEL: ll2q: ; CHECK-LABEL: ll2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sitofp i64 %0 to fp128 %2 = sitofp i64 %0 to fp128
ret fp128 %2 ret fp128 %2
} }
define signext i8 @ull2c(i64 %0) { define signext i8 @ull2c(i64 %0) {
; CHECK-LABEL: ull2c: ; CHECK-LABEL: ull2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i8 %2 = trunc i64 %0 to i8
ret i8 %2 ret i8 %2
} }
define zeroext i8 @ull2uc(i64 %0) { define zeroext i8 @ull2uc(i64 %0) {
; CHECK-LABEL: ull2uc: ; CHECK-LABEL: ull2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i8 %2 = trunc i64 %0 to i8
ret i8 %2 ret i8 %2
} }
define signext i16 @ull2s(i64 %0) { define signext i16 @ull2s(i64 %0) {
; CHECK-LABEL: ull2s: ; CHECK-LABEL: ull2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i16 %2 = trunc i64 %0 to i16
ret i16 %2 ret i16 %2
} }
define zeroext i16 @ull2us(i64 %0) { define zeroext i16 @ull2us(i64 %0) {
; CHECK-LABEL: ull2us: ; CHECK-LABEL: ull2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i16 %2 = trunc i64 %0 to i16
ret i16 %2 ret i16 %2
} }
define signext i32 @ull2i(i64 %0) { define signext i32 @ull2i(i64 %0) {
; CHECK-LABEL: ull2i: ; CHECK-LABEL: ull2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i32 %2 = trunc i64 %0 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i32 @ull2ui(i64 %0) { define zeroext i32 @ull2ui(i64 %0) {
; CHECK-LABEL: ull2ui: ; CHECK-LABEL: ull2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i64 %0 to i32 %2 = trunc i64 %0 to i32
ret i32 %2 ret i32 %2
} }
define i64 @ull2ll(i64 returned %0) { define i64 @ull2ll(i64 returned %0) {
; CHECK-LABEL: ull2ll: ; CHECK-LABEL: ull2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 %0 ret i64 %0
} }
define i64 @ull2ull(i64 returned %0) { define i64 @ull2ull(i64 returned %0) {
; CHECK-LABEL: ull2ull: ; CHECK-LABEL: ull2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 %0 ret i64 %0
} }
define float @ull2f(i64 %x) { define float @ull2f(i64 %x) {
; CHECK-LABEL: ull2f: ; CHECK-LABEL: ull2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s2, %s0, (0)1 ; CHECK-NEXT: cmps.l %s2, %s0, (0)1
; CHECK-NEXT: cvt.d.l %s1, %s0 ; CHECK-NEXT: cvt.d.l %s1, %s0
; CHECK-NEXT: cvt.s.d %s1, %s1 ; CHECK-NEXT: cvt.s.d %s1, %s1
; CHECK-NEXT: srl %s3, %s0, 1 ; CHECK-NEXT: srl %s3, %s0, 1
; CHECK-NEXT: and %s0, 1, %s0 ; CHECK-NEXT: and %s0, 1, %s0
; CHECK-NEXT: or %s0, %s0, %s3 ; CHECK-NEXT: or %s0, %s0, %s3
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: fadd.s %s0, %s0, %s0 ; CHECK-NEXT: fadd.s %s0, %s0, %s0
; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 ; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = uitofp i64 %x to float %r = uitofp i64 %x to float
ret float %r ret float %r
} }
define double @ull2d(i64 %x) { define double @ull2d(i64 %x) {
; CHECK-LABEL: ull2d: ; CHECK-LABEL: ull2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %s1, %s0, 32 ; CHECK-NEXT: srl %s1, %s0, 32
; CHECK-NEXT: lea.sl %s2, 1160773632 ; CHECK-NEXT: lea.sl %s2, 1160773632
; CHECK-NEXT: or %s1, %s1, %s2 ; CHECK-NEXT: or %s1, %s1, %s2
; CHECK-NEXT: lea %s2, 1048576 ; CHECK-NEXT: lea %s2, 1048576
; CHECK-NEXT: lea.sl %s2, -986710016(, %s2) ; CHECK-NEXT: lea.sl %s2, -986710016(, %s2)
; CHECK-NEXT: fadd.d %s1, %s1, %s2 ; CHECK-NEXT: fadd.d %s1, %s1, %s2
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, 1127219200 ; CHECK-NEXT: lea.sl %s2, 1127219200
; CHECK-NEXT: or %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: fadd.d %s0, %s0, %s1 ; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = uitofp i64 %x to double %r = uitofp i64 %x to double
ret double %r ret double %r
} }
define fp128 @ull2q(i64) { define fp128 @ull2q(i64) {
; CHECK-LABEL: ull2q: ; CHECK-LABEL: ull2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %s1, %s0, 61 ; CHECK-NEXT: srl %s1, %s0, 61
; CHECK-NEXT: and %s1, 4, %s1 ; CHECK-NEXT: and %s1, 4, %s1
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ldu %s1, (%s1, %s2) ; CHECK-NEXT: ldu %s1, (%s1, %s2)
; CHECK-NEXT: cvt.q.s %s2, %s1 ; CHECK-NEXT: cvt.q.s %s2, %s1
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0
; CHECK-NEXT: fadd.q %s0, %s0, %s2 ; CHECK-NEXT: fadd.q %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = uitofp i64 %0 to fp128 %2 = uitofp i64 %0 to fp128
ret fp128 %2 ret fp128 %2
} }
define signext i8 @i2c(i32 signext %0) { define signext i8 @i2c(i32 signext %0) {
; CHECK-LABEL: i2c: ; CHECK-LABEL: i2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i32 %0 to i8 %2 = trunc i32 %0 to i8
ret i8 %2 ret i8 %2
} }
define zeroext i8 @i2uc(i32 signext %0) { define zeroext i8 @i2uc(i32 signext %0) {
; CHECK-LABEL: i2uc: ; CHECK-LABEL: i2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i32 %0 to i8 %2 = trunc i32 %0 to i8
ret i8 %2 ret i8 %2
} }
define signext i16 @i2s(i32 signext %0) { define signext i16 @i2s(i32 signext %0) {
; CHECK-LABEL: i2s: ; CHECK-LABEL: i2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i32 %0 to i16 %2 = trunc i32 %0 to i16
ret i16 %2 ret i16 %2
} }
define zeroext i16 @i2us(i32 signext %0) { define zeroext i16 @i2us(i32 signext %0) {
; CHECK-LABEL: i2us: ; CHECK-LABEL: i2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i32 %0 to i16 %2 = trunc i32 %0 to i16
ret i16 %2 ret i16 %2
} }
define signext i32 @i2i(i32 signext returned %0) { define signext i32 @i2i(i32 signext returned %0) {
; CHECK-LABEL: i2i: ; CHECK-LABEL: i2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 %0 ret i32 %0
} }
define zeroext i32 @i2ui(i32 signext returned %0) { define zeroext i32 @i2ui(i32 signext returned %0) {
; CHECK-LABEL: i2ui: ; CHECK-LABEL: i2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 %0 ret i32 %0
} }
define i64 @i2ll(i32 signext %0) { define i64 @i2ll(i32 signext %0) {
; CHECK-LABEL: i2ll: ; CHECK-LABEL: i2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i32 %0 to i64 %2 = sext i32 %0 to i64
ret i64 %2 ret i64 %2
} }
define i64 @i2ull(i32 signext %0) { define i64 @i2ull(i32 signext %0) {
; CHECK-LABEL: i2ull: ; CHECK-LABEL: i2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i32 %0 to i64 %2 = sext i32 %0 to i64
ret i64 %2 ret i64 %2
} }
define float @i2f(i32 signext %x) { define float @i2f(i32 signext %x) {
; CHECK-LABEL: i2f: ; CHECK-LABEL: i2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sitofp i32 %x to float %r = sitofp i32 %x to float
ret float %r ret float %r
} }
define double @i2d(i32 signext %x) { define double @i2d(i32 signext %x) {
; CHECK-LABEL: i2d: ; CHECK-LABEL: i2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sitofp i32 %x to double %r = sitofp i32 %x to double
ret double %r ret double %r
} }
define fp128 @i2q(i32 signext %x) { define fp128 @i2q(i32 signext %x) {
; CHECK-LABEL: i2q: ; CHECK-LABEL: i2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sitofp i32 %x to fp128 %r = sitofp i32 %x to fp128
ret fp128 %r ret fp128 %r
} }
define signext i8 @ui2c(i32 zeroext %0) { define signext i8 @ui2c(i32 zeroext %0) {
; CHECK-LABEL: ui2c: ; CHECK-LABEL: ui2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i32 %0 to i8 %2 = trunc i32 %0 to i8
ret i8 %2 ret i8 %2
} }
define zeroext i8 @ui2uc(i32 zeroext %0) { define zeroext i8 @ui2uc(i32 zeroext %0) {
; CHECK-LABEL: ui2uc: ; CHECK-LABEL: ui2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i32 %0 to i8 %2 = trunc i32 %0 to i8
ret i8 %2 ret i8 %2
} }
define signext i16 @ui2s(i32 zeroext %0) { define signext i16 @ui2s(i32 zeroext %0) {
; CHECK-LABEL: ui2s: ; CHECK-LABEL: ui2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i32 %0 to i16 %2 = trunc i32 %0 to i16
ret i16 %2 ret i16 %2
} }
define zeroext i16 @ui2us(i32 zeroext %0) { define zeroext i16 @ui2us(i32 zeroext %0) {
; CHECK-LABEL: ui2us: ; CHECK-LABEL: ui2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i32 %0 to i16 %2 = trunc i32 %0 to i16
ret i16 %2 ret i16 %2
} }
define signext i32 @ui2i(i32 zeroext returned %0) { define signext i32 @ui2i(i32 zeroext returned %0) {
; CHECK-LABEL: ui2i: ; CHECK-LABEL: ui2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 %0 ret i32 %0
} }
define zeroext i32 @ui2ui(i32 zeroext returned %0) { define zeroext i32 @ui2ui(i32 zeroext returned %0) {
; CHECK-LABEL: ui2ui: ; CHECK-LABEL: ui2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 %0 ret i32 %0
} }
define i64 @ui2ll(i32 zeroext %0) { define i64 @ui2ll(i32 zeroext %0) {
; CHECK-LABEL: ui2ll: ; CHECK-LABEL: ui2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i32 %0 to i64 %2 = zext i32 %0 to i64
ret i64 %2 ret i64 %2
} }
define i64 @ui2ull(i32 zeroext %0) { define i64 @ui2ull(i32 zeroext %0) {
; CHECK-LABEL: ui2ull: ; CHECK-LABEL: ui2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i32 %0 to i64 %2 = zext i32 %0 to i64
ret i64 %2 ret i64 %2
} }
define float @ui2f(i32 zeroext %x) { define float @ui2f(i32 zeroext %x) {
; CHECK-LABEL: ui2f: ; CHECK-LABEL: ui2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = uitofp i32 %x to float %r = uitofp i32 %x to float
ret float %r ret float %r
} }
define double @ui2d(i32 zeroext %x) { define double @ui2d(i32 zeroext %x) {
; CHECK-LABEL: ui2d: ; CHECK-LABEL: ui2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = uitofp i32 %x to double %r = uitofp i32 %x to double
ret double %r ret double %r
} }
define fp128 @ui2q(i32 zeroext %0) { define fp128 @ui2q(i32 zeroext %0) {
; CHECK-LABEL: ui2q: ; CHECK-LABEL: ui2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = uitofp i32 %0 to fp128 %2 = uitofp i32 %0 to fp128
ret fp128 %2 ret fp128 %2
} }
define signext i8 @s2c(i16 signext %0) { define signext i8 @s2c(i16 signext %0) {
; CHECK-LABEL: s2c: ; CHECK-LABEL: s2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i16 %0 to i8 %2 = trunc i16 %0 to i8
ret i8 %2 ret i8 %2
} }
define zeroext i8 @s2uc(i16 signext %0) { define zeroext i8 @s2uc(i16 signext %0) {
; CHECK-LABEL: s2uc: ; CHECK-LABEL: s2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i16 %0 to i8 %2 = trunc i16 %0 to i8
ret i8 %2 ret i8 %2
} }
define signext i16 @s2s(i16 returned signext %0) { define signext i16 @s2s(i16 returned signext %0) {
; CHECK-LABEL: s2s: ; CHECK-LABEL: s2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i16 %0 ret i16 %0
} }
define zeroext i16 @s2us(i16 returned signext %0) { define zeroext i16 @s2us(i16 returned signext %0) {
; CHECK-LABEL: s2us: ; CHECK-LABEL: s2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i16 %0 ret i16 %0
} }
define signext i32 @s2i(i16 signext %0) { define signext i32 @s2i(i16 signext %0) {
; CHECK-LABEL: s2i: ; CHECK-LABEL: s2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i16 %0 to i32 %2 = sext i16 %0 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i32 @s2ui(i16 signext %0) { define zeroext i32 @s2ui(i16 signext %0) {
; CHECK-LABEL: s2ui: ; CHECK-LABEL: s2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i16 %0 to i32 %2 = sext i16 %0 to i32
ret i32 %2 ret i32 %2
} }
define i64 @s2ll(i16 signext %0) { define i64 @s2ll(i16 signext %0) {
; CHECK-LABEL: s2ll: ; CHECK-LABEL: s2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i16 %0 to i64 %2 = sext i16 %0 to i64
ret i64 %2 ret i64 %2
} }
define i64 @s2ull(i16 signext %0) { define i64 @s2ull(i16 signext %0) {
; CHECK-LABEL: s2ull: ; CHECK-LABEL: s2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i16 %0 to i64 %2 = sext i16 %0 to i64
ret i64 %2 ret i64 %2
} }
define float @s2f(i16 signext %x) { define float @s2f(i16 signext %x) {
; CHECK-LABEL: s2f: ; CHECK-LABEL: s2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sitofp i16 %x to float %r = sitofp i16 %x to float
ret float %r ret float %r
} }
define double @s2d(i16 signext %x) { define double @s2d(i16 signext %x) {
; CHECK-LABEL: s2d: ; CHECK-LABEL: s2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sitofp i16 %x to double %r = sitofp i16 %x to double
ret double %r ret double %r
} }
define fp128 @s2q(i16 signext) { define fp128 @s2q(i16 signext) {
; CHECK-LABEL: s2q: ; CHECK-LABEL: s2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sitofp i16 %0 to fp128 %2 = sitofp i16 %0 to fp128
ret fp128 %2 ret fp128 %2
} }
define signext i8 @us2c(i16 zeroext %0) { define signext i8 @us2c(i16 zeroext %0) {
; CHECK-LABEL: us2c: ; CHECK-LABEL: us2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i16 %0 to i8 %2 = trunc i16 %0 to i8
ret i8 %2 ret i8 %2
} }
define zeroext i8 @us2uc(i16 zeroext %0) { define zeroext i8 @us2uc(i16 zeroext %0) {
; CHECK-LABEL: us2uc: ; CHECK-LABEL: us2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i16 %0 to i8 %2 = trunc i16 %0 to i8
ret i8 %2 ret i8 %2
} }
define signext i16 @us2s(i16 returned zeroext %0) { define signext i16 @us2s(i16 returned zeroext %0) {
; CHECK-LABEL: us2s: ; CHECK-LABEL: us2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i16 %0 ret i16 %0
} }
define zeroext i16 @us2us(i16 returned zeroext %0) { define zeroext i16 @us2us(i16 returned zeroext %0) {
; CHECK-LABEL: us2us: ; CHECK-LABEL: us2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i16 %0 ret i16 %0
} }
define signext i32 @us2i(i16 zeroext %0) { define signext i32 @us2i(i16 zeroext %0) {
; CHECK-LABEL: us2i: ; CHECK-LABEL: us2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32 %2 = zext i16 %0 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i32 @us2ui(i16 zeroext %0) { define zeroext i32 @us2ui(i16 zeroext %0) {
; CHECK-LABEL: us2ui: ; CHECK-LABEL: us2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32 %2 = zext i16 %0 to i32
ret i32 %2 ret i32 %2
} }
define i64 @us2ll(i16 zeroext %0) { define i64 @us2ll(i16 zeroext %0) {
; CHECK-LABEL: us2ll: ; CHECK-LABEL: us2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i64 %2 = zext i16 %0 to i64
ret i64 %2 ret i64 %2
} }
define i64 @us2ull(i16 zeroext %0) { define i64 @us2ull(i16 zeroext %0) {
; CHECK-LABEL: us2ull: ; CHECK-LABEL: us2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i64 %2 = zext i16 %0 to i64
ret i64 %2 ret i64 %2
} }
define float @us2f(i16 zeroext %x) { define float @us2f(i16 zeroext %x) {
; CHECK-LABEL: us2f: ; CHECK-LABEL: us2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = uitofp i16 %x to float %r = uitofp i16 %x to float
ret float %r ret float %r
} }
define double @us2d(i16 zeroext %x) { define double @us2d(i16 zeroext %x) {
; CHECK-LABEL: us2d: ; CHECK-LABEL: us2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = uitofp i16 %x to double %r = uitofp i16 %x to double
ret double %r ret double %r
} }
define fp128 @us2q(i16 zeroext) { define fp128 @us2q(i16 zeroext) {
; CHECK-LABEL: us2q: ; CHECK-LABEL: us2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = uitofp i16 %0 to fp128 %2 = uitofp i16 %0 to fp128
ret fp128 %2 ret fp128 %2
} }
define signext i8 @c2c(i8 returned signext %0) { define signext i8 @c2c(i8 returned signext %0) {
; CHECK-LABEL: c2c: ; CHECK-LABEL: c2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 %0 ret i8 %0
} }
define zeroext i8 @c2uc(i8 returned signext %0) { define zeroext i8 @c2uc(i8 returned signext %0) {
; CHECK-LABEL: c2uc: ; CHECK-LABEL: c2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 %0 ret i8 %0
} }
define signext i16 @c2s(i8 signext %0) { define signext i16 @c2s(i8 signext %0) {
; CHECK-LABEL: c2s: ; CHECK-LABEL: c2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i8 %0 to i16 %2 = sext i8 %0 to i16
ret i16 %2 ret i16 %2
} }
define zeroext i16 @c2us(i8 signext %0) { define zeroext i16 @c2us(i8 signext %0) {
; CHECK-LABEL: c2us: ; CHECK-LABEL: c2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i8 %0 to i16 %2 = sext i8 %0 to i16
ret i16 %2 ret i16 %2
} }
define signext i32 @c2i(i8 signext %0) { define signext i32 @c2i(i8 signext %0) {
; CHECK-LABEL: c2i: ; CHECK-LABEL: c2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i8 %0 to i32 %2 = sext i8 %0 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i32 @c2ui(i8 signext %0) { define zeroext i32 @c2ui(i8 signext %0) {
; CHECK-LABEL: c2ui: ; CHECK-LABEL: c2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i8 %0 to i32 %2 = sext i8 %0 to i32
ret i32 %2 ret i32 %2
} }
define i64 @c2ll(i8 signext %0) { define i64 @c2ll(i8 signext %0) {
; CHECK-LABEL: c2ll: ; CHECK-LABEL: c2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i8 %0 to i64 %2 = sext i8 %0 to i64
ret i64 %2 ret i64 %2
} }
define i64 @c2ull(i8 signext %0) { define i64 @c2ull(i8 signext %0) {
; CHECK-LABEL: c2ull: ; CHECK-LABEL: c2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i8 %0 to i64 %2 = sext i8 %0 to i64
ret i64 %2 ret i64 %2
} }
define float @c2f(i8 signext %x) { define float @c2f(i8 signext %x) {
; CHECK-LABEL: c2f: ; CHECK-LABEL: c2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sitofp i8 %x to float %r = sitofp i8 %x to float
ret float %r ret float %r
} }
define double @c2d(i8 signext %x) { define double @c2d(i8 signext %x) {
; CHECK-LABEL: c2d: ; CHECK-LABEL: c2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sitofp i8 %x to double %r = sitofp i8 %x to double
ret double %r ret double %r
} }
define fp128 @c2q(i8 signext) { define fp128 @c2q(i8 signext) {
; CHECK-LABEL: c2q: ; CHECK-LABEL: c2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sitofp i8 %0 to fp128 %2 = sitofp i8 %0 to fp128
ret fp128 %2 ret fp128 %2
} }
define signext i8 @uc2c(i8 returned zeroext %0) { define signext i8 @uc2c(i8 returned zeroext %0) {
; CHECK-LABEL: uc2c: ; CHECK-LABEL: uc2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 %0 ret i8 %0
} }
define zeroext i8 @uc2uc(i8 returned zeroext %0) { define zeroext i8 @uc2uc(i8 returned zeroext %0) {
; CHECK-LABEL: uc2uc: ; CHECK-LABEL: uc2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 %0 ret i8 %0
} }
define signext i16 @uc2s(i8 zeroext %0) { define signext i16 @uc2s(i8 zeroext %0) {
; CHECK-LABEL: uc2s: ; CHECK-LABEL: uc2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i16 %2 = zext i8 %0 to i16
ret i16 %2 ret i16 %2
} }
define zeroext i16 @uc2us(i8 zeroext %0) { define zeroext i16 @uc2us(i8 zeroext %0) {
; CHECK-LABEL: uc2us: ; CHECK-LABEL: uc2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i16 %2 = zext i8 %0 to i16
ret i16 %2 ret i16 %2
} }
define signext i32 @uc2i(i8 zeroext %0) { define signext i32 @uc2i(i8 zeroext %0) {
; CHECK-LABEL: uc2i: ; CHECK-LABEL: uc2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32 %2 = zext i8 %0 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i32 @uc2ui(i8 zeroext %0) { define zeroext i32 @uc2ui(i8 zeroext %0) {
; CHECK-LABEL: uc2ui: ; CHECK-LABEL: uc2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32 %2 = zext i8 %0 to i32
ret i32 %2 ret i32 %2
} }
define i64 @uc2ll(i8 zeroext %0) { define i64 @uc2ll(i8 zeroext %0) {
; CHECK-LABEL: uc2ll: ; CHECK-LABEL: uc2ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i64 %2 = zext i8 %0 to i64
ret i64 %2 ret i64 %2
} }
define i64 @uc2ull(i8 zeroext %0) { define i64 @uc2ull(i8 zeroext %0) {
; CHECK-LABEL: uc2ull: ; CHECK-LABEL: uc2ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i64 %2 = zext i8 %0 to i64
ret i64 %2 ret i64 %2
} }
define float @uc2f(i8 zeroext %x) { define float @uc2f(i8 zeroext %x) {
; CHECK-LABEL: uc2f: ; CHECK-LABEL: uc2f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = uitofp i8 %x to float %r = uitofp i8 %x to float
ret float %r ret float %r
} }
define double @uc2d(i8 zeroext %x) { define double @uc2d(i8 zeroext %x) {
; CHECK-LABEL: uc2d: ; CHECK-LABEL: uc2d:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = uitofp i8 %x to double %r = uitofp i8 %x to double
ret double %r ret double %r
} }
define fp128 @uc2q(i8 zeroext) { define fp128 @uc2q(i8 zeroext) {
; CHECK-LABEL: uc2q: ; CHECK-LABEL: uc2q:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: cvt.q.d %s0, %s0 ; CHECK-NEXT: cvt.q.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = uitofp i8 %0 to fp128 %2 = uitofp i8 %0 to fp128
ret fp128 %2 ret fp128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @i128() { define i128 @i128() {
; CHECK-LABEL: i128: ; CHECK-LABEL: i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: or %s1, -1, (0)1 ; CHECK-NEXT: or %s1, -1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i128 -2147483648 ret i128 -2147483648
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @ui128() { define i128 @ui128() {
; CHECK-LABEL: ui128: ; CHECK-LABEL: ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: or %s1, -1, (0)1 ; CHECK-NEXT: or %s1, -1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i128 -2147483648 ret i128 -2147483648
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @i1282c(i128 %0) { define signext i8 @i1282c(i128 %0) {
; CHECK-LABEL: i1282c: ; CHECK-LABEL: i1282c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i8 %2 = trunc i128 %0 to i8
ret i8 %2 ret i8 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @ui1282c(i128 %0) { define signext i8 @ui1282c(i128 %0) {
; CHECK-LABEL: ui1282c: ; CHECK-LABEL: ui1282c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i8 %2 = trunc i128 %0 to i8
ret i8 %2 ret i8 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @i1282uc(i128 %0) { define zeroext i8 @i1282uc(i128 %0) {
; CHECK-LABEL: i1282uc: ; CHECK-LABEL: i1282uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i8 %2 = trunc i128 %0 to i8
ret i8 %2 ret i8 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @ui1282uc(i128 %0) { define zeroext i8 @ui1282uc(i128 %0) {
; CHECK-LABEL: ui1282uc: ; CHECK-LABEL: ui1282uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i8 %2 = trunc i128 %0 to i8
ret i8 %2 ret i8 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @i1282s(i128 %0) { define signext i16 @i1282s(i128 %0) {
; CHECK-LABEL: i1282s: ; CHECK-LABEL: i1282s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i16 %2 = trunc i128 %0 to i16
ret i16 %2 ret i16 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @ui1282s(i128 %0) { define signext i16 @ui1282s(i128 %0) {
; CHECK-LABEL: ui1282s: ; CHECK-LABEL: ui1282s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i16 %2 = trunc i128 %0 to i16
ret i16 %2 ret i16 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @i1282us(i128 %0) { define zeroext i16 @i1282us(i128 %0) {
; CHECK-LABEL: i1282us: ; CHECK-LABEL: i1282us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i16 %2 = trunc i128 %0 to i16
ret i16 %2 ret i16 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @ui1282us(i128 %0) { define zeroext i16 @ui1282us(i128 %0) {
; CHECK-LABEL: ui1282us: ; CHECK-LABEL: ui1282us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i16 %2 = trunc i128 %0 to i16
ret i16 %2 ret i16 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @i1282i(i128 %0) { define signext i32 @i1282i(i128 %0) {
; CHECK-LABEL: i1282i: ; CHECK-LABEL: i1282i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i32 %2 = trunc i128 %0 to i32
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @ui1282i(i128 %0) { define signext i32 @ui1282i(i128 %0) {
; CHECK-LABEL: ui1282i: ; CHECK-LABEL: ui1282i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i32 %2 = trunc i128 %0 to i32
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @i1282ui(i128 %0) { define zeroext i32 @i1282ui(i128 %0) {
; CHECK-LABEL: i1282ui: ; CHECK-LABEL: i1282ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i32 %2 = trunc i128 %0 to i32
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @ui1282ui(i128 %0) { define zeroext i32 @ui1282ui(i128 %0) {
; CHECK-LABEL: ui1282ui: ; CHECK-LABEL: ui1282ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i32 %2 = trunc i128 %0 to i32
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @i1282ll(i128 %0) { define i64 @i1282ll(i128 %0) {
; CHECK-LABEL: i1282ll: ; CHECK-LABEL: i1282ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i64 %2 = trunc i128 %0 to i64
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @ui1282ll(i128 %0) { define i64 @ui1282ll(i128 %0) {
; CHECK-LABEL: ui1282ll: ; CHECK-LABEL: ui1282ll:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i64 %2 = trunc i128 %0 to i64
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @i1282ull(i128 %0) { define i64 @i1282ull(i128 %0) {
; CHECK-LABEL: i1282ull: ; CHECK-LABEL: i1282ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i64 %2 = trunc i128 %0 to i64
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @ui1282ull(i128 %0) { define i64 @ui1282ull(i128 %0) {
; CHECK-LABEL: ui1282ull: ; CHECK-LABEL: ui1282ull:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = trunc i128 %0 to i64 %2 = trunc i128 %0 to i64
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @i1282ui128(i128 returned %0) { define i128 @i1282ui128(i128 returned %0) {
; CHECK-LABEL: i1282ui128: ; CHECK-LABEL: i1282ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i128 %0 ret i128 %0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @ui1282i128(i128 returned %0) { define i128 @ui1282i128(i128 returned %0) {
; CHECK-LABEL: ui1282i128: ; CHECK-LABEL: ui1282i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i128 %0 ret i128 %0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @i1282f(i128) { define float @i1282f(i128) {
; CHECK-LABEL: i1282f: ; CHECK-LABEL: i1282f:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __floattisf@lo ; CHECK-NEXT: lea %s2, __floattisf@lo
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = fptoui float %0 to i128 %2 = fptoui float %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @ll2i128(i64 %0) { define i128 @ll2i128(i64 %0) {
; CHECK-LABEL: ll2i128: ; CHECK-LABEL: ll2i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s0, 63 ; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i64 %0 to i128 %2 = sext i64 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @ll2ui128(i64 %0) { define i128 @ll2ui128(i64 %0) {
; CHECK-LABEL: ll2ui128: ; CHECK-LABEL: ll2ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s0, 63 ; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i64 %0 to i128 %2 = sext i64 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @ull2i128(i64 %0) { define i128 @ull2i128(i64 %0) {
; CHECK-LABEL: ull2i128: ; CHECK-LABEL: ull2i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i64 %0 to i128 %2 = zext i64 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @ull2ui128(i64 %0) { define i128 @ull2ui128(i64 %0) {
; CHECK-LABEL: ull2ui128: ; CHECK-LABEL: ull2ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i64 %0 to i128 %2 = zext i64 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @i2i128(i32 signext %0) { define i128 @i2i128(i32 signext %0) {
; CHECK-LABEL: i2i128: ; CHECK-LABEL: i2i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s0, 63 ; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i32 %0 to i128 %2 = sext i32 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @i2ui128(i32 signext %0) { define i128 @i2ui128(i32 signext %0) {
; CHECK-LABEL: i2ui128: ; CHECK-LABEL: i2ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s0, 63 ; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i32 %0 to i128 %2 = sext i32 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @ui2i128(i32 zeroext %0) { define i128 @ui2i128(i32 zeroext %0) {
; CHECK-LABEL: ui2i128: ; CHECK-LABEL: ui2i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i32 %0 to i128 %2 = zext i32 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @ui2ui128(i32 zeroext %0) { define i128 @ui2ui128(i32 zeroext %0) {
; CHECK-LABEL: ui2ui128: ; CHECK-LABEL: ui2ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i32 %0 to i128 %2 = zext i32 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @s2i128(i16 signext %0) { define i128 @s2i128(i16 signext %0) {
; CHECK-LABEL: s2i128: ; CHECK-LABEL: s2i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s0, 63 ; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i16 %0 to i128 %2 = sext i16 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @s2ui128(i16 signext %0) { define i128 @s2ui128(i16 signext %0) {
; CHECK-LABEL: s2ui128: ; CHECK-LABEL: s2ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s0, 63 ; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i16 %0 to i128 %2 = sext i16 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @us2i128(i16 zeroext %0) { define i128 @us2i128(i16 zeroext %0) {
; CHECK-LABEL: us2i128: ; CHECK-LABEL: us2i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i128 %2 = zext i16 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @us2ui128(i16 zeroext %0) { define i128 @us2ui128(i16 zeroext %0) {
; CHECK-LABEL: us2ui128: ; CHECK-LABEL: us2ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i128 %2 = zext i16 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @c2i128(i8 signext %0) { define i128 @c2i128(i8 signext %0) {
; CHECK-LABEL: c2i128: ; CHECK-LABEL: c2i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s0, 63 ; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i8 %0 to i128 %2 = sext i8 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @char2ui128(i8 signext %0) { define i128 @char2ui128(i8 signext %0) {
; CHECK-LABEL: char2ui128: ; CHECK-LABEL: char2ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s0, 63 ; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = sext i8 %0 to i128 %2 = sext i8 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @uc2i128(i8 zeroext %0) { define i128 @uc2i128(i8 zeroext %0) {
; CHECK-LABEL: uc2i128: ; CHECK-LABEL: uc2i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i128 %2 = zext i8 %0 to i128
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @uc2ui128(i8 zeroext %0) { define i128 @uc2ui128(i8 zeroext %0) {
; CHECK-LABEL: uc2ui128: ; CHECK-LABEL: uc2ui128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i128 %2 = zext i8 %0 to i128
ret i128 %2 ret i128 %2
} }

llvm/test/CodeGen/VE/Scalar/constants.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define i8 @p0i8() { define i8 @p0i8() {
; CHECK-LABEL: p0i8: ; CHECK-LABEL: p0i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 0 ret i8 0
} }
define signext i8 @p0si8() { define signext i8 @p0si8() {
; CHECK-LABEL: p0si8: ; CHECK-LABEL: p0si8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 0 ret i8 0
} }
define zeroext i8 @p0zi8() { define zeroext i8 @p0zi8() {
; CHECK-LABEL: p0zi8: ; CHECK-LABEL: p0zi8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 0 ret i8 0
} }
define i8 @p128i8() { define i8 @p128i8() {
; CHECK-LABEL: p128i8: ; CHECK-LABEL: p128i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128 ; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 128 ret i8 128
} }
define signext i8 @p128si8() { define signext i8 @p128si8() {
; CHECK-LABEL: p128si8: ; CHECK-LABEL: p128si8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -128 ; CHECK-NEXT: lea %s0, -128
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 128 ret i8 128
} }
define zeroext i8 @p128zi8() { define zeroext i8 @p128zi8() {
; CHECK-LABEL: p128zi8: ; CHECK-LABEL: p128zi8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128 ; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 128 ret i8 128
} }
define i8 @p256i8() { define i8 @p256i8() {
; CHECK-LABEL: p256i8: ; CHECK-LABEL: p256i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 256 ret i8 256
} }
define signext i8 @p256si8() { define signext i8 @p256si8() {
; CHECK-LABEL: p256si8: ; CHECK-LABEL: p256si8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 256 ret i8 256
} }
define zeroext i8 @p256zi8() { define zeroext i8 @p256zi8() {
; CHECK-LABEL: p256zi8: ; CHECK-LABEL: p256zi8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i8 256 ret i8 256
} }
define i16 @p0i16() { define i16 @p0i16() {
; CHECK-LABEL: p0i16: ; CHECK-LABEL: p0i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i16 0 ret i16 0
} }
define signext i16 @p0si16() { define signext i16 @p0si16() {
; CHECK-LABEL: p0si16: ; CHECK-LABEL: p0si16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i16 0 ret i16 0
} }
define zeroext i16 @p0zi16() { define zeroext i16 @p0zi16() {
; CHECK-LABEL: p0zi16: ; CHECK-LABEL: p0zi16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i16 0 ret i16 0
} }
define i32 @p0i32() { define i32 @p0i32() {
; CHECK-LABEL: p0i32: ; CHECK-LABEL: p0i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 0 ret i32 0
} }
define signext i32 @p0si32() { define signext i32 @p0si32() {
; CHECK-LABEL: p0si32: ; CHECK-LABEL: p0si32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 0 ret i32 0
} }
define zeroext i32 @p0zi32() { define zeroext i32 @p0zi32() {
; CHECK-LABEL: p0zi32: ; CHECK-LABEL: p0zi32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 0 ret i32 0
} }
define i32 @p128i32() { define i32 @p128i32() {
; CHECK-LABEL: p128i32: ; CHECK-LABEL: p128i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128 ; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 128 ret i32 128
} }
define signext i32 @p128si32() { define signext i32 @p128si32() {
; CHECK-LABEL: p128si32: ; CHECK-LABEL: p128si32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128 ; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 128 ret i32 128
} }
define zeroext i32 @p128zi32() { define zeroext i32 @p128zi32() {
; CHECK-LABEL: p128zi32: ; CHECK-LABEL: p128zi32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128 ; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i32 128 ret i32 128
} }
define i64 @p0i64() { define i64 @p0i64() {
; CHECK-LABEL: p0i64: ; CHECK-LABEL: p0i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 0 ret i64 0
} }
define signext i64 @p0si64() { define signext i64 @p0si64() {
; CHECK-LABEL: p0si64: ; CHECK-LABEL: p0si64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 0 ret i64 0
} }
define zeroext i64 @p0zi64() { define zeroext i64 @p0zi64() {
; CHECK-LABEL: p0zi64: ; CHECK-LABEL: p0zi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 0 ret i64 0
} }
define i64 @p128i64() { define i64 @p128i64() {
; CHECK-LABEL: p128i64: ; CHECK-LABEL: p128i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128 ; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 128 ret i64 128
} }
define signext i64 @p128si64() { define signext i64 @p128si64() {
; CHECK-LABEL: p128si64: ; CHECK-LABEL: p128si64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128 ; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 128 ret i64 128
} }
define zeroext i64 @p128zi64() { define zeroext i64 @p128zi64() {
; CHECK-LABEL: p128zi64: ; CHECK-LABEL: p128zi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128 ; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 128 ret i64 128
} }
define i64 @p2264924160i64() { define i64 @p2264924160i64() {
; CHECK-LABEL: p2264924160i64: ; CHECK-LABEL: p2264924160i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2030043136 ; CHECK-NEXT: lea %s0, -2030043136
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 2264924160 ret i64 2264924160
} }
define signext i64 @p2264924160si64() { define signext i64 @p2264924160si64() {
; CHECK-LABEL: p2264924160si64: ; CHECK-LABEL: p2264924160si64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2030043136 ; CHECK-NEXT: lea %s0, -2030043136
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 2264924160 ret i64 2264924160
} }
define zeroext i64 @p2264924160zi64() { define zeroext i64 @p2264924160zi64() {
; CHECK-LABEL: p2264924160zi64: ; CHECK-LABEL: p2264924160zi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2030043136 ; CHECK-NEXT: lea %s0, -2030043136
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 2264924160 ret i64 2264924160
} }
define i64 @p2147483647i64() { define i64 @p2147483647i64() {
; CHECK-LABEL: p2147483647i64: ; CHECK-LABEL: p2147483647i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647 ; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 2147483647 ret i64 2147483647
} }
define signext i64 @p2147483647si64() { define signext i64 @p2147483647si64() {
; CHECK-LABEL: p2147483647si64: ; CHECK-LABEL: p2147483647si64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647 ; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 2147483647 ret i64 2147483647
} }
define zeroext i64 @p2147483647zi64() { define zeroext i64 @p2147483647zi64() {
; CHECK-LABEL: p2147483647zi64: ; CHECK-LABEL: p2147483647zi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647 ; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 2147483647 ret i64 2147483647
} }
define i64 @p15032385535i64() { define i64 @p15032385535i64() {
; CHECK-LABEL: p15032385535i64: ; CHECK-LABEL: p15032385535i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647 ; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: lea.sl %s0, 3(, %s0) ; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385535 ret i64 15032385535
} }
define signext i64 @p15032385535si64() { define signext i64 @p15032385535si64() {
; CHECK-LABEL: p15032385535si64: ; CHECK-LABEL: p15032385535si64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647 ; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: lea.sl %s0, 3(, %s0) ; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385535 ret i64 15032385535
} }
define zeroext i64 @p15032385535zi64() { define zeroext i64 @p15032385535zi64() {
; CHECK-LABEL: p15032385535zi64: ; CHECK-LABEL: p15032385535zi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647 ; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: lea.sl %s0, 3(, %s0) ; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385535 ret i64 15032385535
} }
define i64 @p15032385536i64() { define i64 @p15032385536i64() {
; CHECK-LABEL: p15032385536i64: ; CHECK-LABEL: p15032385536i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, 3(, %s0) ; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385536 ret i64 15032385536
} }
define signext i64 @p15032385536si64() { define signext i64 @p15032385536si64() {
; CHECK-LABEL: p15032385536si64: ; CHECK-LABEL: p15032385536si64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, 3(, %s0) ; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385536 ret i64 15032385536
} }
define zeroext i64 @p15032385536zi64() { define zeroext i64 @p15032385536zi64() {
; CHECK-LABEL: p15032385536zi64: ; CHECK-LABEL: p15032385536zi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648 ; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, 3(, %s0) ; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385536 ret i64 15032385536
} }
define float @m5f32() { define float @m5f32() {
; CHECK-LABEL: m5f32: ; CHECK-LABEL: m5f32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -1063256064 ; CHECK-NEXT: lea.sl %s0, -1063256064
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float -5.000000e+00 ret float -5.000000e+00
} }
define double @m5f64() { define double @m5f64() {
; CHECK-LABEL: m5f64: ; CHECK-LABEL: m5f64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -1072431104 ; CHECK-NEXT: lea.sl %s0, -1072431104
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double -5.000000e+00 ret double -5.000000e+00
} }
define float @p2p3f32() { define float @p2p3f32() {
; CHECK-LABEL: p2p3f32: ; CHECK-LABEL: p2p3f32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1075000115 ; CHECK-NEXT: lea.sl %s0, 1075000115
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 0x4002666660000000 ; 2.3 ret float 0x4002666660000000 ; 2.3
} }
define double @p2p3f64() { define double @p2p3f64() {
; CHECK-LABEL: p2p3f64: ; CHECK-LABEL: p2p3f64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 1717986918 ; CHECK-NEXT: lea %s0, 1717986918
; CHECK-NEXT: lea.sl %s0, 1073899110(, %s0) ; CHECK-NEXT: lea.sl %s0, 1073899110(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 2.3 ret double 2.3
} }
define float @p128p3f32() { define float @p128p3f32() {
; CHECK-LABEL: p128p3f32: ; CHECK-LABEL: p128p3f32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1124093133 ; CHECK-NEXT: lea.sl %s0, 1124093133
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 0x40600999A0000000 ; 128.3 ret float 0x40600999A0000000 ; 128.3
} }
define double @p128p3f64() { define double @p128p3f64() {
; CHECK-LABEL: p128p3f64: ; CHECK-LABEL: p128p3f64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -1717986918 ; CHECK-NEXT: lea %s0, -1717986918
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, 1080035737(, %s0) ; CHECK-NEXT: lea.sl %s0, 1080035737(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 128.3 ret double 128.3
} }

llvm/test/CodeGen/VE/Scalar/ctlz.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
declare i128 @llvm.ctlz.i128(i128, i1) declare i128 @llvm.ctlz.i128(i128, i1)
declare i64 @llvm.ctlz.i64(i64, i1) declare i64 @llvm.ctlz.i64(i64, i1)
declare i32 @llvm.ctlz.i32(i32, i1) declare i32 @llvm.ctlz.i32(i32, i1)
declare i16 @llvm.ctlz.i16(i16, i1) declare i16 @llvm.ctlz.i16(i16, i1)
declare i8 @llvm.ctlz.i8(i8, i1) declare i8 @llvm.ctlz.i8(i8, i1)
define i128 @func128(i128 %p){ define i128 @func128(i128 %p){
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s2, %s1, (0)1 ; CHECK-NEXT: cmps.l %s2, %s1, (0)1
; CHECK-NEXT: ldz %s1, %s1 ; CHECK-NEXT: ldz %s1, %s1
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0) ; CHECK-NEXT: lea %s0, 64(, %s0)
; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2 ; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true) %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true)
ret i128 %r ret i128 %r
} }
define i64 @func64(i64 %p) { define i64 @func64(i64 %p) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctlz.i64(i64 %p, i1 true) %r = tail call i64 @llvm.ctlz.i64(i64 %p, i1 true)
ret i64 %r ret i64 %r
} }
define signext i32 @func32s(i32 signext %p) { define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true) %r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32z(i32 zeroext %p) { define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true) %r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true)
ret i32 %r ret i32 %r
} }
define signext i16 @func16s(i16 signext %p) { define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -16, %s0 ; CHECK-NEXT: adds.w.sx %s0, -16, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 true) %r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 true)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16z(i16 zeroext %p) { define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -16, %s0 ; CHECK-NEXT: adds.w.sx %s0, -16, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 true) %r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 true)
ret i16 %r ret i16 %r
} }
define signext i8 @func8s(i8 signext %p) { define signext i8 @func8s(i8 signext %p) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -24, %s0 ; CHECK-NEXT: adds.w.sx %s0, -24, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 true) %r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 true)
ret i8 %r ret i8 %r
} }
define zeroext i8 @func8z(i8 zeroext %p) { define zeroext i8 @func8z(i8 zeroext %p) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -24, %s0 ; CHECK-NEXT: adds.w.sx %s0, -24, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 true) %r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 true)
ret i8 %r ret i8 %r
} }
define i128 @func128i(){ define i128 @func128i(){
; CHECK-LABEL: func128i: ; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 112 ; CHECK-NEXT: lea %s0, 112
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctlz.i128(i128 65535, i1 true) %r = tail call i128 @llvm.ctlz.i128(i128 65535, i1 true)
ret i128 %r ret i128 %r
} }
define i64 @func64i() { define i64 @func64i() {
; CHECK-LABEL: func64i: ; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 48, (0)1 ; CHECK-NEXT: or %s0, 48, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctlz.i64(i64 65535, i1 true) %r = tail call i64 @llvm.ctlz.i64(i64 65535, i1 true)
ret i64 %r ret i64 %r
} }
define signext i32 @func32is() { define signext i32 @func32is() {
; CHECK-LABEL: func32is: ; CHECK-LABEL: func32is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 65535, i1 true) %r = tail call i32 @llvm.ctlz.i32(i32 65535, i1 true)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32iz() { define zeroext i32 @func32iz() {
; CHECK-LABEL: func32iz: ; CHECK-LABEL: func32iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 65535, i1 true) %r = tail call i32 @llvm.ctlz.i32(i32 65535, i1 true)
ret i32 %r ret i32 %r
} }
define signext i16 @func16is() { define signext i16 @func16is() {
; CHECK-LABEL: func16is: ; CHECK-LABEL: func16is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 255, i1 true) %r = tail call i16 @llvm.ctlz.i16(i16 255, i1 true)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16iz() { define zeroext i16 @func16iz() {
; CHECK-LABEL: func16iz: ; CHECK-LABEL: func16iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 255, i1 true) %r = tail call i16 @llvm.ctlz.i16(i16 255, i1 true)
ret i16 %r ret i16 %r
} }
define signext i8 @func8is() { define signext i8 @func8is() {
; CHECK-LABEL: func8is: ; CHECK-LABEL: func8is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true) %r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true)
ret i8 %r ret i8 %r
} }
define zeroext i8 @func8iz() { define zeroext i8 @func8iz() {
; CHECK-LABEL: func8iz: ; CHECK-LABEL: func8iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true) %r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true)
ret i8 %r ret i8 %r
} }
define i128 @func128x(i128 %p){ define i128 @func128x(i128 %p){
; CHECK-LABEL: func128x: ; CHECK-LABEL: func128x:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s2, %s1, (0)1 ; CHECK-NEXT: cmps.l %s2, %s1, (0)1
; CHECK-NEXT: ldz %s1, %s1 ; CHECK-NEXT: ldz %s1, %s1
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0) ; CHECK-NEXT: lea %s0, 64(, %s0)
; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2 ; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false) %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false)
ret i128 %r ret i128 %r
} }
define i64 @func64x(i64 %p) { define i64 @func64x(i64 %p) {
; CHECK-LABEL: func64x: ; CHECK-LABEL: func64x:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctlz.i64(i64 %p, i1 false) %r = tail call i64 @llvm.ctlz.i64(i64 %p, i1 false)
ret i64 %r ret i64 %r
} }
define signext i32 @func32sx(i32 signext %p) { define signext i32 @func32sx(i32 signext %p) {
; CHECK-LABEL: func32sx: ; CHECK-LABEL: func32sx:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 false) %r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 false)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32zx(i32 zeroext %p) { define zeroext i32 @func32zx(i32 zeroext %p) {
; CHECK-LABEL: func32zx: ; CHECK-LABEL: func32zx:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 false) %r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 false)
ret i32 %r ret i32 %r
} }
define signext i16 @func16sx(i16 signext %p) { define signext i16 @func16sx(i16 signext %p) {
; CHECK-LABEL: func16sx: ; CHECK-LABEL: func16sx:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -16, %s0 ; CHECK-NEXT: adds.w.sx %s0, -16, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 false) %r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 false)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16zx(i16 zeroext %p) { define zeroext i16 @func16zx(i16 zeroext %p) {
; CHECK-LABEL: func16zx: ; CHECK-LABEL: func16zx:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -16, %s0 ; CHECK-NEXT: adds.w.sx %s0, -16, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 false) %r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 false)
ret i16 %r ret i16 %r
} }
define signext i8 @func8sx(i8 signext %p) { define signext i8 @func8sx(i8 signext %p) {
; CHECK-LABEL: func8sx: ; CHECK-LABEL: func8sx:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -24, %s0 ; CHECK-NEXT: adds.w.sx %s0, -24, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 false) %r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 false)
ret i8 %r ret i8 %r
} }
define zeroext i8 @func8zx(i8 zeroext %p) { define zeroext i8 @func8zx(i8 zeroext %p) {
; CHECK-LABEL: func8zx: ; CHECK-LABEL: func8zx:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0 ; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0) ; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -24, %s0 ; CHECK-NEXT: adds.w.sx %s0, -24, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 false) %r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 false)
ret i8 %r ret i8 %r
} }

llvm/test/CodeGen/VE/Scalar/ctpop.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
declare i128 @llvm.ctpop.i128(i128) declare i128 @llvm.ctpop.i128(i128)
declare i64 @llvm.ctpop.i64(i64) declare i64 @llvm.ctpop.i64(i64)
declare i32 @llvm.ctpop.i32(i32) declare i32 @llvm.ctpop.i32(i32)
declare i16 @llvm.ctpop.i16(i16) declare i16 @llvm.ctpop.i16(i16)
declare i8 @llvm.ctpop.i8(i8) declare i8 @llvm.ctpop.i8(i8)
define i128 @func128(i128 %p) { define i128 @func128(i128 %p) {
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s1, %s1 ; CHECK-NEXT: pcnt %s1, %s1
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: adds.l %s0, %s0, %s1 ; CHECK-NEXT: adds.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctpop.i128(i128 %p) %r = tail call i128 @llvm.ctpop.i128(i128 %p)
ret i128 %r ret i128 %r
} }
define i64 @func64(i64 %p) { define i64 @func64(i64 %p) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctpop.i64(i64 %p) %r = tail call i64 @llvm.ctpop.i64(i64 %p)
ret i64 %r ret i64 %r
} }
define signext i32 @func32s(i32 signext %p) { define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctpop.i32(i32 %p) %r = tail call i32 @llvm.ctpop.i32(i32 %p)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32z(i32 zeroext %p) { define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctpop.i32(i32 %p) %r = tail call i32 @llvm.ctpop.i32(i32 %p)
ret i32 %r ret i32 %r
} }
define signext i16 @func16s(i16 signext %p) { define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctpop.i16(i16 %p) %r = tail call i16 @llvm.ctpop.i16(i16 %p)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16z(i16 zeroext %p) { define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctpop.i16(i16 %p) %r = tail call i16 @llvm.ctpop.i16(i16 %p)
ret i16 %r ret i16 %r
} }
define signext i8 @func8s(i8 signext %p) { define signext i8 @func8s(i8 signext %p) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctpop.i8(i8 %p) %r = tail call i8 @llvm.ctpop.i8(i8 %p)
ret i8 %r ret i8 %r
} }
define zeroext i8 @func8z(i8 zeroext %p) { define zeroext i8 @func8z(i8 zeroext %p) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctpop.i8(i8 %p) %r = tail call i8 @llvm.ctpop.i8(i8 %p)
ret i8 %r ret i8 %r
} }
define i128 @func128i() { define i128 @func128i() {
; CHECK-LABEL: func128i: ; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctpop.i128(i128 65535) %r = tail call i128 @llvm.ctpop.i128(i128 65535)
ret i128 %r ret i128 %r
} }
define i64 @func64i() { define i64 @func64i() {
; CHECK-LABEL: func64i: ; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctpop.i64(i64 65535) %r = tail call i64 @llvm.ctpop.i64(i64 65535)
ret i64 %r ret i64 %r
} }
define signext i32 @func32is() { define signext i32 @func32is() {
; CHECK-LABEL: func32is: ; CHECK-LABEL: func32is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctpop.i32(i32 65535) %r = tail call i32 @llvm.ctpop.i32(i32 65535)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32iz() { define zeroext i32 @func32iz() {
; CHECK-LABEL: func32iz: ; CHECK-LABEL: func32iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctpop.i32(i32 65535) %r = tail call i32 @llvm.ctpop.i32(i32 65535)
ret i32 %r ret i32 %r
} }
define signext i16 @func16si() { define signext i16 @func16si() {
; CHECK-LABEL: func16si: ; CHECK-LABEL: func16si:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctpop.i16(i16 65535) %r = tail call i16 @llvm.ctpop.i16(i16 65535)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16zi() { define zeroext i16 @func16zi() {
; CHECK-LABEL: func16zi: ; CHECK-LABEL: func16zi:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1 ; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctpop.i16(i16 65535) %r = tail call i16 @llvm.ctpop.i16(i16 65535)
ret i16 %r ret i16 %r
} }
define signext i8 @func8si() { define signext i8 @func8si() {
; CHECK-LABEL: func8si: ; CHECK-LABEL: func8si:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctpop.i8(i8 255) %r = tail call i8 @llvm.ctpop.i8(i8 255)
ret i8 %r ret i8 %r
} }
define zeroext i8 @func8zi() { define zeroext i8 @func8zi() {
; CHECK-LABEL: func8zi: ; CHECK-LABEL: func8zi:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctpop.i8(i8 255) %r = tail call i8 @llvm.ctpop.i8(i8 255)
ret i8 %r ret i8 %r
} }

llvm/test/CodeGen/VE/Scalar/cttz.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
declare i128 @llvm.cttz.i128(i128, i1) declare i128 @llvm.cttz.i128(i128, i1)
declare i64 @llvm.cttz.i64(i64, i1) declare i64 @llvm.cttz.i64(i64, i1)
declare i32 @llvm.cttz.i32(i32, i1) declare i32 @llvm.cttz.i32(i32, i1)
declare i16 @llvm.cttz.i16(i16, i1) declare i16 @llvm.cttz.i16(i16, i1)
declare i8 @llvm.cttz.i8(i8, i1) declare i8 @llvm.cttz.i8(i8, i1)
define i128 @func128(i128 %p) { define i128 @func128(i128 %p) {
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s2, %s0, (0)1 ; CHECK-NEXT: cmps.l %s2, %s0, (0)1
; CHECK-NEXT: lea %s3, -1(, %s0) ; CHECK-NEXT: lea %s3, -1(, %s0)
; CHECK-NEXT: nnd %s0, %s0, %s3 ; CHECK-NEXT: nnd %s0, %s0, %s3
; CHECK-NEXT: pcnt %s3, %s0 ; CHECK-NEXT: pcnt %s3, %s0
; CHECK-NEXT: lea %s0, -1(, %s1) ; CHECK-NEXT: lea %s0, -1(, %s1)
; CHECK-NEXT: nnd %s0, %s1, %s0 ; CHECK-NEXT: nnd %s0, %s1, %s0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0) ; CHECK-NEXT: lea %s0, 64(, %s0)
; CHECK-NEXT: cmov.l.ne %s0, %s3, %s2 ; CHECK-NEXT: cmov.l.ne %s0, %s3, %s2
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true) %r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true)
ret i128 %r ret i128 %r
} }
define i64 @func64(i64 %p) { define i64 @func64(i64 %p) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1(, %s0) ; CHECK-NEXT: lea %s1, -1(, %s0)
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.cttz.i64(i64 %p, i1 true) %r = tail call i64 @llvm.cttz.i64(i64 %p, i1 true)
ret i64 %r ret i64 %r
} }
define signext i32 @func32s(i32 signext %p) { define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true) %r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32z(i32 zeroext %p) { define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true) %r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
ret i32 %r ret i32 %r
} }
define signext i16 @func16s(i16 signext %p) { define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true) %r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16z(i16 zeroext %p) { define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true) %r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
ret i16 %r ret i16 %r
} }
define signext i8 @func8s(i8 signext %p) { define signext i8 @func8s(i8 signext %p) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true) %r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
ret i8 %r ret i8 %r
} }
define zeroext i8 @func8z(i8 zeroext %p) { define zeroext i8 @func8z(i8 zeroext %p) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0 ; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true) %r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
ret i8 %r ret i8 %r
} }
define i128 @func128i() { define i128 @func128i() {
; CHECK-LABEL: func128i: ; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.cttz.i128(i128 65280, i1 true) %r = tail call i128 @llvm.cttz.i128(i128 65280, i1 true)
ret i128 %r ret i128 %r
} }
define i64 @func64i() { define i64 @func64i() {
; CHECK-LABEL: func64i: ; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.cttz.i64(i64 65280, i1 true) %r = tail call i64 @llvm.cttz.i64(i64 65280, i1 true)
ret i64 %r ret i64 %r
} }
define signext i32 @func32is() { define signext i32 @func32is() {
; CHECK-LABEL: func32is: ; CHECK-LABEL: func32is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true) %r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true)
ret i32 %r ret i32 %r
} }
define zeroext i32 @func32iz() { define zeroext i32 @func32iz() {
; CHECK-LABEL: func32iz: ; CHECK-LABEL: func32iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true) %r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true)
ret i32 %r ret i32 %r
} }
define signext i16 @func16is() { define signext i16 @func16is() {
; CHECK-LABEL: func16is: ; CHECK-LABEL: func16is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true) %r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true)
ret i16 %r ret i16 %r
} }
define zeroext i16 @func16iz() { define zeroext i16 @func16iz() {
; CHECK-LABEL: func16iz: ; CHECK-LABEL: func16iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1 ; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true) %r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true)
ret i16 %r ret i16 %r
} }
define signext i8 @func8is() { define signext i8 @func8is() {
; CHECK-LABEL: func8is: ; CHECK-LABEL: func8is:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 4, (0)1 ; CHECK-NEXT: or %s0, 4, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.cttz.i8(i8 240, i1 true) %r = tail call i8 @llvm.cttz.i8(i8 240, i1 true)
ret i8 %r ret i8 %r
} }
define zeroext i8 @func8iz() { define zeroext i8 @func8iz() {
; CHECK-LABEL: func8iz: ; CHECK-LABEL: func8iz:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 4, (0)1 ; CHECK-NEXT: or %s0, 4, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.cttz.i8(i8 240, i1 true) %r = tail call i8 @llvm.cttz.i8(i8 240, i1 true)
ret i8 %r ret i8 %r
} }

llvm/test/CodeGen/VE/Scalar/div.ll

Show All 10 Lines
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = sdiv i128 %0, %1 %3 = sdiv i128 %0, %1
ret i128 %3 ret i128 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @divi64(i64 %a, i64 %b) { define i64 @divi64(i64 %a, i64 %b) {
; CHECK-LABEL: divi64: ; CHECK-LABEL: divi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s0, %s0, %s1 ; CHECK-NEXT: divs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i64 %a, %b %r = sdiv i64 %a, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @divi32(i32 signext %a, i32 signext %b) { define signext i32 @divi32(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32: ; CHECK-LABEL: divi32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i32 %a, %b %r = sdiv i32 %a, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divu128(i128, i128) { define i128 @divu128(i128, i128) {
; CHECK-LABEL: divu128: ; CHECK-LABEL: divu128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s4, __udivti3@lo ; CHECK-NEXT: lea %s4, __udivti3@lo
; CHECK-NEXT: and %s4, %s4, (32)0 ; CHECK-NEXT: and %s4, %s4, (32)0
; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s4) ; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s4)
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = udiv i128 %0, %1 %3 = udiv i128 %0, %1
ret i128 %3 ret i128 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @divu64(i64 %a, i64 %b) { define i64 @divu64(i64 %a, i64 %b) {
; CHECK-LABEL: divu64: ; CHECK-LABEL: divu64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s0, %s0, %s1 ; CHECK-NEXT: divu.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i64 %a, %b %r = udiv i64 %a, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @divu32(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @divu32(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: divu32: ; CHECK-LABEL: divu32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, %s0, %s1 ; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i32 %a, %b %r = udiv i32 %a, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @divi16(i16 signext %a, i16 signext %b) { define signext i16 @divi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: divi16: ; CHECK-LABEL: divi16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%a32 = sext i16 %a to i32 %a32 = sext i16 %a to i32
%b32 = sext i16 %b to i32 %b32 = sext i16 %b to i32
%r32 = sdiv i32 %a32, %b32 %r32 = sdiv i32 %a32, %b32
%r = trunc i32 %r32 to i16 %r = trunc i32 %r32 to i16
ret i16 %r ret i16 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: divu16: ; CHECK-LABEL: divu16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, %s0, %s1 ; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i16 %a, %b %r = udiv i16 %a, %b
ret i16 %r ret i16 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @divi8(i8 signext %a, i8 signext %b) { define signext i8 @divi8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: divi8: ; CHECK-LABEL: divi8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%a32 = sext i8 %a to i32 %a32 = sext i8 %a to i32
%b32 = sext i8 %b to i32 %b32 = sext i8 %b to i32
%r32 = sdiv i32 %a32, %b32 %r32 = sdiv i32 %a32, %b32
%r = trunc i32 %r32 to i8 %r = trunc i32 %r32 to i8
ret i8 %r ret i8 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @divu8(i8 zeroext %a, i8 zeroext %b) { define zeroext i8 @divu8(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: divu8: ; CHECK-LABEL: divu8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, %s0, %s1 ; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i8 %a, %b %r = udiv i8 %a, %b
ret i8 %r ret i8 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divi128ri(i128) { define i128 @divi128ri(i128) {
; CHECK-LABEL: divi128ri: ; CHECK-LABEL: divi128ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __divti3@lo ; CHECK-NEXT: lea %s2, __divti3@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s2) ; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s2)
; CHECK-NEXT: or %s2, 3, (0)1 ; CHECK-NEXT: or %s2, 3, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = sdiv i128 %0, 3 %2 = sdiv i128 %0, 3
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @divi64ri(i64 %a, i64 %b) { define i64 @divi64ri(i64 %a, i64 %b) {
; CHECK-LABEL: divi64ri: ; CHECK-LABEL: divi64ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s0, %s0, (62)0 ; CHECK-NEXT: divs.l %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i64 %a, 3 %r = sdiv i64 %a, 3
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @divi32ri(i32 signext %a, i32 signext %b) { define signext i32 @divi32ri(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32ri: ; CHECK-LABEL: divi32ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, %s0, (62)0 ; CHECK-NEXT: divs.w.sx %s0, %s0, (62)0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i32 %a, 3 %r = sdiv i32 %a, 3
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divu128ri(i128) { define i128 @divu128ri(i128) {
; CHECK-LABEL: divu128ri: ; CHECK-LABEL: divu128ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __udivti3@lo ; CHECK-NEXT: lea %s2, __udivti3@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s2) ; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s2)
; CHECK-NEXT: or %s2, 3, (0)1 ; CHECK-NEXT: or %s2, 3, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = udiv i128 %0, 3 %2 = udiv i128 %0, 3
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @divu64ri(i64 %a, i64 %b) { define i64 @divu64ri(i64 %a, i64 %b) {
; CHECK-LABEL: divu64ri: ; CHECK-LABEL: divu64ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s0, %s0, (62)0 ; CHECK-NEXT: divu.l %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i64 %a, 3 %r = udiv i64 %a, 3
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @divu32ri(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @divu32ri(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: divu32ri: ; CHECK-LABEL: divu32ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, %s0, (62)0 ; CHECK-NEXT: divu.w %s0, %s0, (62)0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i32 %a, 3 %r = udiv i32 %a, 3
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divi128li(i128) { define i128 @divi128li(i128) {
; CHECK-LABEL: divi128li: ; CHECK-LABEL: divi128li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s3, 0, %s1 ; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: or %s2, 0, %s0 ; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: lea %s0, __divti3@lo ; CHECK-NEXT: lea %s0, __divti3@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __divti3@hi(, %s0)
; CHECK-NEXT: or %s0, 3, (0)1 ; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = sdiv i128 3, %0 %2 = sdiv i128 3, %0
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @divi64li(i64 %a, i64 %b) { define i64 @divi64li(i64 %a, i64 %b) {
; CHECK-LABEL: divi64li: ; CHECK-LABEL: divi64li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s0, 3, %s1 ; CHECK-NEXT: divs.l %s0, 3, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i64 3, %b %r = sdiv i64 3, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @divi32li(i32 signext %a, i32 signext %b) { define signext i32 @divi32li(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32li: ; CHECK-LABEL: divi32li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, 3, %s1 ; CHECK-NEXT: divs.w.sx %s0, 3, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i32 3, %b %r = sdiv i32 3, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @divu128li(i128) { define i128 @divu128li(i128) {
; CHECK-LABEL: divu128li: ; CHECK-LABEL: divu128li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s3, 0, %s1 ; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: or %s2, 0, %s0 ; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: lea %s0, __udivti3@lo ; CHECK-NEXT: lea %s0, __udivti3@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __udivti3@hi(, %s0)
; CHECK-NEXT: or %s0, 3, (0)1 ; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = udiv i128 3, %0 %2 = udiv i128 3, %0
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @divu64li(i64 %a, i64 %b) { define i64 @divu64li(i64 %a, i64 %b) {
; CHECK-LABEL: divu64li: ; CHECK-LABEL: divu64li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s0, 3, %s1 ; CHECK-NEXT: divu.l %s0, 3, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i64 3, %b %r = udiv i64 3, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @divu32li(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @divu32li(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: divu32li: ; CHECK-LABEL: divu32li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, 3, %s1 ; CHECK-NEXT: divu.w %s0, 3, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i32 3, %b %r = udiv i32 3, %b
ret i32 %r ret i32 %r
} }

llvm/test/CodeGen/VE/Scalar/fabs.ll

Show All 24 Lines
;;; and handles error conditions in the same way. ;;; and handles error conditions in the same way.
;;; ;;;
;;; Note: ;;; Note:
;;; We test only float/double/fp128. ;;; We test only float/double/fp128.
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define float @fabs_float_var(float %0) { define float @fabs_float_var(float %0) {
; CHECK-LABEL: fabs_float_var: ; CHECK-LABEL: fabs_float_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: and %s0, %s0, (33)0 ; CHECK-NEXT: and %s0, %s0, (33)0
; CHECK-NEXT: sll %s0, %s0, 32 ; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast float @llvm.fabs.f32(float %0) %2 = tail call fast float @llvm.fabs.f32(float %0)
ret float %2 ret float %2
} }
; Function Attrs: nounwind readnone speculatable willreturn ; Function Attrs: nounwind readnone speculatable willreturn
declare float @llvm.fabs.f32(float) declare float @llvm.fabs.f32(float)
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define double @fabs_double_var(double %0) { define double @fabs_double_var(double %0) {
; CHECK-LABEL: fabs_double_var: ; CHECK-LABEL: fabs_double_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (1)0 ; CHECK-NEXT: and %s0, %s0, (1)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast double @llvm.fabs.f64(double %0) %2 = tail call fast double @llvm.fabs.f64(double %0)
ret double %2 ret double %2
} }
; Function Attrs: nounwind readnone speculatable willreturn ; Function Attrs: nounwind readnone speculatable willreturn
declare double @llvm.fabs.f64(double) declare double @llvm.fabs.f64(double)
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
Show All 13 Lines
} }
; Function Attrs: nounwind readnone speculatable willreturn ; Function Attrs: nounwind readnone speculatable willreturn
declare fp128 @llvm.fabs.f128(fp128) declare fp128 @llvm.fabs.f128(fp128)
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @fabs_float_zero() { define float @fabs_float_zero() {
; CHECK-LABEL: fabs_float_zero: ; CHECK-LABEL: fabs_float_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0 ; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 0.000000e+00 ret float 0.000000e+00
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @fabs_double_zero() { define double @fabs_double_zero() {
; CHECK-LABEL: fabs_double_zero: ; CHECK-LABEL: fabs_double_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0 ; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 0.000000e+00 ret double 0.000000e+00
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @fabs_quad_zero() { define fp128 @fabs_quad_zero() {
; CHECK-LABEL: fabs_quad_zero: ; CHECK-LABEL: fabs_quad_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0)
; CHECK-NEXT: ld %s0, 8(, %s2) ; CHECK-NEXT: ld %s0, 8(, %s2)
; CHECK-NEXT: ld %s1, (, %s2) ; CHECK-NEXT: ld %s1, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret fp128 0xL00000000000000000000000000000000 ret fp128 0xL00000000000000000000000000000000
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @fabs_float_const() { define float @fabs_float_const() {
; CHECK-LABEL: fabs_float_const: ; CHECK-LABEL: fabs_float_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1073741824 ; CHECK-NEXT: lea.sl %s0, 1073741824
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 2.000000e+00 ret float 2.000000e+00
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @fabs_double_const() { define double @fabs_double_const() {
; CHECK-LABEL: fabs_double_const: ; CHECK-LABEL: fabs_double_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1073741824 ; CHECK-NEXT: lea.sl %s0, 1073741824
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 2.000000e+00 ret double 2.000000e+00
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fp128 @fabs_quad_const() { define fp128 @fabs_quad_const() {
; CHECK-LABEL: fabs_quad_const: ; CHECK-LABEL: fabs_quad_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0)
; CHECK-NEXT: ld %s0, 8(, %s2) ; CHECK-NEXT: ld %s0, 8(, %s2)
; CHECK-NEXT: ld %s1, (, %s2) ; CHECK-NEXT: ld %s1, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = tail call fast fp128 @llvm.fabs.f128(fp128 0xL0000000000000000C000000000000000) %1 = tail call fast fp128 @llvm.fabs.f128(fp128 0xL0000000000000000C000000000000000)
ret fp128 %1 ret fp128 %1
} }

llvm/test/CodeGen/VE/Scalar/fcopysign.ll

Show All 25 Lines
;;; would, and handles error conditions in the same way. ;;; would, and handles error conditions in the same way.
;;; ;;;
;;; Note: ;;; Note:
;;; We test only float/double/fp128. ;;; We test only float/double/fp128.
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define float @copysign_float_var(float %0, float %1) { define float @copysign_float_var(float %0, float %1) {
; CHECK-LABEL: copysign_float_var: ; CHECK-LABEL: copysign_float_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s1, 32 ; CHECK-NEXT: sra.l %s1, %s1, 32
; CHECK-NEXT: lea %s2, -2147483648 ; CHECK-NEXT: lea %s2, -2147483648
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: and %s1, %s1, %s2 ; CHECK-NEXT: and %s1, %s1, %s2
; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: and %s0, %s0, (33)0 ; CHECK-NEXT: and %s0, %s0, (33)0
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 32 ; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast float @llvm.copysign.f32(float %0, float %1) %3 = tail call fast float @llvm.copysign.f32(float %0, float %1)
ret float %3 ret float %3
} }
; Function Attrs: nounwind readnone speculatable willreturn ; Function Attrs: nounwind readnone speculatable willreturn
declare float @llvm.copysign.f32(float, float) declare float @llvm.copysign.f32(float, float)
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define double @copysign_double_var(double %0, double %1) { define double @copysign_double_var(double %0, double %1) {
; CHECK-LABEL: copysign_double_var: ; CHECK-LABEL: copysign_double_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (1)1 ; CHECK-NEXT: and %s1, %s1, (1)1
; CHECK-NEXT: and %s0, %s0, (1)0 ; CHECK-NEXT: and %s0, %s0, (1)0
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast double @llvm.copysign.f64(double %0, double %1) %3 = tail call fast double @llvm.copysign.f64(double %0, double %1)
ret double %3 ret double %3
} }
; Function Attrs: nounwind readnone speculatable willreturn ; Function Attrs: nounwind readnone speculatable willreturn
declare double @llvm.copysign.f64(double, double) declare double @llvm.copysign.f64(double, double)
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
Show All 19 Lines
} }
; Function Attrs: nounwind readnone speculatable willreturn ; Function Attrs: nounwind readnone speculatable willreturn
declare fp128 @llvm.copysign.f128(fp128, fp128) declare fp128 @llvm.copysign.f128(fp128, fp128)
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define float @copysign_float_zero(float %0) { define float @copysign_float_zero(float %0) {
; CHECK-LABEL: copysign_float_zero: ; CHECK-LABEL: copysign_float_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 32 ; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast float @llvm.copysign.f32(float 0.000000e+00, float %0) %2 = tail call fast float @llvm.copysign.f32(float 0.000000e+00, float %0)
ret float %2 ret float %2
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define double @copysign_double_zero(double %0) { define double @copysign_double_zero(double %0) {
; CHECK-LABEL: copysign_double_zero: ; CHECK-LABEL: copysign_double_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (1)1 ; CHECK-NEXT: and %s0, %s0, (1)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast double @llvm.copysign.f64(double 0.000000e+00, double %0) %2 = tail call fast double @llvm.copysign.f64(double 0.000000e+00, double %0)
ret double %2 ret double %2
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fp128 @copysign_quad_zero(fp128 %0) { define fp128 @copysign_quad_zero(fp128 %0) {
; CHECK-LABEL: copysign_quad_zero: ; CHECK-LABEL: copysign_quad_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
Show All 18 Lines
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = tail call fast fp128 @llvm.copysign.f128(fp128 0xL00000000000000000000000000000000, fp128 %0) %2 = tail call fast fp128 @llvm.copysign.f128(fp128 0xL00000000000000000000000000000000, fp128 %0)
ret fp128 %2 ret fp128 %2
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define float @copysign_float_const(float %0) { define float @copysign_float_const(float %0) {
; CHECK-LABEL: copysign_float_const: ; CHECK-LABEL: copysign_float_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: lea %s1, 1073741824 ; CHECK-NEXT: lea %s1, 1073741824
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 32 ; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast float @llvm.copysign.f32(float -2.000000e+00, float %0) %2 = tail call fast float @llvm.copysign.f32(float -2.000000e+00, float %0)
ret float %2 ret float %2
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define double @copysign_double_const(double %0) { define double @copysign_double_const(double %0) {
; CHECK-LABEL: copysign_double_const: ; CHECK-LABEL: copysign_double_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (1)1 ; CHECK-NEXT: and %s0, %s0, (1)1
; CHECK-NEXT: lea.sl %s1, 1073741824 ; CHECK-NEXT: lea.sl %s1, 1073741824
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast double @llvm.copysign.f64(double -2.000000e+00, double %0) %2 = tail call fast double @llvm.copysign.f64(double -2.000000e+00, double %0)
ret double %2 ret double %2
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fp128 @copysign_quad_const(fp128 %0) { define fp128 @copysign_quad_const(fp128 %0) {
; CHECK-LABEL: copysign_quad_const: ; CHECK-LABEL: copysign_quad_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
Show All 22 Lines

llvm/test/CodeGen/VE/Scalar/fcos.ll

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
} }
; Function Attrs: nounwind readnone speculatable willreturn ; Function Attrs: nounwind readnone speculatable willreturn
declare fp128 @llvm.cos.f128(fp128) declare fp128 @llvm.cos.f128(fp128)
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @fcos_float_zero() { define float @fcos_float_zero() {
; CHECK-LABEL: fcos_float_zero: ; CHECK-LABEL: fcos_float_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1065353216 ; CHECK-NEXT: lea.sl %s0, 1065353216
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 1.000000e+00 ret float 1.000000e+00
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @fcos_double_zero() { define double @fcos_double_zero() {
; CHECK-LABEL: fcos_double_zero: ; CHECK-LABEL: fcos_double_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1072693248 ; CHECK-NEXT: lea.sl %s0, 1072693248
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 1.000000e+00 ret double 1.000000e+00
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fp128 @fcos_quad_zero() { define fp128 @fcos_quad_zero() {
; CHECK-LABEL: fcos_quad_zero: ; CHECK-LABEL: fcos_quad_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0)
; CHECK-NEXT: ld %s0, 8(, %s2) ; CHECK-NEXT: ld %s0, 8(, %s2)
; CHECK-NEXT: ld %s1, (, %s2) ; CHECK-NEXT: ld %s1, (, %s2)
; CHECK-NEXT: lea %s2, cosl@lo ; CHECK-NEXT: lea %s2, cosl@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, cosl@hi(, %s2) ; CHECK-NEXT: lea.sl %s12, cosl@hi(, %s2)
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%1 = tail call fast fp128 @llvm.cos.f128(fp128 0xL00000000000000000000000000000000) %1 = tail call fast fp128 @llvm.cos.f128(fp128 0xL00000000000000000000000000000000)
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @fcos_float_const() { define float @fcos_float_const() {
; CHECK-LABEL: fcos_float_const: ; CHECK-LABEL: fcos_float_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -1093332685 ; CHECK-NEXT: lea.sl %s0, -1093332685
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 0xBFDAA22660000000 ret float 0xBFDAA22660000000
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @fcos_double_const() { define double @fcos_double_const() {
; CHECK-LABEL: fcos_double_const: ; CHECK-LABEL: fcos_double_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 1465086469 ; CHECK-NEXT: lea %s0, 1465086469
; CHECK-NEXT: lea.sl %s0, -1076190682(, %s0) ; CHECK-NEXT: lea.sl %s0, -1076190682(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 0xBFDAA22657537205 ret double 0xBFDAA22657537205
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fp128 @fcos_quad_const() { define fp128 @fcos_quad_const() {
; CHECK-LABEL: fcos_quad_const: ; CHECK-LABEL: fcos_quad_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
Show All 12 Lines

llvm/test/CodeGen/VE/Scalar/fp_add.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @func1(float %a, float %b) { define float @func1(float %a, float %b) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fadd.s %s0, %s0, %s1 ; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, %b %r = fadd float %a, %b
ret float %r ret float %r
} }
define double @func2(double %a, double %b) { define double @func2(double %a, double %b) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fadd.d %s0, %s0, %s1 ; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, %b %r = fadd double %a, %b
ret double %r ret double %r
} }
define fp128 @func3(fp128 %a, fp128 %b) { define fp128 @func3(fp128 %a, fp128 %b) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fadd.q %s0, %s0, %s2 ; CHECK-NEXT: fadd.q %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, %b %r = fadd fp128 %a, %b
ret fp128 %r ret fp128 %r
} }
define float @func4(float %a) { define float @func4(float %a) {
; CHECK-LABEL: func4: ; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1084227584 ; CHECK-NEXT: lea.sl %s1, 1084227584
; CHECK-NEXT: fadd.s %s0, %s0, %s1 ; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, 5.000000e+00 %r = fadd float %a, 5.000000e+00
ret float %r ret float %r
} }
define double @func5(double %a) { define double @func5(double %a) {
; CHECK-LABEL: func5: ; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1075052544 ; CHECK-NEXT: lea.sl %s1, 1075052544
; CHECK-NEXT: fadd.d %s0, %s0, %s1 ; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, 5.000000e+00 %r = fadd double %a, 5.000000e+00
ret double %r ret double %r
} }
define fp128 @func6(fp128 %a) { define fp128 @func6(fp128 %a) {
; CHECK-LABEL: func6: ; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4 ; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xL00000000000000004001400000000000 %r = fadd fp128 %a, 0xL00000000000000004001400000000000
ret fp128 %r ret fp128 %r
} }
define float @func7(float %a) { define float @func7(float %a) {
; CHECK-LABEL: func7: ; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 2139095039 ; CHECK-NEXT: lea.sl %s1, 2139095039
; CHECK-NEXT: fadd.s %s0, %s0, %s1 ; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, 0x47EFFFFFE0000000 %r = fadd float %a, 0x47EFFFFFE0000000
ret float %r ret float %r
} }
define double @func8(double %a) { define double @func8(double %a) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1 ; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1) ; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1)
; CHECK-NEXT: fadd.d %s0, %s0, %s1 ; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, 0x7FEFFFFFFFFFFFFF %r = fadd double %a, 0x7FEFFFFFFFFFFFFF
ret double %r ret double %r
} }
define fp128 @func9(fp128 %a) { define fp128 @func9(fp128 %a) {
; CHECK-LABEL: func9: ; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4 ; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF %r = fadd fp128 %a, 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF
ret fp128 %r ret fp128 %r
} }
define float @fadds_imm(float %a) { define float @fadds_imm(float %a) {
; CHECK-LABEL: fadds_imm: ; CHECK-LABEL: fadds_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fadd.s %s0, %s0, (2)1 ; CHECK-NEXT: fadd.s %s0, %s0, (2)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, -2.e+00 %r = fadd float %a, -2.e+00
ret float %r ret float %r
} }
define double @faddd_imm(double %a) { define double @faddd_imm(double %a) {
; CHECK-LABEL: faddd_imm: ; CHECK-LABEL: faddd_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fadd.d %s0, %s0, (2)1 ; CHECK-NEXT: fadd.d %s0, %s0, (2)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, -2.e+00 %r = fadd double %a, -2.e+00
ret double %r ret double %r
} }
define fp128 @faddq_imm(fp128 %a) { define fp128 @faddq_imm(fp128 %a) {
; CHECK-LABEL: faddq_imm: ; CHECK-LABEL: faddq_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4 ; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xLA0000000000000000000000000000000 %r = fadd fp128 %a, 0xLA0000000000000000000000000000000
ret fp128 %r ret fp128 %r
} }

llvm/test/CodeGen/VE/Scalar/fp_div.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @func1(float %a, float %b) { define float @func1(float %a, float %b) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fdiv.s %s0, %s0, %s1 ; CHECK-NEXT: fdiv.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv float %a, %b %r = fdiv float %a, %b
ret float %r ret float %r
} }
define double @func2(double %a, double %b) { define double @func2(double %a, double %b) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fdiv.d %s0, %s0, %s1 ; CHECK-NEXT: fdiv.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv double %a, %b %r = fdiv double %a, %b
ret double %r ret double %r
} }
define fp128 @func3(fp128 %a, fp128 %b) { define fp128 @func3(fp128 %a, fp128 %b) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s4, __divtf3@lo ; CHECK-NEXT: lea %s4, __divtf3@lo
; CHECK-NEXT: and %s4, %s4, (32)0 ; CHECK-NEXT: and %s4, %s4, (32)0
; CHECK-NEXT: lea.sl %s12, __divtf3@hi(, %s4) ; CHECK-NEXT: lea.sl %s12, __divtf3@hi(, %s4)
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = fdiv fp128 %a, %b %r = fdiv fp128 %a, %b
ret fp128 %r ret fp128 %r
} }
define float @func4(float %a) { define float @func4(float %a) {
; CHECK-LABEL: func4: ; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1084227584 ; CHECK-NEXT: lea.sl %s1, 1084227584
; CHECK-NEXT: fdiv.s %s0, %s0, %s1 ; CHECK-NEXT: fdiv.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv float %a, 5.000000e+00 %r = fdiv float %a, 5.000000e+00
ret float %r ret float %r
} }
define double @func5(double %a) { define double @func5(double %a) {
; CHECK-LABEL: func5: ; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1075052544 ; CHECK-NEXT: lea.sl %s1, 1075052544
; CHECK-NEXT: fdiv.d %s0, %s0, %s1 ; CHECK-NEXT: fdiv.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv double %a, 5.000000e+00 %r = fdiv double %a, 5.000000e+00
ret double %r ret double %r
} }
define fp128 @func6(fp128 %a) { define fp128 @func6(fp128 %a) {
; CHECK-LABEL: func6: ; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s4, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s4, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s2, 8(, %s4) ; CHECK-NEXT: ld %s2, 8(, %s4)
; CHECK-NEXT: ld %s3, (, %s4) ; CHECK-NEXT: ld %s3, (, %s4)
; CHECK-NEXT: lea %s4, __divtf3@lo ; CHECK-NEXT: lea %s4, __divtf3@lo
; CHECK-NEXT: and %s4, %s4, (32)0 ; CHECK-NEXT: and %s4, %s4, (32)0
; CHECK-NEXT: lea.sl %s12, __divtf3@hi(, %s4) ; CHECK-NEXT: lea.sl %s12, __divtf3@hi(, %s4)
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = fdiv fp128 %a, 0xL00000000000000004001400000000000 %r = fdiv fp128 %a, 0xL00000000000000004001400000000000
ret fp128 %r ret fp128 %r
} }
define float @func7(float %a) { define float @func7(float %a) {
; CHECK-LABEL: func7: ; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 2139095039 ; CHECK-NEXT: lea.sl %s1, 2139095039
; CHECK-NEXT: fdiv.s %s0, %s0, %s1 ; CHECK-NEXT: fdiv.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv float %a, 0x47EFFFFFE0000000 %r = fdiv float %a, 0x47EFFFFFE0000000
ret float %r ret float %r
} }
define double @func8(double %a) { define double @func8(double %a) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1 ; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1) ; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1)
; CHECK-NEXT: fdiv.d %s0, %s0, %s1 ; CHECK-NEXT: fdiv.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv double %a, 0x7FEFFFFFFFFFFFFF %r = fdiv double %a, 0x7FEFFFFFFFFFFFFF
ret double %r ret double %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @func9(fp128 %a) { define fp128 @func9(fp128 %a) {
; CHECK-LABEL: func9: ; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
Show All 13 Lines

llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines; CHECK-NEXT: or %s11, 0, %s9
%a.val = load half, half* %a, align 4 %a.val = load half, half* %a, align 4
%a.asd = fpext half %a.val to double %a.asd = fpext half %a.val to double
ret double %a.asd ret double %a.asd
} }
define void @func_fp32i16(i16* %fl.ptr, float %val) { define void @func_fp32i16(i16* %fl.ptr, float %val) {
; CHECK-LABEL: func_fp32i16: ; CHECK-LABEL: func_fp32i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0 ; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo ; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __gnu_f2h_ieee@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __gnu_f2h_ieee@hi(, %s0)
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: st2b %s0, (, %s18) ; CHECK-NEXT: st2b %s0, (, %s18)
; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%val.asf = call i16 @llvm.convert.to.fp16.f32(float %val) %val.asf = call i16 @llvm.convert.to.fp16.f32(float %val)
store i16 %val.asf, i16* %fl.ptr store i16 %val.asf, i16* %fl.ptr
ret void ret void
} }
define half @func_fp32fp16(half* %fl.ptr, float %a) { define half @func_fp32fp16(half* %fl.ptr, float %a) {
; CHECK-LABEL: func_fp32fp16: ; CHECK-LABEL: func_fp32fp16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s19, 296(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0 ; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo ; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __gnu_f2h_ieee@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __gnu_f2h_ieee@hi(, %s0)
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s19, 0, %s0 ; CHECK-NEXT: or %s19, 0, %s0
; CHECK-NEXT: lea %s0, __gnu_h2f_ieee@lo ; CHECK-NEXT: lea %s0, __gnu_h2f_ieee@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(, %s0)
; CHECK-NEXT: or %s0, 0, %s19 ; CHECK-NEXT: or %s0, 0, %s19
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: st2b %s19, (, %s18) ; CHECK-NEXT: st2b %s19, (, %s18)
; CHECK-NEXT: ld %s19, 56(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s19, 296(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%a.asd = fptrunc float %a to half %a.asd = fptrunc float %a to half
store half %a.asd, half* %fl.ptr store half %a.asd, half* %fl.ptr
ret half %a.asd ret half %a.asd
} }
define double @func_fp32fp64(float* %a) { define double @func_fp32fp64(float* %a) {
; CHECK-LABEL: func_fp32fp64: ; CHECK-LABEL: func_fp32fp64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldu %s0, (, %s0) ; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%a.val = load float, float* %a, align 4 %a.val = load float, float* %a, align 4
%a.asd = fpext float %a.val to double %a.asd = fpext float %a.val to double
ret double %a.asd ret double %a.asd
} }
define void @func_fp64i16(i16* %fl.ptr, double %val) { define void @func_fp64i16(i16* %fl.ptr, double %val) {
; CHECK-LABEL: func_fp64i16: ; CHECK-LABEL: func_fp64i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0 ; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __truncdfhf2@lo ; CHECK-NEXT: lea %s0, __truncdfhf2@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __truncdfhf2@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __truncdfhf2@hi(, %s0)
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: st2b %s0, (, %s18) ; CHECK-NEXT: st2b %s0, (, %s18)
; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%val.asf = call i16 @llvm.convert.to.fp16.f64(double %val) %val.asf = call i16 @llvm.convert.to.fp16.f64(double %val)
store i16 %val.asf, i16* %fl.ptr store i16 %val.asf, i16* %fl.ptr
ret void ret void
} }
define void @func_fp64fp16(half* %fl.ptr, double %val) { define void @func_fp64fp16(half* %fl.ptr, double %val) {
; CHECK-LABEL: func_fp64fp16: ; CHECK-LABEL: func_fp64fp16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0 ; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __truncdfhf2@lo ; CHECK-NEXT: lea %s0, __truncdfhf2@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __truncdfhf2@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __truncdfhf2@hi(, %s0)
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: st2b %s0, (, %s18) ; CHECK-NEXT: st2b %s0, (, %s18)
; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%val.asf = fptrunc double %val to half %val.asf = fptrunc double %val to half
store half %val.asf, half* %fl.ptr store half %val.asf, half* %fl.ptr
ret void ret void
} }
define void @func_fp64fp32(float* %fl.ptr, double %val) { define void @func_fp64fp32(float* %fl.ptr, double %val) {
; CHECK-LABEL: func_fp64fp32: ; CHECK-LABEL: func_fp64fp32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cvt.s.d %s1, %s1 ; CHECK-NEXT: cvt.s.d %s1, %s1
; CHECK-NEXT: stu %s1, (, %s0) ; CHECK-NEXT: stu %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%val.asf = fptrunc double %val to float %val.asf = fptrunc double %val to float
store float %val.asf, float* %fl.ptr store float %val.asf, float* %fl.ptr
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/fp_fneg.ll

Show All 22 Lines
;;; <result> = fneg float %val ; yields float:result = -%var ;;; <result> = fneg float %val ; yields float:result = -%var
;;; ;;;
;;; Note: ;;; Note:
;;; We test only float/double/fp128. ;;; We test only float/double/fp128.
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @fneg_float(float %0) { define float @fneg_float(float %0) {
; CHECK-LABEL: fneg_float: ; CHECK-LABEL: fneg_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32 ; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 32 ; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fneg float %0 %2 = fneg float %0
ret float %2 ret float %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @fneg_double(double %0) { define double @fneg_double(double %0) {
; CHECK-LABEL: fneg_double: ; CHECK-LABEL: fneg_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (1)1 ; CHECK-NEXT: xor %s0, %s0, (1)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = fneg double %0 %2 = fneg double %0
ret double %2 ret double %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @fneg_quad(fp128 %0) { define fp128 @fneg_quad(fp128 %0) {
; CHECK-LABEL: fneg_quad: ; CHECK-LABEL: fneg_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
Show All 12 Lines

llvm/test/CodeGen/VE/Scalar/fp_mul.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @func1(float %a, float %b) { define float @func1(float %a, float %b) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, %s1 ; CHECK-NEXT: fmul.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, %b %r = fmul float %a, %b
ret float %r ret float %r
} }
define double @func2(double %a, double %b) { define double @func2(double %a, double %b) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmul.d %s0, %s0, %s1 ; CHECK-NEXT: fmul.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul double %a, %b %r = fmul double %a, %b
ret double %r ret double %r
} }
define fp128 @func3(fp128 %a, fp128 %b) { define fp128 @func3(fp128 %a, fp128 %b) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmul.q %s0, %s0, %s2 ; CHECK-NEXT: fmul.q %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul fp128 %a, %b %r = fmul fp128 %a, %b
ret fp128 %r ret fp128 %r
} }
define float @func4(float %a) { define float @func4(float %a) {
; CHECK-LABEL: func4: ; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1084227584 ; CHECK-NEXT: lea.sl %s1, 1084227584
; CHECK-NEXT: fmul.s %s0, %s0, %s1 ; CHECK-NEXT: fmul.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, 5.000000e+00 %r = fmul float %a, 5.000000e+00
ret float %r ret float %r
} }
define double @func5(double %a) { define double @func5(double %a) {
; CHECK-LABEL: func5: ; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1075052544 ; CHECK-NEXT: lea.sl %s1, 1075052544
; CHECK-NEXT: fmul.d %s0, %s0, %s1 ; CHECK-NEXT: fmul.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul double %a, 5.000000e+00 %r = fmul double %a, 5.000000e+00
ret double %r ret double %r
} }
define fp128 @func6(fp128 %a) { define fp128 @func6(fp128 %a) {
; CHECK-LABEL: func6: ; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fmul.q %s0, %s0, %s4 ; CHECK-NEXT: fmul.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul fp128 %a, 0xL00000000000000004001400000000000 %r = fmul fp128 %a, 0xL00000000000000004001400000000000
ret fp128 %r ret fp128 %r
} }
define float @func7(float %a) { define float @func7(float %a) {
; CHECK-LABEL: func7: ; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 2139095039 ; CHECK-NEXT: lea.sl %s1, 2139095039
; CHECK-NEXT: fmul.s %s0, %s0, %s1 ; CHECK-NEXT: fmul.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, 0x47EFFFFFE0000000 %r = fmul float %a, 0x47EFFFFFE0000000
ret float %r ret float %r
} }
define double @func8(double %a) { define double @func8(double %a) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1 ; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1) ; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1)
; CHECK-NEXT: fmul.d %s0, %s0, %s1 ; CHECK-NEXT: fmul.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul double %a, 0x7FEFFFFFFFFFFFFF %r = fmul double %a, 0x7FEFFFFFFFFFFFFF
ret double %r ret double %r
} }
define fp128 @func9(fp128 %a) { define fp128 @func9(fp128 %a) {
; CHECK-LABEL: func9: ; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fmul.q %s0, %s0, %s4 ; CHECK-NEXT: fmul.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul fp128 %a, 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF %r = fmul fp128 %a, 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF
ret fp128 %r ret fp128 %r
} }
define float @fmuls_ir(float %a) { define float @fmuls_ir(float %a) {
; CHECK-LABEL: fmuls_ir: ; CHECK-LABEL: fmuls_ir:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, (0)1 ; CHECK-NEXT: fmul.s %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float 0.e+00, %a %r = fmul float 0.e+00, %a
ret float %r ret float %r
} }
define float @fmuls_ri(float %a) { define float @fmuls_ri(float %a) {
; CHECK-LABEL: fmuls_ri: ; CHECK-LABEL: fmuls_ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, (2)1 ; CHECK-NEXT: fmul.s %s0, %s0, (2)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, -2. %r = fmul float %a, -2.
ret float %r ret float %r
} }
define float @fmuls_ri2(float %a) { define float @fmuls_ri2(float %a) {
; CHECK-LABEL: fmuls_ri2: ; CHECK-LABEL: fmuls_ri2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, (3)1 ; CHECK-NEXT: fmul.s %s0, %s0, (3)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, -36893488147419103232. %r = fmul float %a, -36893488147419103232.
ret float %r ret float %r
} }
define float @fmuls_ri3(float %a) { define float @fmuls_ri3(float %a) {
; CHECK-LABEL: fmuls_ri3: ; CHECK-LABEL: fmuls_ri3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, (9)0 ; CHECK-NEXT: fmul.s %s0, %s0, (9)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, 1.175494210692441075487029444849287348827052428745893333857174530571588870475618904265502351336181163787841796875E-38 %r = fmul float %a, 1.175494210692441075487029444849287348827052428745893333857174530571588870475618904265502351336181163787841796875E-38
ret float %r ret float %r
} }

llvm/test/CodeGen/VE/Scalar/fp_sub.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @func1(float %a, float %b) { define float @func1(float %a, float %b) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fsub.s %s0, %s0, %s1 ; CHECK-NEXT: fsub.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fsub float %a, %b %r = fsub float %a, %b
ret float %r ret float %r
} }
define double @func2(double %a, double %b) { define double @func2(double %a, double %b) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fsub.d %s0, %s0, %s1 ; CHECK-NEXT: fsub.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fsub double %a, %b %r = fsub double %a, %b
ret double %r ret double %r
} }
define fp128 @func3(fp128 %a, fp128 %b) { define fp128 @func3(fp128 %a, fp128 %b) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fsub.q %s0, %s0, %s2 ; CHECK-NEXT: fsub.q %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fsub fp128 %a, %b %r = fsub fp128 %a, %b
ret fp128 %r ret fp128 %r
} }
define float @func4(float %a) { define float @func4(float %a) {
; CHECK-LABEL: func4: ; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, -1063256064 ; CHECK-NEXT: lea.sl %s1, -1063256064
; CHECK-NEXT: fadd.s %s0, %s0, %s1 ; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, -5.000000e+00 %r = fadd float %a, -5.000000e+00
ret float %r ret float %r
} }
define double @func5(double %a) { define double @func5(double %a) {
; CHECK-LABEL: func5: ; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, -1072431104 ; CHECK-NEXT: lea.sl %s1, -1072431104
; CHECK-NEXT: fadd.d %s0, %s0, %s1 ; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, -5.000000e+00 %r = fadd double %a, -5.000000e+00
ret double %r ret double %r
} }
define fp128 @func6(fp128 %a) { define fp128 @func6(fp128 %a) {
; CHECK-LABEL: func6: ; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4 ; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xL0000000000000000C001400000000000 %r = fadd fp128 %a, 0xL0000000000000000C001400000000000
ret fp128 %r ret fp128 %r
} }
define float @func7(float %a) { define float @func7(float %a) {
; CHECK-LABEL: func7: ; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, -8388609 ; CHECK-NEXT: lea.sl %s1, -8388609
; CHECK-NEXT: fadd.s %s0, %s0, %s1 ; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, 0xC7EFFFFFE0000000 %r = fadd float %a, 0xC7EFFFFFE0000000
ret float %r ret float %r
} }
define double @func8(double %a) { define double @func8(double %a) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1 ; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, -1048577(, %s1) ; CHECK-NEXT: lea.sl %s1, -1048577(, %s1)
; CHECK-NEXT: fadd.d %s0, %s0, %s1 ; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, 0xFFEFFFFFFFFFFFFF %r = fadd double %a, 0xFFEFFFFFFFFFFFFF
ret double %r ret double %r
} }
define fp128 @func9(fp128 %a) { define fp128 @func9(fp128 %a) {
; CHECK-LABEL: func9: ; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2) ; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2) ; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4 ; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xLFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFF %r = fadd fp128 %a, 0xLFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFF
ret fp128 %r ret fp128 %r
} }
define float @fsubs_ir(float %a) { define float @fsubs_ir(float %a) {
; CHECK-LABEL: fsubs_ir: ; CHECK-LABEL: fsubs_ir:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fsub.s %s0, 0, %s0 ; CHECK-NEXT: fsub.s %s0, 0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fsub float 0.e+00, %a %r = fsub float 0.e+00, %a
ret float %r ret float %r
} }
define float @fsubs_ri(float %a) { define float @fsubs_ri(float %a) {
; CHECK-LABEL: fsubs_ri: ; CHECK-LABEL: fsubs_ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fadd.s %s0, %s0, (2)1 ; CHECK-NEXT: fadd.s %s0, %s0, (2)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = fsub float %a, 2.0e+00 %r = fsub float %a, 2.0e+00
ret float %r ret float %r
} }

llvm/test/CodeGen/VE/Scalar/fp_to_int.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @f2c(float %a) { define signext i8 @f2c(float %a) {
; CHECK-LABEL: f2c: ; CHECK-LABEL: f2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptosi float %a to i8 %conv = fptosi float %a to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @f2s(float %a) { define signext i16 @f2s(float %a) {
; CHECK-LABEL: f2s: ; CHECK-LABEL: f2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptosi float %a to i16 %conv = fptosi float %a to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @f2i(float %a) { define i32 @f2i(float %a) {
; CHECK-LABEL: f2i: ; CHECK-LABEL: f2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptosi float %a to i32 %conv = fptosi float %a to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @f2l(float %a) { define i64 @f2l(float %a) {
; CHECK-LABEL: f2l: ; CHECK-LABEL: f2l:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptosi float %a to i64 %conv = fptosi float %a to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @f2uc(float %a) { define zeroext i8 @f2uc(float %a) {
; CHECK-LABEL: f2uc: ; CHECK-LABEL: f2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptoui float %a to i8 %conv = fptoui float %a to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @f2us(float %a) { define zeroext i16 @f2us(float %a) {
; CHECK-LABEL: f2us: ; CHECK-LABEL: f2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptoui float %a to i16 %conv = fptoui float %a to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @f2ui(float %a) { define i32 @f2ui(float %a) {
; CHECK-LABEL: f2ui: ; CHECK-LABEL: f2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptoui float %a to i32 %conv = fptoui float %a to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @f2ul(float %a) { define i64 @f2ul(float %a) {
; CHECK-LABEL: f2ul: ; CHECK-LABEL: f2ul:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea.sl %s1, 1593835520 ; CHECK-NEXT: lea.sl %s1, 1593835520
; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: fsub.s %s1, %s0, %s1 ; CHECK-NEXT: fsub.s %s1, %s0, %s1
; CHECK-NEXT: cvt.d.s %s1, %s1 ; CHECK-NEXT: cvt.d.s %s1, %s1
; CHECK-NEXT: cvt.l.d.rz %s1, %s1 ; CHECK-NEXT: cvt.l.d.rz %s1, %s1
; CHECK-NEXT: xor %s1, %s1, (1)1 ; CHECK-NEXT: xor %s1, %s1, (1)1
; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: cmov.s.lt %s1, %s0, %s2 ; CHECK-NEXT: cmov.s.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptoui float %a to i64 %conv = fptoui float %a to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @d2c(double %a) { define signext i8 @d2c(double %a) {
; CHECK-LABEL: d2c: ; CHECK-LABEL: d2c:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptosi double %a to i8 %conv = fptosi double %a to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @d2s(double %a) { define signext i16 @d2s(double %a) {
; CHECK-LABEL: d2s: ; CHECK-LABEL: d2s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptosi double %a to i16 %conv = fptosi double %a to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @d2i(double %a) { define i32 @d2i(double %a) {
; CHECK-LABEL: d2i: ; CHECK-LABEL: d2i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptosi double %a to i32 %conv = fptosi double %a to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @d2l(double %a) { define i64 @d2l(double %a) {
; CHECK-LABEL: d2l: ; CHECK-LABEL: d2l:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptosi double %a to i64 %conv = fptosi double %a to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @d2uc(double %a) { define zeroext i8 @d2uc(double %a) {
; CHECK-LABEL: d2uc: ; CHECK-LABEL: d2uc:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptoui double %a to i8 %conv = fptoui double %a to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @d2us(double %a) { define zeroext i16 @d2us(double %a) {
; CHECK-LABEL: d2us: ; CHECK-LABEL: d2us:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0 ; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptoui double %a to i16 %conv = fptoui double %a to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i32 @d2ui(double %a) { define i32 @d2ui(double %a) {
; CHECK-LABEL: d2ui: ; CHECK-LABEL: d2ui:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptoui double %a to i32 %conv = fptoui double %a to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @d2ul(double %a) { define i64 @d2ul(double %a) {
; CHECK-LABEL: d2ul: ; CHECK-LABEL: d2ul:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea.sl %s1, 1138753536 ; CHECK-NEXT: lea.sl %s1, 1138753536
; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: fsub.d %s1, %s0, %s1 ; CHECK-NEXT: fsub.d %s1, %s0, %s1
; CHECK-NEXT: cvt.l.d.rz %s1, %s1 ; CHECK-NEXT: cvt.l.d.rz %s1, %s1
; CHECK-NEXT: xor %s1, %s1, (1)1 ; CHECK-NEXT: xor %s1, %s1, (1)1
; CHECK-NEXT: cvt.l.d.rz %s0, %s0 ; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: cmov.d.lt %s1, %s0, %s2 ; CHECK-NEXT: cmov.d.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = fptoui double %a to i64 %conv = fptoui double %a to i64
ret i64 %conv ret i64 %conv
} }

llvm/test/CodeGen/VE/Scalar/fsin.ll

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
} }
; Function Attrs: nounwind readnone speculatable willreturn ; Function Attrs: nounwind readnone speculatable willreturn
declare fp128 @llvm.sin.f128(fp128) declare fp128 @llvm.sin.f128(fp128)
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @fsin_float_zero() { define float @fsin_float_zero() {
; CHECK-LABEL: fsin_float_zero: ; CHECK-LABEL: fsin_float_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0 ; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 0.000000e+00 ret float 0.000000e+00
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @fsin_double_zero() { define double @fsin_double_zero() {
; CHECK-LABEL: fsin_double_zero: ; CHECK-LABEL: fsin_double_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0 ; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 0.000000e+00 ret double 0.000000e+00
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fp128 @fsin_quad_zero() { define fp128 @fsin_quad_zero() {
; CHECK-LABEL: fsin_quad_zero: ; CHECK-LABEL: fsin_quad_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0)
; CHECK-NEXT: ld %s0, 8(, %s2) ; CHECK-NEXT: ld %s0, 8(, %s2)
; CHECK-NEXT: ld %s1, (, %s2) ; CHECK-NEXT: ld %s1, (, %s2)
; CHECK-NEXT: lea %s2, sinl@lo ; CHECK-NEXT: lea %s2, sinl@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, sinl@hi(, %s2) ; CHECK-NEXT: lea.sl %s12, sinl@hi(, %s2)
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%1 = tail call fast fp128 @llvm.sin.f128(fp128 0xL00000000000000000000000000000000) %1 = tail call fast fp128 @llvm.sin.f128(fp128 0xL00000000000000000000000000000000)
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @fsin_float_const() { define float @fsin_float_const() {
; CHECK-LABEL: fsin_float_const: ; CHECK-LABEL: fsin_float_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -1083652169 ; CHECK-NEXT: lea.sl %s0, -1083652169
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 0xBFED18F6E0000000 ret float 0xBFED18F6E0000000
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @fsin_double_const() { define double @fsin_double_const() {
; CHECK-LABEL: fsin_double_const: ; CHECK-LABEL: fsin_double_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -355355578 ; CHECK-NEXT: lea %s0, -355355578
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, -1074980618(, %s0) ; CHECK-NEXT: lea.sl %s0, -1074980618(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 0xBFED18F6EAD1B446 ret double 0xBFED18F6EAD1B446
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fp128 @fsin_quad_const() { define fp128 @fsin_quad_const() {
; CHECK-LABEL: fsin_quad_const: ; CHECK-LABEL: fsin_quad_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
Show All 12 Lines

llvm/test/CodeGen/VE/Scalar/fsqrt.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
} }
; Function Attrs: nounwind readnone speculatable willreturn ; Function Attrs: nounwind readnone speculatable willreturn
declare fp128 @llvm.sqrt.f128(fp128) declare fp128 @llvm.sqrt.f128(fp128)
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @fsqrt_float_zero() { define float @fsqrt_float_zero() {
; CHECK-LABEL: fsqrt_float_zero: ; CHECK-LABEL: fsqrt_float_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0 ; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 0.000000e+00 ret float 0.000000e+00
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @fsqrt_double_zero() { define double @fsqrt_double_zero() {
; CHECK-LABEL: fsqrt_double_zero: ; CHECK-LABEL: fsqrt_double_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0 ; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 0.000000e+00 ret double 0.000000e+00
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fp128 @fsqrt_quad_zero() { define fp128 @fsqrt_quad_zero() {
; CHECK-LABEL: fsqrt_quad_zero: ; CHECK-LABEL: fsqrt_quad_zero:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0) ; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0)
; CHECK-NEXT: ld %s0, 8(, %s2) ; CHECK-NEXT: ld %s0, 8(, %s2)
; CHECK-NEXT: ld %s1, (, %s2) ; CHECK-NEXT: ld %s1, (, %s2)
; CHECK-NEXT: lea %s2, sqrtl@lo ; CHECK-NEXT: lea %s2, sqrtl@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, sqrtl@hi(, %s2) ; CHECK-NEXT: lea.sl %s12, sqrtl@hi(, %s2)
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%1 = tail call fast fp128 @llvm.sqrt.f128(fp128 0xL00000000000000000000000000000000) %1 = tail call fast fp128 @llvm.sqrt.f128(fp128 0xL00000000000000000000000000000000)
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @fsqrt_float_const() { define float @fsqrt_float_const() {
; CHECK-LABEL: fsqrt_float_const: ; CHECK-LABEL: fsqrt_float_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -4194304 ; CHECK-NEXT: lea.sl %s0, -4194304
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret float 0xFFF8000000000000 ret float 0xFFF8000000000000
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @fsqrt_double_const() { define double @fsqrt_double_const() {
; CHECK-LABEL: fsqrt_double_const: ; CHECK-LABEL: fsqrt_double_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -524288 ; CHECK-NEXT: lea.sl %s0, -524288
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
ret double 0xFFF8000000000000 ret double 0xFFF8000000000000
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define fp128 @fsqrt_quad_const() { define fp128 @fsqrt_quad_const() {
; CHECK-LABEL: fsqrt_quad_const: ; CHECK-LABEL: fsqrt_quad_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
Show All 12 Lines

llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve | FileCheck %s
; RUN: llc < %s -mtriple=ve -relocation-model=pic \
; RUN: | FileCheck -check-prefix=PIC %s
define void @func() {
; CHECK-LABEL: func:
; CHECK: # %bb.0:
; CHECK-NEXT: b.l.t (, %s10)
;
; PIC-LABEL: func:
; PIC: # %bb.0:
; PIC-NEXT: b.l.t (, %s10)
ret void
}
@vi8 = common dso_local local_unnamed_addr global i8 0, align 1
define i8 @func_gv() {
; CHECK-LABEL: func_gv:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: b.l.t (, %s10)
;
; PIC-LABEL: func_gv:
; PIC: # %bb.0:
; PIC-NEXT: st %s9, (, %s11)
; PIC-NEXT: st %s10, 8(, %s11)
; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: or %s9, 0, %s11
; PIC-NEXT: lea %s13, -176
; PIC-NEXT: and %s13, %s13, (32)0
; PIC-NEXT: lea.sl %s11, -1(%s13, %s11)
; PIC-NEXT: brge.l.t %s11, %s8, .LBB1_2
; PIC-NEXT: # %bb.1:
; PIC-NEXT: ld %s61, 24(, %s14)
; PIC-NEXT: or %s62, 0, %s0
; PIC-NEXT: lea %s63, 315
; PIC-NEXT: shm.l %s63, (%s61)
; PIC-NEXT: shm.l %s8, 8(%s61)
; PIC-NEXT: shm.l %s11, 16(%s61)
; PIC-NEXT: monc
; PIC-NEXT: or %s0, 0, %s62
; PIC-NEXT: .LBB1_2:
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; PIC-NEXT: and %s15, %s15, (32)0
; PIC-NEXT: sic %s16
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; PIC-NEXT: lea %s0, vi8@got_lo
; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: lea.sl %s0, vi8@got_hi(, %s0)
; PIC-NEXT: ld %s0, (%s0, %s15)
; PIC-NEXT: ld1b.zx %s0, (, %s0)
; PIC-NEXT: or %s11, 0, %s9
; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: ld %s10, 8(, %s11)
; PIC-NEXT: ld %s9, (, %s11)
; PIC-NEXT: b.l.t (, %s10)
%v = load i8, i8* @vi8, align 1
ret i8 %v
}
define i32 @func_alloca(i32 signext %0) {
; CHECK-LABEL: func_alloca:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s13, -192
; CHECK-NEXT: and %s13, %s13, (32)0
; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: stl %s0, 188(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
;
; PIC-LABEL: func_alloca:
; PIC: # %bb.0:
; PIC-NEXT: st %s9, (, %s11)
; PIC-NEXT: st %s10, 8(, %s11)
; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: or %s9, 0, %s11
; PIC-NEXT: lea %s13, -192
; PIC-NEXT: and %s13, %s13, (32)0
; PIC-NEXT: lea.sl %s11, -1(%s13, %s11)
; PIC-NEXT: brge.l.t %s11, %s8, .LBB2_2
; PIC-NEXT: # %bb.1:
; PIC-NEXT: ld %s61, 24(, %s14)
; PIC-NEXT: or %s62, 0, %s0
; PIC-NEXT: lea %s63, 315
; PIC-NEXT: shm.l %s63, (%s61)
; PIC-NEXT: shm.l %s8, 8(%s61)
; PIC-NEXT: shm.l %s11, 16(%s61)
; PIC-NEXT: monc
; PIC-NEXT: or %s0, 0, %s62
; PIC-NEXT: .LBB2_2:
; PIC-NEXT: stl %s0, 188(, %s11)
; PIC-NEXT: or %s11, 0, %s9
; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: ld %s10, 8(, %s11)
; PIC-NEXT: ld %s9, (, %s11)
; PIC-NEXT: b.l.t (, %s10)
%2 = alloca i32, align 4
store i32 %0, i32* %2, align 4
%3 = load i32, i32* %2, align 4
ret i32 %3
}

llvm/test/CodeGen/VE/Scalar/inlineasm-lea.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
define i64 @lea1a(i64 %x) nounwind { define i64 @lea1a(i64 %x) nounwind {
; CHECK-LABEL: lea1a: ; CHECK-LABEL: lea1a:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s0, (%s0) ; CHECK-NEXT: lea %s0, (%s0)
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea $0, ($1)", "=r,r"(i64 %x) nounwind %asmtmp = tail call i64 asm "lea $0, ($1)", "=r,r"(i64 %x) nounwind
ret i64 %asmtmp ret i64 %asmtmp
} }
define i64 @lea1b(i64 %x) nounwind { define i64 @lea1b(i64 %x) nounwind {
; CHECK-LABEL: lea1b: ; CHECK-LABEL: lea1b:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s0, (, %s0) ; CHECK-NEXT: lea %s0, (, %s0)
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea $0, (, $1)", "=r,r"(i64 %x) nounwind %asmtmp = tail call i64 asm "lea $0, (, $1)", "=r,r"(i64 %x) nounwind
ret i64 %asmtmp ret i64 %asmtmp
} }
define i64 @lea2(i64 %x, i64 %y) nounwind { define i64 @lea2(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: lea2: ; CHECK-LABEL: lea2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s0, (%s0, %s1) ; CHECK-NEXT: lea %s0, (%s0, %s1)
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea $0, ($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind %asmtmp = tail call i64 asm "lea $0, ($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind
ret i64 %asmtmp ret i64 %asmtmp
} }
define i64 @lea3(i64 %x, i64 %y) nounwind { define i64 @lea3(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: lea3: ; CHECK-LABEL: lea3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s0, 2048(%s0, %s1) ; CHECK-NEXT: lea %s0, 2048(%s0, %s1)
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea $0, 2048($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind %asmtmp = tail call i64 asm "lea $0, 2048($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind
ret i64 %asmtmp ret i64 %asmtmp
} }
define i64 @leasl3(i64 %x, i64 %y) nounwind { define i64 @leasl3(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: leasl3: ; CHECK-LABEL: leasl3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lea.sl %s0, 2048(%s1, %s0) ; CHECK-NEXT: lea.sl %s0, 2048(%s1, %s0)
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea.sl $0, 2048($1, $2)", "=r,r,r"(i64 %y, i64 %x) nounwind %asmtmp = tail call i64 asm "lea.sl $0, 2048($1, $2)", "=r,r,r"(i64 %y, i64 %x) nounwind
ret i64 %asmtmp ret i64 %asmtmp
} }

llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst.ll

; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
define void @vld(i8* %p, i64 %i) nounwind { define void @vld(i8* %p, i64 %i) nounwind {
; CHECK-LABEL: vld: ; CHECK-LABEL: vld:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind %lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
ret void ret void
} }
define void @vldvst(i8* %p, i64 %i) nounwind { define void @vldvst(i8* %p, i64 %i) nounwind {
; CHECK-LABEL: vldvst: ; CHECK-LABEL: vldvst:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind %lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
%1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind %1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %1, i8* %p, i64 %i) nounwind tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %1, i8* %p, i64 %i) nounwind
ret void ret void
} }
define void @vld2vst2(i8* %p, i64 %i) nounwind { define void @vld2vst2(i8* %p, i64 %i) nounwind {
; CHECK-LABEL: vld2vst2: ; CHECK-LABEL: vld2vst2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vld %v1, %s1, %s0 ; CHECK-NEXT: vld %v1, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v1, %s1, %s0 ; CHECK-NEXT: vst %v1, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind %lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
%1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind %1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
%2 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind %2 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %1, i8* %p, i64 %i) nounwind tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %1, i8* %p, i64 %i) nounwind
tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %2, i8* %p, i64 %i) nounwind tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %2, i8* %p, i64 %i) nounwind
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/int_to_fp.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @c2f(i8 signext %a) { define float @c2f(i8 signext %a) {
; CHECK-LABEL: c2f: ; CHECK-LABEL: c2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = sitofp i8 %a to float %conv = sitofp i8 %a to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @s2f(i16 signext %a) { define float @s2f(i16 signext %a) {
; CHECK-LABEL: s2f: ; CHECK-LABEL: s2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = sitofp i16 %a to float %conv = sitofp i16 %a to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @i2f(i32 %a) { define float @i2f(i32 %a) {
; CHECK-LABEL: i2f: ; CHECK-LABEL: i2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = sitofp i32 %a to float %conv = sitofp i32 %a to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @l2f(i64 %a) { define float @l2f(i64 %a) {
; CHECK-LABEL: l2f: ; CHECK-LABEL: l2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = sitofp i64 %a to float %conv = sitofp i64 %a to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @uc2f(i8 zeroext %a) { define float @uc2f(i8 zeroext %a) {
; CHECK-LABEL: uc2f: ; CHECK-LABEL: uc2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = uitofp i8 %a to float %conv = uitofp i8 %a to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @us2f(i16 zeroext %a) { define float @us2f(i16 zeroext %a) {
; CHECK-LABEL: us2f: ; CHECK-LABEL: us2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0 ; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = uitofp i16 %a to float %conv = uitofp i16 %a to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @ui2f(i32 %a) { define float @ui2f(i32 %a) {
; CHECK-LABEL: ui2f: ; CHECK-LABEL: ui2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = uitofp i32 %a to float %conv = uitofp i32 %a to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @ul2f(i64 %a) { define float @ul2f(i64 %a) {
; CHECK-LABEL: ul2f: ; CHECK-LABEL: ul2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmps.l %s2, %s0, (0)1 ; CHECK-NEXT: cmps.l %s2, %s0, (0)1
; CHECK-NEXT: cvt.d.l %s1, %s0 ; CHECK-NEXT: cvt.d.l %s1, %s0
; CHECK-NEXT: cvt.s.d %s1, %s1 ; CHECK-NEXT: cvt.s.d %s1, %s1
; CHECK-NEXT: srl %s3, %s0, 1 ; CHECK-NEXT: srl %s3, %s0, 1
; CHECK-NEXT: and %s0, 1, %s0 ; CHECK-NEXT: and %s0, 1, %s0
; CHECK-NEXT: or %s0, %s0, %s3 ; CHECK-NEXT: or %s0, %s0, %s3
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0 ; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: fadd.s %s0, %s0, %s0 ; CHECK-NEXT: fadd.s %s0, %s0, %s0
; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 ; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = uitofp i64 %a to float %conv = uitofp i64 %a to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @c2d(i8 signext %a) { define double @c2d(i8 signext %a) {
; CHECK-LABEL: c2d: ; CHECK-LABEL: c2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = sitofp i8 %a to double %conv = sitofp i8 %a to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @s2d(i16 signext %a) { define double @s2d(i16 signext %a) {
; CHECK-LABEL: s2d: ; CHECK-LABEL: s2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = sitofp i16 %a to double %conv = sitofp i16 %a to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @i2d(i32 %a) { define double @i2d(i32 %a) {
; CHECK-LABEL: i2d: ; CHECK-LABEL: i2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = sitofp i32 %a to double %conv = sitofp i32 %a to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @l2d(i64 %a) { define double @l2d(i64 %a) {
; CHECK-LABEL: l2d: ; CHECK-LABEL: l2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = sitofp i64 %a to double %conv = sitofp i64 %a to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @uc2d(i8 zeroext %a) { define double @uc2d(i8 zeroext %a) {
; CHECK-LABEL: uc2d: ; CHECK-LABEL: uc2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = uitofp i8 %a to double %conv = uitofp i8 %a to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @us2d(i16 zeroext %a) { define double @us2d(i16 zeroext %a) {
; CHECK-LABEL: us2d: ; CHECK-LABEL: us2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0 ; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = uitofp i16 %a to double %conv = uitofp i16 %a to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @ui2d(i32 %a) { define double @ui2d(i32 %a) {
; CHECK-LABEL: ui2d: ; CHECK-LABEL: ui2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cvt.d.l %s0, %s0 ; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = uitofp i32 %a to double %conv = uitofp i32 %a to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @ul2d(i64 %a) { define double @ul2d(i64 %a) {
; CHECK-LABEL: ul2d: ; CHECK-LABEL: ul2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: srl %s1, %s0, 32 ; CHECK-NEXT: srl %s1, %s0, 32
; CHECK-NEXT: lea.sl %s2, 1160773632 ; CHECK-NEXT: lea.sl %s2, 1160773632
; CHECK-NEXT: or %s1, %s1, %s2 ; CHECK-NEXT: or %s1, %s1, %s2
; CHECK-NEXT: lea %s2, 1048576 ; CHECK-NEXT: lea %s2, 1048576
; CHECK-NEXT: lea.sl %s2, -986710016(, %s2) ; CHECK-NEXT: lea.sl %s2, -986710016(, %s2)
; CHECK-NEXT: fadd.d %s1, %s1, %s2 ; CHECK-NEXT: fadd.d %s1, %s1, %s2
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, 1127219200 ; CHECK-NEXT: lea.sl %s2, 1127219200
; CHECK-NEXT: or %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: fadd.d %s0, %s0, %s1 ; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%conv = uitofp i64 %a to double %conv = uitofp i64 %a to double
ret double %conv ret double %conv
} }

llvm/test/CodeGen/VE/Scalar/left_shift.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func1(i8 signext %0, i8 signext %1) { define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i8 %0 to i32 %3 = sext i8 %0 to i32
%4 = sext i8 %1 to i32 %4 = sext i8 %1 to i32
%5 = shl i32 %3, %4 %5 = shl i32 %3, %4
%6 = trunc i32 %5 to i8 %6 = trunc i32 %5 to i8
ret i8 %6 ret i8 %6
} }
define signext i16 @func2(i16 signext %0, i16 signext %1) { define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i16 %0 to i32 %3 = sext i16 %0 to i32
%4 = sext i16 %1 to i32 %4 = sext i16 %1 to i32
%5 = shl i32 %3, %4 %5 = shl i32 %3, %4
%6 = trunc i32 %5 to i16 %6 = trunc i32 %5 to i16
ret i16 %6 ret i16 %6
} }
define i32 @func3(i32 %0, i32 %1) { define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i32 %0, %1 %3 = shl i32 %0, %1
ret i32 %3 ret i32 %3
} }
define i64 @func4(i64 %0, i64 %1) { define i64 @func4(i64 %0, i64 %1) {
; CHECK-LABEL: func4: ; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i64 %0, %1 %3 = shl i64 %0, %1
ret i64 %3 ret i64 %3
} }
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) { define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func6: ; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i8 %0 to i32 %3 = zext i8 %0 to i32
%4 = zext i8 %1 to i32 %4 = zext i8 %1 to i32
%5 = shl i32 %3, %4 %5 = shl i32 %3, %4
%6 = trunc i32 %5 to i8 %6 = trunc i32 %5 to i8
ret i8 %6 ret i8 %6
} }
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) { define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7: ; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i16 %0 to i32 %3 = zext i16 %0 to i32
%4 = zext i16 %1 to i32 %4 = zext i16 %1 to i32
%5 = shl i32 %3, %4 %5 = shl i32 %3, %4
%6 = trunc i32 %5 to i16 %6 = trunc i32 %5 to i16
ret i16 %6 ret i16 %6
} }
define i32 @func8(i32 %0, i32 %1) { define i32 @func8(i32 %0, i32 %1) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i32 %0, %1 %3 = shl i32 %0, %1
ret i32 %3 ret i32 %3
} }
define i64 @func9(i64 %0, i64 %1) { define i64 @func9(i64 %0, i64 %1) {
; CHECK-LABEL: func9: ; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i64 %0, %1 %3 = shl i64 %0, %1
ret i64 %3 ret i64 %3
} }
define signext i8 @func11(i8 signext %0) { define signext i8 @func11(i8 signext %0) {
; CHECK-LABEL: func11: ; CHECK-LABEL: func11:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i8 %0, 5 %2 = shl i8 %0, 5
ret i8 %2 ret i8 %2
} }
define signext i16 @func12(i16 signext %0) { define signext i16 @func12(i16 signext %0) {
; CHECK-LABEL: func12: ; CHECK-LABEL: func12:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i16 %0, 5 %2 = shl i16 %0, 5
ret i16 %2 ret i16 %2
} }
define i32 @func13(i32 %0) { define i32 @func13(i32 %0) {
; CHECK-LABEL: func13: ; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 %0, 5 %2 = shl i32 %0, 5
ret i32 %2 ret i32 %2
} }
define i64 @func14(i64 %0) { define i64 @func14(i64 %0) {
; CHECK-LABEL: func14: ; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 5 ; CHECK-NEXT: sll %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 %0, 5 %2 = shl i64 %0, 5
ret i64 %2 ret i64 %2
} }
define zeroext i8 @func16(i8 zeroext %0) { define zeroext i8 @func16(i8 zeroext %0) {
; CHECK-LABEL: func16: ; CHECK-LABEL: func16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: lea %s1, 224 ; CHECK-NEXT: lea %s1, 224
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i8 %0, 5 %2 = shl i8 %0, 5
ret i8 %2 ret i8 %2
} }
define zeroext i16 @func17(i16 zeroext %0) { define zeroext i16 @func17(i16 zeroext %0) {
; CHECK-LABEL: func17: ; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: lea %s1, 65504 ; CHECK-NEXT: lea %s1, 65504
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i16 %0, 5 %2 = shl i16 %0, 5
ret i16 %2 ret i16 %2
} }
define i32 @func18(i32 %0) { define i32 @func18(i32 %0) {
; CHECK-LABEL: func18: ; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5 ; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 %0, 5 %2 = shl i32 %0, 5
ret i32 %2 ret i32 %2
} }
define i64 @func19(i64 %0) { define i64 @func19(i64 %0) {
; CHECK-LABEL: func19: ; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 5 ; CHECK-NEXT: sll %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 %0, 5 %2 = shl i64 %0, 5
ret i64 %2 ret i64 %2
} }

llvm/test/CodeGen/VE/Scalar/load-align1.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: or %s11, 0, %s9
%addr = alloca i8, align 1 %addr = alloca i8, align 1
%1 = load i8, i8* %addr, align 1 %1 = load i8, i8* %addr, align 1
ret i8 %1 ret i8 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define double @loadf64com() { define double @loadf64com() {
; CHECK-LABEL: loadf64com: ; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 1 %1 = load double, double* @vf64, align 1
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define float @loadf32com() { define float @loadf32com() {
; CHECK-LABEL: loadf32com: ; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0) ; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 1 %1 = load float, float* @vf32, align 1
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() { define i64 @loadi64com() {
; CHECK-LABEL: loadi64com: ; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 1 %1 = load i64, i64* @vi64, align 1
ret i64 %1 ret i64 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() { define i32 @loadi32com() {
; CHECK-LABEL: loadi32com: ; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 1 %1 = load i32, i32* @vi32, align 1
ret i32 %1 ret i32 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() { define i16 @loadi16com() {
; CHECK-LABEL: loadi16com: ; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 1 %1 = load i16, i16* @vi16, align 1
ret i16 %1 ret i16 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() { define i8 @loadi8com() {
; CHECK-LABEL: loadi8com: ; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 1 %1 = load i8, i8* @vi8, align 1
ret i8 %1 ret i8 %1
} }

llvm/test/CodeGen/VE/Scalar/load-align2.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: or %s11, 0, %s9
%addr = alloca i8, align 2 %addr = alloca i8, align 2
%1 = load i8, i8* %addr, align 2 %1 = load i8, i8* %addr, align 2
ret i8 %1 ret i8 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define double @loadf64com() { define double @loadf64com() {
; CHECK-LABEL: loadf64com: ; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 2 %1 = load double, double* @vf64, align 2
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define float @loadf32com() { define float @loadf32com() {
; CHECK-LABEL: loadf32com: ; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0) ; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 2 %1 = load float, float* @vf32, align 2
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() { define i64 @loadi64com() {
; CHECK-LABEL: loadi64com: ; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 2 %1 = load i64, i64* @vi64, align 2
ret i64 %1 ret i64 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() { define i32 @loadi32com() {
; CHECK-LABEL: loadi32com: ; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 2 %1 = load i32, i32* @vi32, align 2
ret i32 %1 ret i32 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() { define i16 @loadi16com() {
; CHECK-LABEL: loadi16com: ; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 2 %1 = load i16, i16* @vi16, align 2
ret i16 %1 ret i16 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() { define i8 @loadi8com() {
; CHECK-LABEL: loadi8com: ; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 2 %1 = load i8, i8* @vi8, align 2
ret i8 %1 ret i8 %1
} }

llvm/test/CodeGen/VE/Scalar/load-align4.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: or %s11, 0, %s9
%addr = alloca i8, align 4 %addr = alloca i8, align 4
%1 = load i8, i8* %addr, align 4 %1 = load i8, i8* %addr, align 4
ret i8 %1 ret i8 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define double @loadf64com() { define double @loadf64com() {
; CHECK-LABEL: loadf64com: ; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 4 %1 = load double, double* @vf64, align 4
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define float @loadf32com() { define float @loadf32com() {
; CHECK-LABEL: loadf32com: ; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0) ; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 4 %1 = load float, float* @vf32, align 4
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() { define i64 @loadi64com() {
; CHECK-LABEL: loadi64com: ; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 4 %1 = load i64, i64* @vi64, align 4
ret i64 %1 ret i64 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() { define i32 @loadi32com() {
; CHECK-LABEL: loadi32com: ; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 4 %1 = load i32, i32* @vi32, align 4
ret i32 %1 ret i32 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() { define i16 @loadi16com() {
; CHECK-LABEL: loadi16com: ; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 4 %1 = load i16, i16* @vi16, align 4
ret i16 %1 ret i16 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() { define i8 @loadi8com() {
; CHECK-LABEL: loadi8com: ; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 4 %1 = load i8, i8* @vi8, align 4
ret i8 %1 ret i8 %1
} }

llvm/test/CodeGen/VE/Scalar/load-align8.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: or %s11, 0, %s9
%addr = alloca i8, align 8 %addr = alloca i8, align 8
%1 = load i8, i8* %addr, align 8 %1 = load i8, i8* %addr, align 8
ret i8 %1 ret i8 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define double @loadf64com() { define double @loadf64com() {
; CHECK-LABEL: loadf64com: ; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 8 %1 = load double, double* @vf64, align 8
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define float @loadf32com() { define float @loadf32com() {
; CHECK-LABEL: loadf32com: ; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0) ; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 8 %1 = load float, float* @vf32, align 8
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() { define i64 @loadi64com() {
; CHECK-LABEL: loadi64com: ; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 8 %1 = load i64, i64* @vi64, align 8
ret i64 %1 ret i64 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() { define i32 @loadi32com() {
; CHECK-LABEL: loadi32com: ; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 8 %1 = load i32, i32* @vi32, align 8
ret i32 %1 ret i32 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() { define i16 @loadi16com() {
; CHECK-LABEL: loadi16com: ; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 8 %1 = load i16, i16* @vi16, align 8
ret i16 %1 ret i16 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() { define i8 @loadi8com() {
; CHECK-LABEL: loadi8com: ; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 8 %1 = load i8, i8* @vi8, align 8
ret i8 %1 ret i8 %1
} }

llvm/test/CodeGen/VE/Scalar/load.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define fp128 @loadf128(fp128* nocapture readonly %0) { define fp128 @loadf128(fp128* nocapture readonly %0) {
; CHECK-LABEL: loadf128: ; CHECK-LABEL: loadf128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s2, 8(, %s0) ; CHECK-NEXT: ld %s2, 8(, %s0)
; CHECK-NEXT: ld %s3, (, %s0) ; CHECK-NEXT: ld %s3, (, %s0)
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3 ; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load fp128, fp128* %0, align 16 %2 = load fp128, fp128* %0, align 16
ret fp128 %2 ret fp128 %2
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define double @loadf64(double* nocapture readonly %0) { define double @loadf64(double* nocapture readonly %0) {
; CHECK-LABEL: loadf64: ; CHECK-LABEL: loadf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load double, double* %0, align 16 %2 = load double, double* %0, align 16
ret double %2 ret double %2
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define float @loadf32(float* nocapture readonly %0) { define float @loadf32(float* nocapture readonly %0) {
; CHECK-LABEL: loadf32: ; CHECK-LABEL: loadf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldu %s0, (, %s0) ; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load float, float* %0, align 16 %2 = load float, float* %0, align 16
ret float %2 ret float %2
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i128 @loadi128(i128* nocapture readonly %0) { define i128 @loadi128(i128* nocapture readonly %0) {
; CHECK-LABEL: loadi128: ; CHECK-LABEL: loadi128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s2, (, %s0) ; CHECK-NEXT: ld %s2, (, %s0)
; CHECK-NEXT: ld %s1, 8(, %s0) ; CHECK-NEXT: ld %s1, 8(, %s0)
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i128, i128* %0, align 16 %2 = load i128, i128* %0, align 16
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi64(i64* nocapture readonly %0) { define i64 @loadi64(i64* nocapture readonly %0) {
; CHECK-LABEL: loadi64: ; CHECK-LABEL: loadi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i64, i64* %0, align 16 %2 = load i64, i64* %0, align 16
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i32 @loadi32(i32* nocapture readonly %0) { define i32 @loadi32(i32* nocapture readonly %0) {
; CHECK-LABEL: loadi32: ; CHECK-LABEL: loadi32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i32, i32* %0, align 16 %2 = load i32, i32* %0, align 16
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi32sext(i32* nocapture readonly %0) { define i64 @loadi32sext(i32* nocapture readonly %0) {
; CHECK-LABEL: loadi32sext: ; CHECK-LABEL: loadi32sext:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i32, i32* %0, align 16 %2 = load i32, i32* %0, align 16
%3 = sext i32 %2 to i64 %3 = sext i32 %2 to i64
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi32zext(i32* nocapture readonly %0) { define i64 @loadi32zext(i32* nocapture readonly %0) {
; CHECK-LABEL: loadi32zext: ; CHECK-LABEL: loadi32zext:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ldl.zx %s0, (, %s0) ; CHECK-NEXT: ldl.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i32, i32* %0, align 16 %2 = load i32, i32* %0, align 16
%3 = zext i32 %2 to i64 %3 = zext i32 %2 to i64
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i16 @loadi16(i16* nocapture readonly %0) { define i16 @loadi16(i16* nocapture readonly %0) {
; CHECK-LABEL: loadi16: ; CHECK-LABEL: loadi16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i16, i16* %0, align 16 %2 = load i16, i16* %0, align 16
ret i16 %2 ret i16 %2
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi16sext(i16* nocapture readonly %0) { define i64 @loadi16sext(i16* nocapture readonly %0) {
; CHECK-LABEL: loadi16sext: ; CHECK-LABEL: loadi16sext:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.sx %s0, (, %s0) ; CHECK-NEXT: ld2b.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i16, i16* %0, align 16 %2 = load i16, i16* %0, align 16
%3 = sext i16 %2 to i64 %3 = sext i16 %2 to i64
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi16zext(i16* nocapture readonly %0) { define i64 @loadi16zext(i16* nocapture readonly %0) {
; CHECK-LABEL: loadi16zext: ; CHECK-LABEL: loadi16zext:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i16, i16* %0, align 16 %2 = load i16, i16* %0, align 16
%3 = zext i16 %2 to i64 %3 = zext i16 %2 to i64
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i8 @loadi8(i8* nocapture readonly %0) { define i8 @loadi8(i8* nocapture readonly %0) {
; CHECK-LABEL: loadi8: ; CHECK-LABEL: loadi8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i8, i8* %0, align 16 %2 = load i8, i8* %0, align 16
ret i8 %2 ret i8 %2
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi8sext(i8* nocapture readonly %0) { define i64 @loadi8sext(i8* nocapture readonly %0) {
; CHECK-LABEL: loadi8sext: ; CHECK-LABEL: loadi8sext:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.sx %s0, (, %s0) ; CHECK-NEXT: ld1b.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i8, i8* %0, align 16 %2 = load i8, i8* %0, align 16
%3 = sext i8 %2 to i64 %3 = sext i8 %2 to i64
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi8zext(i8* nocapture readonly %0) { define i64 @loadi8zext(i8* nocapture readonly %0) {
; CHECK-LABEL: loadi8zext: ; CHECK-LABEL: loadi8zext:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = load i8, i8* %0, align 16 %2 = load i8, i8* %0, align 16
%3 = zext i8 %2 to i64 %3 = zext i8 %2 to i64
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define fp128 @loadf128stk() { define fp128 @loadf128stk() {
; CHECK-LABEL: loadf128stk: ; CHECK-LABEL: loadf128stk:
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/Scalar/load_gv.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
@vi8 = common dso_local local_unnamed_addr global i8 0, align 1 @vi8 = common dso_local local_unnamed_addr global i8 0, align 1
@vi16 = common dso_local local_unnamed_addr global i16 0, align 2 @vi16 = common dso_local local_unnamed_addr global i16 0, align 2
@vi32 = common dso_local local_unnamed_addr global i32 0, align 4 @vi32 = common dso_local local_unnamed_addr global i32 0, align 4
@vi64 = common dso_local local_unnamed_addr global i64 0, align 8 @vi64 = common dso_local local_unnamed_addr global i64 0, align 8
@vi128 = common dso_local local_unnamed_addr global i128 0, align 16 @vi128 = common dso_local local_unnamed_addr global i128 0, align 16
@vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 4 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 4
@vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 8 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 8
@vf128 = common dso_local local_unnamed_addr global fp128 0xL00000000000000000000000000000000, align 16 @vf128 = common dso_local local_unnamed_addr global fp128 0xL00000000000000000000000000000000, align 16
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define fp128 @loadf128com() { define fp128 @loadf128com() {
; CHECK-LABEL: loadf128com: ; CHECK-LABEL: loadf128com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf128@lo ; CHECK-NEXT: lea %s0, vf128@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, vf128@hi(, %s0) ; CHECK-NEXT: lea.sl %s2, vf128@hi(, %s0)
; CHECK-NEXT: ld %s0, 8(, %s2) ; CHECK-NEXT: ld %s0, 8(, %s2)
; CHECK-NEXT: ld %s1, (, %s2) ; CHECK-NEXT: ld %s1, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load fp128, fp128* @vf128, align 16 %1 = load fp128, fp128* @vf128, align 16
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define double @loadf64com() { define double @loadf64com() {
; CHECK-LABEL: loadf64com: ; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo ; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 8 %1 = load double, double* @vf64, align 8
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define float @loadf32com() { define float @loadf32com() {
; CHECK-LABEL: loadf32com: ; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo ; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0) ; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 4 %1 = load float, float* @vf32, align 4
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i128 @loadi128com() { define i128 @loadi128com() {
; CHECK-LABEL: loadi128com: ; CHECK-LABEL: loadi128com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi128@lo ; CHECK-NEXT: lea %s0, vi128@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s1, vi128@hi(, %s0) ; CHECK-NEXT: lea.sl %s1, vi128@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s1) ; CHECK-NEXT: ld %s0, (, %s1)
; CHECK-NEXT: ld %s1, 8(, %s1) ; CHECK-NEXT: ld %s1, 8(, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i128, i128* @vi128, align 16 %1 = load i128, i128* @vi128, align 16
ret i128 %1 ret i128 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() { define i64 @loadi64com() {
; CHECK-LABEL: loadi64com: ; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo ; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0) ; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 8 %1 = load i64, i64* @vi64, align 8
ret i64 %1 ret i64 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() { define i32 @loadi32com() {
; CHECK-LABEL: loadi32com: ; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo ; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0) ; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 4 %1 = load i32, i32* @vi32, align 4
ret i32 %1 ret i32 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() { define i16 @loadi16com() {
; CHECK-LABEL: loadi16com: ; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo ; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0) ; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 2 %1 = load i16, i16* @vi16, align 2
ret i16 %1 ret i16 %1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() { define i8 @loadi8com() {
; CHECK-LABEL: loadi8com: ; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo ; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0) ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 1 %1 = load i8, i8* @vi8, align 1
ret i8 %1 ret i8 %1
} }

llvm/test/CodeGen/VE/Scalar/load_off.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
@bufi8 = global [3 x i8] zeroinitializer, align 1 @bufi8 = global [3 x i8] zeroinitializer, align 1
@bufi16 = global [3 x i16] zeroinitializer, align 2 @bufi16 = global [3 x i16] zeroinitializer, align 2
@bufi32 = global [3 x i32] zeroinitializer, align 4 @bufi32 = global [3 x i32] zeroinitializer, align 4
@bufi64 = global [3 x i64] zeroinitializer, align 8 @bufi64 = global [3 x i64] zeroinitializer, align 8
@bufi128 = global [3 x i128] zeroinitializer, align 16 @bufi128 = global [3 x i128] zeroinitializer, align 16
@buff32 = global [3 x float] zeroinitializer, align 4 @buff32 = global [3 x float] zeroinitializer, align 4
@buff64 = global [3 x double] zeroinitializer, align 8 @buff64 = global [3 x double] zeroinitializer, align 8
@buff128 = global [3 x fp128] zeroinitializer, align 16 @buff128 = global [3 x fp128] zeroinitializer, align 16
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define signext i8 @loadi8s() { define signext i8 @loadi8s() {
; CHECK-LABEL: loadi8s: ; CHECK-LABEL: loadi8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi8@lo ; CHECK-NEXT: lea %s0, bufi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi8@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, bufi8@hi(, %s0)
; CHECK-NEXT: ld1b.sx %s0, 2(, %s0) ; CHECK-NEXT: ld1b.sx %s0, 2(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @bufi8, i64 0, i64 2), align 1 %0 = load i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @bufi8, i64 0, i64 2), align 1
ret i8 %0 ret i8 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define signext i16 @loadi16s() { define signext i16 @loadi16s() {
; CHECK-LABEL: loadi16s: ; CHECK-LABEL: loadi16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi16@lo ; CHECK-NEXT: lea %s0, bufi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi16@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, bufi16@hi(, %s0)
; CHECK-NEXT: ld2b.sx %s0, 4(, %s0) ; CHECK-NEXT: ld2b.sx %s0, 4(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i16, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @bufi16, i64 0, i64 2), align 2 %0 = load i16, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @bufi16, i64 0, i64 2), align 2
ret i16 %0 ret i16 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define signext i32 @loadi32s() { define signext i32 @loadi32s() {
; CHECK-LABEL: loadi32s: ; CHECK-LABEL: loadi32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi32@lo ; CHECK-NEXT: lea %s0, bufi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, bufi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, 8(, %s0) ; CHECK-NEXT: ldl.sx %s0, 8(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @bufi32, i64 0, i64 2), align 4 %0 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @bufi32, i64 0, i64 2), align 4
ret i32 %0 ret i32 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define i64 @loadi64s() { define i64 @loadi64s() {
; CHECK-LABEL: loadi64s: ; CHECK-LABEL: loadi64s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi64@lo ; CHECK-NEXT: lea %s0, bufi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, bufi64@hi(, %s0)
; CHECK-NEXT: ld %s0, 16(, %s0) ; CHECK-NEXT: ld %s0, 16(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i64, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @bufi64, i64 0, i64 2), align 8 %0 = load i64, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @bufi64, i64 0, i64 2), align 8
ret i64 %0 ret i64 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define i128 @loadi128s() { define i128 @loadi128s() {
; CHECK-LABEL: loadi128s: ; CHECK-LABEL: loadi128s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi128@lo ; CHECK-NEXT: lea %s0, bufi128@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s1, bufi128@hi(, %s0) ; CHECK-NEXT: lea.sl %s1, bufi128@hi(, %s0)
; CHECK-NEXT: ld %s0, 32(, %s1) ; CHECK-NEXT: ld %s0, 32(, %s1)
; CHECK-NEXT: ld %s1, 40(, %s1) ; CHECK-NEXT: ld %s1, 40(, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i128, i128* getelementptr inbounds ([3 x i128], [3 x i128]* @bufi128, i64 0, i64 2), align 16 %0 = load i128, i128* getelementptr inbounds ([3 x i128], [3 x i128]* @bufi128, i64 0, i64 2), align 16
ret i128 %0 ret i128 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define zeroext i8 @loadi8z() { define zeroext i8 @loadi8z() {
; CHECK-LABEL: loadi8z: ; CHECK-LABEL: loadi8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi8@lo ; CHECK-NEXT: lea %s0, bufi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi8@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, bufi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, 2(, %s0) ; CHECK-NEXT: ld1b.zx %s0, 2(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @bufi8, i64 0, i64 2), align 1 %0 = load i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @bufi8, i64 0, i64 2), align 1
ret i8 %0 ret i8 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define zeroext i16 @loadi16z() { define zeroext i16 @loadi16z() {
; CHECK-LABEL: loadi16z: ; CHECK-LABEL: loadi16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi16@lo ; CHECK-NEXT: lea %s0, bufi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi16@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, bufi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, 4(, %s0) ; CHECK-NEXT: ld2b.zx %s0, 4(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i16, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @bufi16, i64 0, i64 2), align 2 %0 = load i16, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @bufi16, i64 0, i64 2), align 2
ret i16 %0 ret i16 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define zeroext i32 @loadi32z() { define zeroext i32 @loadi32z() {
; CHECK-LABEL: loadi32z: ; CHECK-LABEL: loadi32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi32@lo ; CHECK-NEXT: lea %s0, bufi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, bufi32@hi(, %s0)
; CHECK-NEXT: ldl.zx %s0, 8(, %s0) ; CHECK-NEXT: ldl.zx %s0, 8(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @bufi32, i64 0, i64 2), align 4 %0 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @bufi32, i64 0, i64 2), align 4
ret i32 %0 ret i32 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define i64 @loadi64z() { define i64 @loadi64z() {
; CHECK-LABEL: loadi64z: ; CHECK-LABEL: loadi64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi64@lo ; CHECK-NEXT: lea %s0, bufi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, bufi64@hi(, %s0)
; CHECK-NEXT: ld %s0, 16(, %s0) ; CHECK-NEXT: ld %s0, 16(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i64, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @bufi64, i64 0, i64 2), align 8 %0 = load i64, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @bufi64, i64 0, i64 2), align 8
ret i64 %0 ret i64 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define i128 @loadi128z() { define i128 @loadi128z() {
; CHECK-LABEL: loadi128z: ; CHECK-LABEL: loadi128z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi128@lo ; CHECK-NEXT: lea %s0, bufi128@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s1, bufi128@hi(, %s0) ; CHECK-NEXT: lea.sl %s1, bufi128@hi(, %s0)
; CHECK-NEXT: ld %s0, 32(, %s1) ; CHECK-NEXT: ld %s0, 32(, %s1)
; CHECK-NEXT: ld %s1, 40(, %s1) ; CHECK-NEXT: ld %s1, 40(, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load i128, i128* getelementptr inbounds ([3 x i128], [3 x i128]* @bufi128, i64 0, i64 2), align 16 %0 = load i128, i128* getelementptr inbounds ([3 x i128], [3 x i128]* @bufi128, i64 0, i64 2), align 16
ret i128 %0 ret i128 %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define float @loadf32() { define float @loadf32() {
; CHECK-LABEL: loadf32: ; CHECK-LABEL: loadf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, buff32@lo ; CHECK-NEXT: lea %s0, buff32@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, buff32@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, buff32@hi(, %s0)
; CHECK-NEXT: ldu %s0, 8(, %s0) ; CHECK-NEXT: ldu %s0, 8(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load float, float* getelementptr inbounds ([3 x float], [3 x float]* @buff32, i64 0, i64 2), align 4 %0 = load float, float* getelementptr inbounds ([3 x float], [3 x float]* @buff32, i64 0, i64 2), align 4
ret float %0 ret float %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define double @loadf64() { define double @loadf64() {
; CHECK-LABEL: loadf64: ; CHECK-LABEL: loadf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, buff64@lo ; CHECK-NEXT: lea %s0, buff64@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, buff64@hi(, %s0) ; CHECK-NEXT: lea.sl %s0, buff64@hi(, %s0)
; CHECK-NEXT: ld %s0, 16(, %s0) ; CHECK-NEXT: ld %s0, 16(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load double, double* getelementptr inbounds ([3 x double], [3 x double]* @buff64, i64 0, i64 2), align 8 %0 = load double, double* getelementptr inbounds ([3 x double], [3 x double]* @buff64, i64 0, i64 2), align 8
ret double %0 ret double %0
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define fp128 @loadf128() { define fp128 @loadf128() {
; CHECK-LABEL: loadf128: ; CHECK-LABEL: loadf128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, buff128@lo ; CHECK-NEXT: lea %s0, buff128@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, buff128@hi(, %s0) ; CHECK-NEXT: lea.sl %s2, buff128@hi(, %s0)
; CHECK-NEXT: ld %s0, 40(, %s2) ; CHECK-NEXT: ld %s0, 40(, %s2)
; CHECK-NEXT: ld %s1, 32(, %s2) ; CHECK-NEXT: ld %s1, 32(, %s2)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
entry: entry:
%0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @buff128, i64 0, i64 2), align 16 %0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @buff128, i64 0, i64 2), align 16
ret fp128 %0 ret fp128 %0
} }

llvm/test/CodeGen/VE/Scalar/loadrri.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
%struct.data = type { [4 x i8] } %struct.data = type { [4 x i8] }
;;; Check basic usage of rri format load instructions. ;;; Check basic usage of rri format load instructions.
;;; Our target is DAG selection mechanism for LD1BSXrri. ;;; Our target is DAG selection mechanism for LD1BSXrri.
;;; We prepared following three styles. ;;; We prepared following three styles.
;;; 1. LD1BSXrri with %reg1 + %reg2 ;;; 1. LD1BSXrri with %reg1 + %reg2
;;; 2. LD1BSXrri with %frame-index + %reg ;;; 2. LD1BSXrri with %frame-index + %reg
;;; 3. LD1BSXrri with %reg + %frame-index ;;; 3. LD1BSXrri with %reg + %frame-index
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define signext i8 @func_rr(%struct.data* nocapture readonly %0, i32 signext %1) { define signext i8 @func_rr(%struct.data* nocapture readonly %0, i32 signext %1) {
; CHECK-LABEL: func_rr: ; CHECK-LABEL: func_rr:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 2 ; CHECK-NEXT: sll %s1, %s1, 2
; CHECK-NEXT: ld1b.sx %s0, (%s1, %s0) ; CHECK-NEXT: ld1b.sx %s0, (%s1, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i32 %1 to i64 %3 = sext i32 %1 to i64
%4 = getelementptr inbounds %struct.data, %struct.data* %0, i64 %3, i32 0, i64 0 %4 = getelementptr inbounds %struct.data, %struct.data* %0, i64 %3, i32 0, i64 0
%5 = load i8, i8* %4, align 1 %5 = load i8, i8* %4, align 1
ret i8 %5 ret i8 %5
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define signext i8 @func_fr(%struct.data* readonly %0, i32 signext %1) { define signext i8 @func_fr(%struct.data* readonly %0, i32 signext %1) {
Show All 38 Lines

llvm/test/CodeGen/VE/Scalar/max.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define double @maxf64(double, double) { define double @maxf64(double, double) {
; CHECK-LABEL: maxf64: ; CHECK-LABEL: maxf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmax.d %s0, %s0, %s1 ; CHECK-NEXT: fmax.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt double %0, %1 %3 = fcmp ogt double %0, %1
%4 = select i1 %3, double %0, double %1 %4 = select i1 %3, double %0, double %1
ret double %4 ret double %4
} }
define double @max2f64(double, double) { define double @max2f64(double, double) {
; CHECK-LABEL: max2f64: ; CHECK-LABEL: max2f64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmax.d %s0, %s0, %s1 ; CHECK-NEXT: fmax.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge double %0, %1 %3 = fcmp oge double %0, %1
%4 = select i1 %3, double %0, double %1 %4 = select i1 %3, double %0, double %1
ret double %4 ret double %4
} }
; VE has no max for unordered comparison ; VE has no max for unordered comparison
define double @maxuf64(double, double) { define double @maxuf64(double, double) {
; CHECK-LABEL: maxuf64: ; CHECK-LABEL: maxuf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.gtnan %s1, %s0, %s2 ; CHECK-NEXT: cmov.d.gtnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt double %0, %1 %3 = fcmp ugt double %0, %1
%4 = select i1 %3, double %0, double %1 %4 = select i1 %3, double %0, double %1
ret double %4 ret double %4
} }
; VE has no max for unordered comparison ; VE has no max for unordered comparison
define double @max2uf64(double, double) { define double @max2uf64(double, double) {
; CHECK-LABEL: max2uf64: ; CHECK-LABEL: max2uf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.genan %s1, %s0, %s2 ; CHECK-NEXT: cmov.d.genan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge double %0, %1 %3 = fcmp uge double %0, %1
%4 = select i1 %3, double %0, double %1 %4 = select i1 %3, double %0, double %1
ret double %4 ret double %4
} }
define float @maxf32(float, float) { define float @maxf32(float, float) {
; CHECK-LABEL: maxf32: ; CHECK-LABEL: maxf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmax.s %s0, %s0, %s1 ; CHECK-NEXT: fmax.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt float %0, %1 %3 = fcmp ogt float %0, %1
%4 = select i1 %3, float %0, float %1 %4 = select i1 %3, float %0, float %1
ret float %4 ret float %4
} }
define float @max2f32(float, float) { define float @max2f32(float, float) {
; CHECK-LABEL: max2f32: ; CHECK-LABEL: max2f32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmax.s %s0, %s0, %s1 ; CHECK-NEXT: fmax.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge float %0, %1 %3 = fcmp oge float %0, %1
%4 = select i1 %3, float %0, float %1 %4 = select i1 %3, float %0, float %1
ret float %4 ret float %4
} }
define float @maxuf32(float, float) { define float @maxuf32(float, float) {
; CHECK-LABEL: maxuf32: ; CHECK-LABEL: maxuf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2 ; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt float %0, %1 %3 = fcmp ugt float %0, %1
%4 = select i1 %3, float %0, float %1 %4 = select i1 %3, float %0, float %1
ret float %4 ret float %4
} }
define float @max2uf32(float, float) { define float @max2uf32(float, float) {
; CHECK-LABEL: max2uf32: ; CHECK-LABEL: max2uf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2 ; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge float %0, %1 %3 = fcmp uge float %0, %1
%4 = select i1 %3, float %0, float %1 %4 = select i1 %3, float %0, float %1
ret float %4 ret float %4
} }
define i64 @maxi64(i64, i64) { define i64 @maxi64(i64, i64) {
; CHECK-LABEL: maxi64: ; CHECK-LABEL: maxi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: maxs.l %s0, %s0, %s1 ; CHECK-NEXT: maxs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i64 %0, %1 %3 = icmp sgt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1 %4 = select i1 %3, i64 %0, i64 %1
ret i64 %4 ret i64 %4
} }
define i64 @max2i64(i64, i64) { define i64 @max2i64(i64, i64) {
; CHECK-LABEL: max2i64: ; CHECK-LABEL: max2i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: maxs.l %s0, %s0, %s1 ; CHECK-NEXT: maxs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i64 %0, %1 %3 = icmp sge i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1 %4 = select i1 %3, i64 %0, i64 %1
ret i64 %4 ret i64 %4
} }
define i64 @maxu64(i64, i64) { define i64 @maxu64(i64, i64) {
; CHECK-LABEL: maxu64: ; CHECK-LABEL: maxu64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1 ; CHECK-NEXT: cmpu.l %s2, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2 ; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i64 %0, %1 %3 = icmp ugt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1 %4 = select i1 %3, i64 %0, i64 %1
ret i64 %4 ret i64 %4
} }
define i64 @max2u64(i64, i64) { define i64 @max2u64(i64, i64) {
; CHECK-LABEL: max2u64: ; CHECK-LABEL: max2u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1 ; CHECK-NEXT: cmpu.l %s2, %s0, %s1
; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2 ; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i64 %0, %1 %3 = icmp uge i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1 %4 = select i1 %3, i64 %0, i64 %1
ret i64 %4 ret i64 %4
} }
define i32 @maxi32(i32, i32) { define i32 @maxi32(i32, i32) {
; CHECK-LABEL: maxi32: ; CHECK-LABEL: maxi32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i32 %0, %1 %3 = icmp sgt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1 %4 = select i1 %3, i32 %0, i32 %1
ret i32 %4 ret i32 %4
} }
define i32 @max2i32(i32, i32) { define i32 @max2i32(i32, i32) {
; CHECK-LABEL: max2i32: ; CHECK-LABEL: max2i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i32 %0, %1 %3 = icmp sge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1 %4 = select i1 %3, i32 %0, i32 %1
ret i32 %4 ret i32 %4
} }
define i32 @maxu32(i32, i32) { define i32 @maxu32(i32, i32) {
; CHECK-LABEL: maxu32: ; CHECK-LABEL: maxu32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1 ; CHECK-NEXT: cmpu.w %s2, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2 ; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i32 %0, %1 %3 = icmp ugt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1 %4 = select i1 %3, i32 %0, i32 %1
ret i32 %4 ret i32 %4
} }
define i32 @max2u32(i32, i32) { define i32 @max2u32(i32, i32) {
; CHECK-LABEL: max2u32: ; CHECK-LABEL: max2u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1 ; CHECK-NEXT: cmpu.w %s2, %s0, %s1
; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2 ; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i32 %0, %1 %3 = icmp uge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1 %4 = select i1 %3, i32 %0, i32 %1
ret i32 %4 ret i32 %4
} }
define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) { define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) {
; CHECK-LABEL: maxi1: ; CHECK-LABEL: maxi1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s1, %s0 ; CHECK-NEXT: or %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %1, true %3 = xor i1 %1, true
%4 = and i1 %3, %0 %4 = and i1 %3, %0
%5 = select i1 %4, i1 %0, i1 %1 %5 = select i1 %4, i1 %0, i1 %1
ret i1 %5 ret i1 %5
} }

llvm/test/CodeGen/VE/Scalar/min.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define double @minf64(double, double) { define double @minf64(double, double) {
; CHECK-LABEL: minf64: ; CHECK-LABEL: minf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmin.d %s0, %s0, %s1 ; CHECK-NEXT: fmin.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt double %0, %1 %3 = fcmp olt double %0, %1
%4 = select i1 %3, double %0, double %1 %4 = select i1 %3, double %0, double %1
ret double %4 ret double %4
} }
define double @min2f64(double, double) { define double @min2f64(double, double) {
; CHECK-LABEL: min2f64: ; CHECK-LABEL: min2f64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmin.d %s0, %s0, %s1 ; CHECK-NEXT: fmin.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole double %0, %1 %3 = fcmp ole double %0, %1
%4 = select i1 %3, double %0, double %1 %4 = select i1 %3, double %0, double %1
ret double %4 ret double %4
} }
define double @minuf64(double, double) { define double @minuf64(double, double) {
; CHECK-LABEL: minuf64: ; CHECK-LABEL: minuf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.ltnan %s1, %s0, %s2 ; CHECK-NEXT: cmov.d.ltnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult double %0, %1 %3 = fcmp ult double %0, %1
%4 = select i1 %3, double %0, double %1 %4 = select i1 %3, double %0, double %1
ret double %4 ret double %4
} }
define double @min2uf64(double, double) { define double @min2uf64(double, double) {
; CHECK-LABEL: min2uf64: ; CHECK-LABEL: min2uf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s2, %s0, %s1 ; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.lenan %s1, %s0, %s2 ; CHECK-NEXT: cmov.d.lenan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule double %0, %1 %3 = fcmp ule double %0, %1
%4 = select i1 %3, double %0, double %1 %4 = select i1 %3, double %0, double %1
ret double %4 ret double %4
} }
define float @minf32(float, float) { define float @minf32(float, float) {
; CHECK-LABEL: minf32: ; CHECK-LABEL: minf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmin.s %s0, %s0, %s1 ; CHECK-NEXT: fmin.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt float %0, %1 %3 = fcmp olt float %0, %1
%4 = select i1 %3, float %0, float %1 %4 = select i1 %3, float %0, float %1
ret float %4 ret float %4
} }
define float @min2f32(float, float) { define float @min2f32(float, float) {
; CHECK-LABEL: min2f32: ; CHECK-LABEL: min2f32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fmin.s %s0, %s0, %s1 ; CHECK-NEXT: fmin.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole float %0, %1 %3 = fcmp ole float %0, %1
%4 = select i1 %3, float %0, float %1 %4 = select i1 %3, float %0, float %1
ret float %4 ret float %4
} }
define float @minuf32(float, float) { define float @minuf32(float, float) {
; CHECK-LABEL: minuf32: ; CHECK-LABEL: minuf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s1, %s0, %s2 ; CHECK-NEXT: cmov.s.ltnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult float %0, %1 %3 = fcmp ult float %0, %1
%4 = select i1 %3, float %0, float %1 %4 = select i1 %3, float %0, float %1
ret float %4 ret float %4
} }
define float @min2uf32(float, float) { define float @min2uf32(float, float) {
; CHECK-LABEL: min2uf32: ; CHECK-LABEL: min2uf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s2, %s0, %s1 ; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s1, %s0, %s2 ; CHECK-NEXT: cmov.s.lenan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule float %0, %1 %3 = fcmp ule float %0, %1
%4 = select i1 %3, float %0, float %1 %4 = select i1 %3, float %0, float %1
ret float %4 ret float %4
} }
define i64 @mini64(i64, i64) { define i64 @mini64(i64, i64) {
; CHECK-LABEL: mini64: ; CHECK-LABEL: mini64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: mins.l %s0, %s0, %s1 ; CHECK-NEXT: mins.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i64 %0, %1 %3 = icmp slt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1 %4 = select i1 %3, i64 %0, i64 %1
ret i64 %4 ret i64 %4
} }
define i64 @min2i64(i64, i64) { define i64 @min2i64(i64, i64) {
; CHECK-LABEL: min2i64: ; CHECK-LABEL: min2i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: mins.l %s0, %s0, %s1 ; CHECK-NEXT: mins.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i64 %0, %1 %3 = icmp sle i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1 %4 = select i1 %3, i64 %0, i64 %1
ret i64 %4 ret i64 %4
} }
define i64 @minu64(i64, i64) { define i64 @minu64(i64, i64) {
; CHECK-LABEL: minu64: ; CHECK-LABEL: minu64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1 ; CHECK-NEXT: cmpu.l %s2, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 ; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i64 %0, %1 %3 = icmp ult i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1 %4 = select i1 %3, i64 %0, i64 %1
ret i64 %4 ret i64 %4
} }
define i64 @min2u64(i64, i64) { define i64 @min2u64(i64, i64) {
; CHECK-LABEL: min2u64: ; CHECK-LABEL: min2u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1 ; CHECK-NEXT: cmpu.l %s2, %s0, %s1
; CHECK-NEXT: cmov.l.le %s1, %s0, %s2 ; CHECK-NEXT: cmov.l.le %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i64 %0, %1 %3 = icmp ule i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1 %4 = select i1 %3, i64 %0, i64 %1
ret i64 %4 ret i64 %4
} }
define i32 @mini32(i32, i32) { define i32 @mini32(i32, i32) {
; CHECK-LABEL: mini32: ; CHECK-LABEL: mini32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1 ; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i32 %0, %1 %3 = icmp slt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1 %4 = select i1 %3, i32 %0, i32 %1
ret i32 %4 ret i32 %4
} }
define i32 @min2i32(i32, i32) { define i32 @min2i32(i32, i32) {
; CHECK-LABEL: min2i32: ; CHECK-LABEL: min2i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1 ; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i32 %0, %1 %3 = icmp sle i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1 %4 = select i1 %3, i32 %0, i32 %1
ret i32 %4 ret i32 %4
} }
define i32 @minu32(i32, i32) { define i32 @minu32(i32, i32) {
; CHECK-LABEL: minu32: ; CHECK-LABEL: minu32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1 ; CHECK-NEXT: cmpu.w %s2, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2 ; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i32 %0, %1 %3 = icmp ult i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1 %4 = select i1 %3, i32 %0, i32 %1
ret i32 %4 ret i32 %4
} }
define i32 @min2u32(i32, i32) { define i32 @min2u32(i32, i32) {
; CHECK-LABEL: min2u32: ; CHECK-LABEL: min2u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1 ; CHECK-NEXT: cmpu.w %s2, %s0, %s1
; CHECK-NEXT: cmov.w.le %s1, %s0, %s2 ; CHECK-NEXT: cmov.w.le %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i32 %0, %1 %3 = icmp ule i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1 %4 = select i1 %3, i32 %0, i32 %1
ret i32 %4 ret i32 %4
} }
define zeroext i1 @mini1(i1 zeroext, i1 zeroext) { define zeroext i1 @mini1(i1 zeroext, i1 zeroext) {
; CHECK-LABEL: mini1: ; CHECK-LABEL: mini1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s1, %s0 ; CHECK-NEXT: and %s2, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, true %3 = xor i1 %0, true
%4 = and i1 %3, %1 %4 = and i1 %3, %1
%5 = select i1 %4, i1 %0, i1 %1 %5 = select i1 %4, i1 %0, i1 %1
ret i1 %5 ret i1 %5
} }

llvm/test/CodeGen/VE/Scalar/multiply.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func8s(i8 signext %a, i8 signext %b) { define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i8 %b, %a %r = mul i8 %b, %a
ret i8 %r ret i8 %r
} }
define signext i16 @func16s(i16 signext %a, i16 signext %b) { define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i16 %b, %a %r = mul i16 %b, %a
ret i16 %r ret i16 %r
} }
define signext i32 @func32s(i32 signext %a, i32 signext %b) { define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul nsw i32 %b, %a %r = mul nsw i32 %b, %a
ret i32 %r ret i32 %r
} }
define i64 @func64(i64 %a, i64 %b) { define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.l %s0, %s1, %s0 ; CHECK-NEXT: muls.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul nsw i64 %b, %a %r = mul nsw i64 %b, %a
ret i64 %r ret i64 %r
} }
define i128 @func128(i128 %a, i128 %b) { define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s1 ; CHECK-NEXT: or %s4, 0, %s1
; CHECK-NEXT: or %s5, 0, %s0 ; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: lea %s0, __multi3@lo ; CHECK-NEXT: lea %s0, __multi3@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s0)
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3 ; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s2, 0, %s5 ; CHECK-NEXT: or %s2, 0, %s5
; CHECK-NEXT: or %s3, 0, %s4 ; CHECK-NEXT: or %s3, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i128 %b, %a %r = mul nsw i128 %b, %a
ret i128 %r ret i128 %r
} }
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i8 %b, %a %r = mul i8 %b, %a
ret i8 %r ret i8 %r
} }
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i16 %b, %a %r = mul i16 %b, %a
ret i16 %r ret i16 %r
} }
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i32 %b, %a %r = mul i32 %b, %a
ret i32 %r ret i32 %r
} }
define i64 @func64z(i64 %a, i64 %b) { define i64 @func64z(i64 %a, i64 %b) {
; CHECK-LABEL: func64z: ; CHECK-LABEL: func64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.l %s0, %s1, %s0 ; CHECK-NEXT: muls.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i64 %b, %a %r = mul i64 %b, %a
ret i64 %r ret i64 %r
} }
define i128 @func128z(i128 %a, i128 %b) { define i128 @func128z(i128 %a, i128 %b) {
; CHECK-LABEL: func128z: ; CHECK-LABEL: func128z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s1 ; CHECK-NEXT: or %s4, 0, %s1
; CHECK-NEXT: or %s5, 0, %s0 ; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: lea %s0, __multi3@lo ; CHECK-NEXT: lea %s0, __multi3@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s0)
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3 ; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s2, 0, %s5 ; CHECK-NEXT: or %s2, 0, %s5
; CHECK-NEXT: or %s3, 0, %s4 ; CHECK-NEXT: or %s3, 0, %s4
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i128 %b, %a %r = mul i128 %b, %a
ret i128 %r ret i128 %r
} }
define signext i8 @funci8s(i8 signext %a) { define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s: ; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i8 %a, 5 %r = mul i8 %a, 5
ret i8 %r ret i8 %r
} }
define signext i16 @funci16s(i16 signext %a) { define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i16 %a, 5 %r = mul i16 %a, 5
ret i16 %r ret i16 %r
} }
define signext i32 @funci32s(i32 signext %a) { define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul nsw i32 %a, 5 %r = mul nsw i32 %a, 5
ret i32 %r ret i32 %r
} }
define i64 @funci64(i64 %a) { define i64 @funci64(i64 %a) {
; CHECK-LABEL: funci64: ; CHECK-LABEL: funci64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.l %s0, 5, %s0 ; CHECK-NEXT: muls.l %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul nsw i64 %a, 5 %r = mul nsw i64 %a, 5
ret i64 %r ret i64 %r
} }
define i128 @funci128(i128 %a) { define i128 @funci128(i128 %a) {
; CHECK-LABEL: funci128: ; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __multi3@lo ; CHECK-NEXT: lea %s2, __multi3@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s2) ; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s2)
; CHECK-NEXT: or %s2, 5, (0)1 ; CHECK-NEXT: or %s2, 5, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i128 %a, 5 %r = mul nsw i128 %a, 5
ret i128 %r ret i128 %r
} }
define zeroext i8 @funci8z(i8 zeroext %a) { define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z: ; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i8 %a, 5 %r = mul i8 %a, 5
ret i8 %r ret i8 %r
} }
define zeroext i16 @funci16z(i16 zeroext %a) { define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i16 %a, 5 %r = mul i16 %a, 5
ret i16 %r ret i16 %r
} }
define zeroext i32 @funci32z(i32 zeroext %a) { define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i32 %a, 5 %r = mul i32 %a, 5
ret i32 %r ret i32 %r
} }
define i64 @funci64z(i64 %a) { define i64 @funci64z(i64 %a) {
; CHECK-LABEL: funci64z: ; CHECK-LABEL: funci64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: muls.l %s0, 5, %s0 ; CHECK-NEXT: muls.l %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = mul i64 %a, 5 %r = mul i64 %a, 5
ret i64 %r ret i64 %r
} }
define i128 @funci128z(i128 %a) { define i128 @funci128z(i128 %a) {
; CHECK-LABEL: funci128z: ; CHECK-LABEL: funci128z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __multi3@lo ; CHECK-NEXT: lea %s2, __multi3@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s2) ; CHECK-NEXT: lea.sl %s12, __multi3@hi(, %s2)
; CHECK-NEXT: or %s2, 5, (0)1 ; CHECK-NEXT: or %s2, 5, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = mul i128 %a, 5 %r = mul i128 %a, 5
ret i128 %r ret i128 %r
} }
define zeroext i32 @funci32z_2(i32 zeroext %a) { define zeroext i32 @funci32z_2(i32 zeroext %a) {
; CHECK-LABEL: funci32z_2: ; CHECK-LABEL: funci32z_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 31 ; CHECK-NEXT: sla.w.sx %s0, %s0, 31
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = shl i32 %a, 31 %r = shl i32 %a, 31
ret i32 %r ret i32 %r
} }
define i64 @funci64_2(i64 %a) { define i64 @funci64_2(i64 %a) {
; CHECK-LABEL: funci64_2: ; CHECK-LABEL: funci64_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 31 ; CHECK-NEXT: sll %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = shl nsw i64 %a, 31 %r = shl nsw i64 %a, 31
ret i64 %r ret i64 %r
} }
define i128 @funci128_2(i128 %a) { define i128 @funci128_2(i128 %a) {
; CHECK-LABEL: funci128_2: ; CHECK-LABEL: funci128_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %s2, %s0, 33 ; CHECK-NEXT: srl %s2, %s0, 33
; CHECK-NEXT: sll %s1, %s1, 31 ; CHECK-NEXT: sll %s1, %s1, 31
; CHECK-NEXT: or %s1, %s1, %s2 ; CHECK-NEXT: or %s1, %s1, %s2
; CHECK-NEXT: sll %s0, %s0, 31 ; CHECK-NEXT: sll %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = shl nsw i128 %a, 31 %r = shl nsw i128 %a, 31
ret i128 %r ret i128 %r
} }

llvm/test/CodeGen/VE/Scalar/nnd.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func8s(i8 signext %a, i8 signext %b) { define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i8 %a, -1 %not = xor i8 %a, -1
%res = and i8 %not, %b %res = and i8 %not, %b
ret i8 %res ret i8 %res
} }
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i8 %a, -1 %not = xor i8 %a, -1
%res = and i8 %b, %not %res = and i8 %b, %not
ret i8 %res ret i8 %res
} }
define signext i8 @funci8s(i8 signext %a) { define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s: ; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 5, (0)1 ; CHECK-NEXT: or %s1, 5, (0)1
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i8 %a, -1 %not = xor i8 %a, -1
%res = and i8 %not, 5 %res = and i8 %not, 5
ret i8 %res ret i8 %res
} }
define zeroext i8 @funci8z(i8 zeroext %a) { define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z: ; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 251 ; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i8 %a, -1 %not = xor i8 %a, -1
%res = and i8 -5, %not %res = and i8 -5, %not
ret i8 %res ret i8 %res
} }
define signext i16 @func16s(i16 signext %a, i16 signext %b) { define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i16 %a, -1 %not = xor i16 %a, -1
%res = and i16 %not, %b %res = and i16 %not, %b
ret i16 %res ret i16 %res
} }
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i16 %a, -1 %not = xor i16 %a, -1
%res = and i16 %b, %not %res = and i16 %b, %not
ret i16 %res ret i16 %res
} }
define signext i16 @funci16s(i16 signext %a) { define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, -1, %s0 ; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i16 %a, -1 %not = xor i16 %a, -1
%res = and i16 %not, 65535 %res = and i16 %not, 65535
ret i16 %res ret i16 %res
} }
define zeroext i16 @funci16z(i16 zeroext %a) { define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, (52)0 ; CHECK-NEXT: nnd %s0, %s0, (52)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i16 %a, -1 %not = xor i16 %a, -1
%res = and i16 4095, %not %res = and i16 4095, %not
ret i16 %res ret i16 %res
} }
define signext i32 @func32s(i32 signext %a, i32 signext %b) { define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i32 %a, -1 %not = xor i32 %a, -1
%res = and i32 %not, %b %res = and i32 %not, %b
ret i32 %res ret i32 %res
} }
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i32 %a, -1 %not = xor i32 %a, -1
%res = and i32 %not, %b %res = and i32 %not, %b
ret i32 %res ret i32 %res
} }
define signext i32 @funci32s(i32 signext %a) { define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, (36)0 ; CHECK-NEXT: nnd %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i32 %a, -1 %not = xor i32 %a, -1
%res = and i32 %not, 268435455 %res = and i32 %not, 268435455
ret i32 %res ret i32 %res
} }
define zeroext i32 @funci32z(i32 zeroext %a) { define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, (36)0 ; CHECK-NEXT: nnd %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i32 %a, -1 %not = xor i32 %a, -1
%res = and i32 %not, 268435455 %res = and i32 %not, 268435455
ret i32 %res ret i32 %res
} }
define i64 @func64(i64 %a, i64 %b) { define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i64 %a, -1 %not = xor i64 %a, -1
%res = and i64 %not, %b %res = and i64 %not, %b
ret i64 %res ret i64 %res
} }
define i64 @func64_2(i64 %a, i64 %b) { define i64 @func64_2(i64 %a, i64 %b) {
; CHECK-LABEL: func64_2: ; CHECK-LABEL: func64_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s1, %s0 ; CHECK-NEXT: nnd %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i64 %b, -1 %not = xor i64 %b, -1
%res = and i64 %not, %a %res = and i64 %not, %a
ret i64 %res ret i64 %res
} }
define i64 @func64i(i64 %a) { define i64 @func64i(i64 %a) {
; CHECK-LABEL: func64i: ; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, (24)0 ; CHECK-NEXT: nnd %s0, %s0, (24)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i64 %a, -1 %not = xor i64 %a, -1
%res = and i64 %not, 1099511627775 %res = and i64 %not, 1099511627775
ret i64 %res ret i64 %res
} }
define i128 @func128(i128 %a, i128 %b) { define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s2 ; CHECK-NEXT: nnd %s0, %s0, %s2
; CHECK-NEXT: nnd %s1, %s1, %s3 ; CHECK-NEXT: nnd %s1, %s1, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i128 %a, -1 %not = xor i128 %a, -1
%res = and i128 %b, %not %res = and i128 %b, %not
ret i128 %res ret i128 %res
} }
define i128 @funci128(i128 %a) { define i128 @funci128(i128 %a) {
; CHECK-LABEL: funci128: ; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 5, (0)1 ; CHECK-NEXT: or %s1, 5, (0)1
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%not = xor i128 %a, -1 %not = xor i128 %a, -1
%res = and i128 %not, 5 %res = and i128 %not, 5
ret i128 %res ret i128 %res
} }
define i64 @func64_nnd_fold(i64 %x, i64 %y, i64 %m) { define i64 @func64_nnd_fold(i64 %x, i64 %y, i64 %m) {
; CHECK-LABEL: func64_nnd_fold: ; CHECK-LABEL: func64_nnd_fold:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s1, %s2, %s1 ; CHECK-NEXT: nnd %s1, %s2, %s1
; CHECK-NEXT: and %s0, %s0, %s2 ; CHECK-NEXT: and %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%D = xor i64 %x, %y %D = xor i64 %x, %y
%A = and i64 %D, %m %A = and i64 %D, %m
%res = xor i64 %A, %y %res = xor i64 %A, %y
ret i64 %res ret i64 %res
} }
define i64 @func64iy_nnd_fold(i64 %x, i64 %m) { define i64 @func64iy_nnd_fold(i64 %x, i64 %m) {
; CHECK-LABEL: func64iy_nnd_fold: ; CHECK-LABEL: func64iy_nnd_fold:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s1, -64, %s1 ; CHECK-NEXT: or %s1, -64, %s1
; CHECK-NEXT: nnd %s0, %s0, %s1 ; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%D = xor i64 %x, -64 %D = xor i64 %x, -64
%A = and i64 %D, %m %A = and i64 %D, %m
%res = xor i64 %A, -64 %res = xor i64 %A, -64
ret i64 %res ret i64 %res
} }
define i64 @func64im_nnd_fold(i64 %x, i64 %y) { define i64 @func64im_nnd_fold(i64 %x, i64 %y) {
; CHECK-LABEL: func64im_nnd_fold: ; CHECK-LABEL: func64im_nnd_fold:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: and %s0, 30, %s0 ; CHECK-NEXT: and %s0, 30, %s0
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%D = xor i64 %x, %y %D = xor i64 %x, %y
%A = and i64 %D, 30 %A = and i64 %D, 30
%res = xor i64 %A, %y %res = xor i64 %A, %y
ret i64 %res ret i64 %res
} }

llvm/test/CodeGen/VE/Scalar/or.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func8s(i8 signext %a, i8 signext %b) { define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i8 %a, %b %res = or i8 %a, %b
ret i8 %res ret i8 %res
} }
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s1, %s0 ; CHECK-NEXT: or %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i8 %b, %a %res = or i8 %b, %a
ret i8 %res ret i8 %res
} }
define signext i8 @funci8s(i8 signext %a) { define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s: ; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 5, %s0 ; CHECK-NEXT: or %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i8 %a, 5 %res = or i8 %a, 5
ret i8 %res ret i8 %res
} }
define zeroext i8 @funci8z(i8 zeroext %a) { define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z: ; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 251 ; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i8 -5, %a %res = or i8 -5, %a
ret i8 %res ret i8 %res
} }
define signext i16 @func16s(i16 signext %a, i16 signext %b) { define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i16 %a, %b %res = or i16 %a, %b
ret i16 %res ret i16 %res
} }
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s1, %s0 ; CHECK-NEXT: or %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i16 %b, %a %res = or i16 %b, %a
ret i16 %res ret i16 %res
} }
define signext i16 @funci16s(i16 signext %a) { define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, -1, (0)1 ; CHECK-NEXT: or %s0, -1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i16 %a, 65535 %res = or i16 %a, 65535
ret i16 %res ret i16 %res
} }
define zeroext i16 @funci16z(i16 zeroext %a) { define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, (52)0 ; CHECK-NEXT: or %s0, %s0, (52)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i16 4095, %a %res = or i16 4095, %a
ret i16 %res ret i16 %res
} }
define signext i32 @func32s(i32 signext %a, i32 signext %b) { define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i32 %a, %b %res = or i32 %a, %b
ret i32 %res ret i32 %res
} }
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i32 %a, %b %res = or i32 %a, %b
ret i32 %res ret i32 %res
} }
define signext i32 @funci32s(i32 signext %a) { define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, (36)0 ; CHECK-NEXT: or %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i32 %a, 268435455 %res = or i32 %a, 268435455
ret i32 %res ret i32 %res
} }
define zeroext i32 @funci32z(i32 zeroext %a) { define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, (36)0 ; CHECK-NEXT: or %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i32 %a, 268435455 %res = or i32 %a, 268435455
ret i32 %res ret i32 %res
} }
define i64 @func64(i64 %a, i64 %b) { define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i64 %a, %b %res = or i64 %a, %b
ret i64 %res ret i64 %res
} }
define i64 @func64i(i64 %a) { define i64 @func64i(i64 %a) {
; CHECK-LABEL: func64i: ; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, (24)0 ; CHECK-NEXT: or %s0, %s0, (24)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i64 %a, 1099511627775 %res = or i64 %a, 1099511627775
ret i64 %res ret i64 %res
} }
define i128 @func128(i128 %a, i128 %b) { define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s2, %s0 ; CHECK-NEXT: or %s0, %s2, %s0
; CHECK-NEXT: or %s1, %s3, %s1 ; CHECK-NEXT: or %s1, %s3, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i128 %b, %a %res = or i128 %b, %a
ret i128 %res ret i128 %res
} }
define i128 @funci128(i128 %a) { define i128 @funci128(i128 %a) {
; CHECK-LABEL: funci128: ; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 5, %s0 ; CHECK-NEXT: or %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = or i128 %a, 5 %res = or i128 %a, 5
ret i128 %res ret i128 %res
} }

llvm/test/CodeGen/VE/Scalar/rem.ll

Show All 10 Lines
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = srem i128 %a, %b %r = srem i128 %a, %b
ret i128 %r ret i128 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @remi64(i64 %a, i64 %b) { define i64 @remi64(i64 %a, i64 %b) {
; CHECK-LABEL: remi64: ; CHECK-LABEL: remi64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s2, %s0, %s1 ; CHECK-NEXT: divs.l %s2, %s0, %s1
; CHECK-NEXT: muls.l %s1, %s2, %s1 ; CHECK-NEXT: muls.l %s1, %s2, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = srem i64 %a, %b %r = srem i64 %a, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @remi32(i32 signext %a, i32 signext %b) { define signext i32 @remi32(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: remi32: ; CHECK-LABEL: remi32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1 ; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = srem i32 %a, %b %r = srem i32 %a, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @remu128(i128 %a, i128 %b) { define i128 @remu128(i128 %a, i128 %b) {
; CHECK-LABEL: remu128: ; CHECK-LABEL: remu128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s4, __umodti3@lo ; CHECK-NEXT: lea %s4, __umodti3@lo
; CHECK-NEXT: and %s4, %s4, (32)0 ; CHECK-NEXT: and %s4, %s4, (32)0
; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s4) ; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s4)
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = urem i128 %a, %b %r = urem i128 %a, %b
ret i128 %r ret i128 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @remu64(i64 %a, i64 %b) { define i64 @remu64(i64 %a, i64 %b) {
; CHECK-LABEL: remu64: ; CHECK-LABEL: remu64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s2, %s0, %s1 ; CHECK-NEXT: divu.l %s2, %s0, %s1
; CHECK-NEXT: muls.l %s1, %s2, %s1 ; CHECK-NEXT: muls.l %s1, %s2, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = urem i64 %a, %b %r = urem i64 %a, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @remu32(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @remu32(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: remu32: ; CHECK-LABEL: remu32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s2, %s0, %s1 ; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = urem i32 %a, %b %r = urem i32 %a, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @remi16(i16 signext %a, i16 signext %b) { define signext i16 @remi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: remi16: ; CHECK-LABEL: remi16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1 ; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%a32 = sext i16 %a to i32 %a32 = sext i16 %a to i32
%b32 = sext i16 %b to i32 %b32 = sext i16 %b to i32
%r32 = srem i32 %a32, %b32 %r32 = srem i32 %a32, %b32
%r = trunc i32 %r32 to i16 %r = trunc i32 %r32 to i16
ret i16 %r ret i16 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: remu16: ; CHECK-LABEL: remu16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s2, %s0, %s1 ; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = urem i16 %a, %b %r = urem i16 %a, %b
ret i16 %r ret i16 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @remi8(i8 signext %a, i8 signext %b) { define signext i8 @remi8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: remi8: ; CHECK-LABEL: remi8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1 ; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%a32 = sext i8 %a to i32 %a32 = sext i8 %a to i32
%b32 = sext i8 %b to i32 %b32 = sext i8 %b to i32
%r32 = srem i32 %a32, %b32 %r32 = srem i32 %a32, %b32
%r = trunc i32 %r32 to i8 %r = trunc i32 %r32 to i8
ret i8 %r ret i8 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @remu8(i8 zeroext %a, i8 zeroext %b) { define zeroext i8 @remu8(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: remu8: ; CHECK-LABEL: remu8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s2, %s0, %s1 ; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = urem i8 %a, %b %r = urem i8 %a, %b
ret i8 %r ret i8 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @remi128ri(i128 %a) { define i128 @remi128ri(i128 %a) {
; CHECK-LABEL: remi128ri: ; CHECK-LABEL: remi128ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __modti3@lo ; CHECK-NEXT: lea %s2, __modti3@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s2) ; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s2)
; CHECK-NEXT: or %s2, 3, (0)1 ; CHECK-NEXT: or %s2, 3, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = srem i128 %a, 3 %r = srem i128 %a, 3
ret i128 %r ret i128 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @remi64ri(i64 %a) { define i64 @remi64ri(i64 %a) {
; CHECK-LABEL: remi64ri: ; CHECK-LABEL: remi64ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s1, %s0, (62)0 ; CHECK-NEXT: divs.l %s1, %s0, (62)0
; CHECK-NEXT: muls.l %s1, 3, %s1 ; CHECK-NEXT: muls.l %s1, 3, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = srem i64 %a, 3 %r = srem i64 %a, 3
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @remi32ri(i32 signext %a) { define signext i32 @remi32ri(i32 signext %a) {
; CHECK-LABEL: remi32ri: ; CHECK-LABEL: remi32ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s1, %s0, (62)0 ; CHECK-NEXT: divs.w.sx %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1 ; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = srem i32 %a, 3 %r = srem i32 %a, 3
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @remu128ri(i128 %a) { define i128 @remu128ri(i128 %a) {
; CHECK-LABEL: remu128ri: ; CHECK-LABEL: remu128ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s2, __umodti3@lo ; CHECK-NEXT: lea %s2, __umodti3@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s2) ; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s2)
; CHECK-NEXT: or %s2, 3, (0)1 ; CHECK-NEXT: or %s2, 3, (0)1
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = urem i128 %a, 3 %r = urem i128 %a, 3
ret i128 %r ret i128 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @remu64ri(i64 %a) { define i64 @remu64ri(i64 %a) {
; CHECK-LABEL: remu64ri: ; CHECK-LABEL: remu64ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s1, %s0, (62)0 ; CHECK-NEXT: divu.l %s1, %s0, (62)0
; CHECK-NEXT: muls.l %s1, 3, %s1 ; CHECK-NEXT: muls.l %s1, 3, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = urem i64 %a, 3 %r = urem i64 %a, 3
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @remu32ri(i32 zeroext %a) { define zeroext i32 @remu32ri(i32 zeroext %a) {
; CHECK-LABEL: remu32ri: ; CHECK-LABEL: remu32ri:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s1, %s0, (62)0 ; CHECK-NEXT: divu.w %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1 ; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = urem i32 %a, 3 %r = urem i32 %a, 3
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @remi128li(i128 %a) { define i128 @remi128li(i128 %a) {
; CHECK-LABEL: remi128li: ; CHECK-LABEL: remi128li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s3, 0, %s1 ; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: or %s2, 0, %s0 ; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: lea %s0, __modti3@lo ; CHECK-NEXT: lea %s0, __modti3@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s0)
; CHECK-NEXT: or %s0, 3, (0)1 ; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%r = srem i128 3, %a %r = srem i128 3, %a
ret i128 %r ret i128 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @remi64li(i64 %a, i64 %b) { define i64 @remi64li(i64 %a, i64 %b) {
; CHECK-LABEL: remi64li: ; CHECK-LABEL: remi64li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s0, 3, %s1 ; CHECK-NEXT: divs.l %s0, 3, %s1
; CHECK-NEXT: muls.l %s0, %s0, %s1 ; CHECK-NEXT: muls.l %s0, %s0, %s1
; CHECK-NEXT: subs.l %s0, 3, %s0 ; CHECK-NEXT: subs.l %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = srem i64 3, %b %r = srem i64 3, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @remi32li(i32 signext %a, i32 signext %b) { define signext i32 @remi32li(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: remi32li: ; CHECK-LABEL: remi32li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, 3, %s1 ; CHECK-NEXT: divs.w.sx %s0, 3, %s1
; CHECK-NEXT: muls.w.sx %s0, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
; CHECK-NEXT: subs.w.sx %s0, 3, %s0 ; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = srem i32 3, %b %r = srem i32 3, %b
ret i32 %r ret i32 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @remu128li(i128) { define i128 @remu128li(i128) {
; CHECK-LABEL: remu128li: ; CHECK-LABEL: remu128li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s3, 0, %s1 ; CHECK-NEXT: or %s3, 0, %s1
; CHECK-NEXT: or %s2, 0, %s0 ; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: lea %s0, __umodti3@lo ; CHECK-NEXT: lea %s0, __umodti3@lo
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s0) ; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s0)
; CHECK-NEXT: or %s0, 3, (0)1 ; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = urem i128 3, %0 %2 = urem i128 3, %0
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @remu64li(i64 %a, i64 %b) { define i64 @remu64li(i64 %a, i64 %b) {
; CHECK-LABEL: remu64li: ; CHECK-LABEL: remu64li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s0, 3, %s1 ; CHECK-NEXT: divu.l %s0, 3, %s1
; CHECK-NEXT: muls.l %s0, %s0, %s1 ; CHECK-NEXT: muls.l %s0, %s0, %s1
; CHECK-NEXT: subs.l %s0, 3, %s0 ; CHECK-NEXT: subs.l %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = urem i64 3, %b %r = urem i64 3, %b
ret i64 %r ret i64 %r
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @remu32li(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @remu32li(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: remu32li: ; CHECK-LABEL: remu32li:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, 3, %s1 ; CHECK-NEXT: divu.w %s0, 3, %s1
; CHECK-NEXT: muls.w.sx %s0, %s0, %s1 ; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
; CHECK-NEXT: subs.w.sx %s0, 3, %s0 ; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%r = urem i32 3, %b %r = urem i32 3, %b
ret i32 %r ret i32 %r
} }

llvm/test/CodeGen/VE/Scalar/right_shift.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func1(i8 signext %0, i8 signext %1) { define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i8 %0 to i32 %3 = sext i8 %0 to i32
%4 = sext i8 %1 to i32 %4 = sext i8 %1 to i32
%5 = ashr i32 %3, %4 %5 = ashr i32 %3, %4
%6 = trunc i32 %5 to i8 %6 = trunc i32 %5 to i8
ret i8 %6 ret i8 %6
} }
define signext i16 @func2(i16 signext %0, i16 signext %1) { define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i16 %0 to i32 %3 = sext i16 %0 to i32
%4 = sext i16 %1 to i32 %4 = sext i16 %1 to i32
%5 = ashr i32 %3, %4 %5 = ashr i32 %3, %4
%6 = trunc i32 %5 to i16 %6 = trunc i32 %5 to i16
ret i16 %6 ret i16 %6
} }
define i32 @func3(i32 %0, i32 %1) { define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = ashr i32 %0, %1 %3 = ashr i32 %0, %1
ret i32 %3 ret i32 %3
} }
define i64 @func4(i64 %0, i64 %1) { define i64 @func4(i64 %0, i64 %1) {
; CHECK-LABEL: func4: ; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, %s1 ; CHECK-NEXT: sra.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = ashr i64 %0, %1 %3 = ashr i64 %0, %1
ret i64 %3 ret i64 %3
} }
define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) { define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func7: ; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i8 %0 to i32 %3 = zext i8 %0 to i32
%4 = zext i8 %1 to i32 %4 = zext i8 %1 to i32
%5 = lshr i32 %3, %4 %5 = lshr i32 %3, %4
%6 = trunc i32 %5 to i8 %6 = trunc i32 %5 to i8
ret i8 %6 ret i8 %6
} }
define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) { define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i16 %0 to i32 %3 = zext i16 %0 to i32
%4 = zext i16 %1 to i32 %4 = zext i16 %1 to i32
%5 = lshr i32 %3, %4 %5 = lshr i32 %3, %4
%6 = trunc i32 %5 to i16 %6 = trunc i32 %5 to i16
ret i16 %6 ret i16 %6
} }
define i32 @func9(i32 %0, i32 %1) { define i32 @func9(i32 %0, i32 %1) {
; CHECK-LABEL: func9: ; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = lshr i32 %0, %1 %3 = lshr i32 %0, %1
ret i32 %3 ret i32 %3
} }
define i64 @func10(i64 %0, i64 %1) { define i64 @func10(i64 %0, i64 %1) {
; CHECK-LABEL: func10: ; CHECK-LABEL: func10:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = lshr i64 %0, %1 %3 = lshr i64 %0, %1
ret i64 %3 ret i64 %3
} }
define signext i8 @func12(i8 signext %0) { define signext i8 @func12(i8 signext %0) {
; CHECK-LABEL: func12: ; CHECK-LABEL: func12:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 5 ; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i8 %0, 5 %2 = ashr i8 %0, 5
ret i8 %2 ret i8 %2
} }
define signext i16 @func13(i16 signext %0) { define signext i16 @func13(i16 signext %0) {
; CHECK-LABEL: func13: ; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 5 ; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i16 %0, 5 %2 = ashr i16 %0, 5
ret i16 %2 ret i16 %2
} }
define i32 @func14(i32 %0) { define i32 @func14(i32 %0) {
; CHECK-LABEL: func14: ; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 5 ; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i32 %0, 5 %2 = ashr i32 %0, 5
ret i32 %2 ret i32 %2
} }
define i64 @func15(i64 %0) { define i64 @func15(i64 %0) {
; CHECK-LABEL: func15: ; CHECK-LABEL: func15:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 5 ; CHECK-NEXT: sra.l %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i64 %0, 5 %2 = ashr i64 %0, 5
ret i64 %2 ret i64 %2
} }
define zeroext i8 @func17(i8 zeroext %0) { define zeroext i8 @func17(i8 zeroext %0) {
; CHECK-LABEL: func17: ; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5 ; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i8 %0, 5 %2 = lshr i8 %0, 5
ret i8 %2 ret i8 %2
} }
define zeroext i16 @func18(i16 zeroext %0) { define zeroext i16 @func18(i16 zeroext %0) {
; CHECK-LABEL: func18: ; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5 ; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i16 %0, 5 %2 = lshr i16 %0, 5
ret i16 %2 ret i16 %2
} }
define i32 @func19(i32 %0) { define i32 @func19(i32 %0) {
; CHECK-LABEL: func19: ; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5 ; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i32 %0, 5 %2 = lshr i32 %0, 5
ret i32 %2 ret i32 %2
} }
define i64 @func20(i64 %0) { define i64 @func20(i64 %0) {
; CHECK-LABEL: func20: ; CHECK-LABEL: func20:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s0, 5 ; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i64 %0, 5 %2 = lshr i64 %0, 5
ret i64 %2 ret i64 %2
} }

llvm/test/CodeGen/VE/Scalar/rotl.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define i64 @func1(i64 %a, i32 %b) { define i64 @func1(i64 %a, i32 %b) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s2, %s0, %s1 ; CHECK-NEXT: sll %s2, %s0, %s1
; CHECK-NEXT: lea %s3, 64 ; CHECK-NEXT: lea %s3, 64
; CHECK-NEXT: subs.w.sx %s1, %s3, %s1 ; CHECK-NEXT: subs.w.sx %s1, %s3, %s1
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%b64 = zext i32 %b to i64 %b64 = zext i32 %b to i64
%a.sl = shl i64 %a, %b64 %a.sl = shl i64 %a, %b64
%b.inv = sub nsw i32 64, %b %b.inv = sub nsw i32 64, %b
%b.inv64 = zext i32 %b.inv to i64 %b.inv64 = zext i32 %b.inv to i64
%a.sr = lshr i64 %a, %b.inv64 %a.sr = lshr i64 %a, %b.inv64
%r = or i64 %a.sr, %a.sl %r = or i64 %a.sr, %a.sl
ret i64 %r ret i64 %r
} }
define i32 @func2(i32 %a, i32 %b) { define i32 @func2(i32 %a, i32 %b) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s2, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s2, %s0, %s1
; CHECK-NEXT: subs.w.sx %s1, 32, %s1 ; CHECK-NEXT: subs.w.sx %s1, 32, %s1
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%a.sl = shl i32 %a, %b %a.sl = shl i32 %a, %b
%b.inv = sub nsw i32 32, %b %b.inv = sub nsw i32 32, %b
%a.sr = lshr i32 %a, %b.inv %a.sr = lshr i32 %a, %b.inv
%r = or i32 %a.sr, %a.sl %r = or i32 %a.sr, %a.sl
ret i32 %r ret i32 %r
} }

llvm/test/CodeGen/VE/Scalar/rotr.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define i64 @func1(i64 %a, i32 %b) { define i64 @func1(i64 %a, i32 %b) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %s2, %s0, %s1 ; CHECK-NEXT: srl %s2, %s0, %s1
; CHECK-NEXT: lea %s3, 64 ; CHECK-NEXT: lea %s3, 64
; CHECK-NEXT: subs.w.sx %s1, %s3, %s1 ; CHECK-NEXT: subs.w.sx %s1, %s3, %s1
; CHECK-NEXT: sll %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%b64 = zext i32 %b to i64 %b64 = zext i32 %b to i64
%a.lr = lshr i64 %a, %b64 %a.lr = lshr i64 %a, %b64
%b.inv = sub nsw i32 64, %b %b.inv = sub nsw i32 64, %b
%b.inv64 = zext i32 %b.inv to i64 %b.inv64 = zext i32 %b.inv to i64
%a.sl = shl i64 %a, %b.inv64 %a.sl = shl i64 %a, %b.inv64
%r = or i64 %a.sl, %a.lr %r = or i64 %a.sl, %a.lr
ret i64 %r ret i64 %r
} }
define i32 @func2(i32 %a, i32 %b) { define i32 @func2(i32 %a, i32 %b) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s0, (32)0 ; CHECK-NEXT: and %s2, %s0, (32)0
; CHECK-NEXT: srl %s2, %s2, %s1 ; CHECK-NEXT: srl %s2, %s2, %s1
; CHECK-NEXT: subs.w.sx %s1, 32, %s1 ; CHECK-NEXT: subs.w.sx %s1, 32, %s1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s0, %s2 ; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%a.lr = lshr i32 %a, %b %a.lr = lshr i32 %a, %b
%b.inv = sub nsw i32 32, %b %b.inv = sub nsw i32 32, %b
%a.sl = shl i32 %a, %b.inv %a.sl = shl i32 %a, %b.inv
%r = or i32 %a.sl, %a.lr %r = or i32 %a.sl, %a.lr
ret i32 %r ret i32 %r
} }

llvm/test/CodeGen/VE/Scalar/select.ll

Show All 35 Lines
;;; %X = select i1 true, i8 17, i8 42 ; yields i8:17 ;;; %X = select i1 true, i8 17, i8 42 ; yields i8:17
;;; ;;;
;;; Note: ;;; Note:
;;; We test only i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128 ;;; We test only i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_i1_var(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2) { define zeroext i1 @select_i1_var(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2) {
; CHECK-LABEL: select_i1_var: ; CHECK-LABEL: select_i1_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i1 %1, i1 %2 %4 = select i1 %0, i1 %1, i1 %2
ret i1 %4 ret i1 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_i8_var(i1 zeroext %0, i8 signext %1, i8 signext %2) { define signext i8 @select_i8_var(i1 zeroext %0, i8 signext %1, i8 signext %2) {
; CHECK-LABEL: select_i8_var: ; CHECK-LABEL: select_i8_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i8 %1, i8 %2 %4 = select i1 %0, i8 %1, i8 %2
ret i8 %4 ret i8 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_u8_var(i1 zeroext %0, i8 zeroext %1, i8 zeroext %2) { define zeroext i8 @select_u8_var(i1 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
; CHECK-LABEL: select_u8_var: ; CHECK-LABEL: select_u8_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i8 %1, i8 %2 %4 = select i1 %0, i8 %1, i8 %2
ret i8 %4 ret i8 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_i16_var(i1 zeroext %0, i16 signext %1, i16 signext %2) { define signext i16 @select_i16_var(i1 zeroext %0, i16 signext %1, i16 signext %2) {
; CHECK-LABEL: select_i16_var: ; CHECK-LABEL: select_i16_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i16 %1, i16 %2 %4 = select i1 %0, i16 %1, i16 %2
ret i16 %4 ret i16 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_u16_var(i1 zeroext %0, i16 zeroext %1, i16 zeroext %2) { define zeroext i16 @select_u16_var(i1 zeroext %0, i16 zeroext %1, i16 zeroext %2) {
; CHECK-LABEL: select_u16_var: ; CHECK-LABEL: select_u16_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i16 %1, i16 %2 %4 = select i1 %0, i16 %1, i16 %2
ret i16 %4 ret i16 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_i32_var(i1 zeroext %0, i32 signext %1, i32 signext %2) { define signext i32 @select_i32_var(i1 zeroext %0, i32 signext %1, i32 signext %2) {
; CHECK-LABEL: select_i32_var: ; CHECK-LABEL: select_i32_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i32 %1, i32 %2 %4 = select i1 %0, i32 %1, i32 %2
ret i32 %4 ret i32 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_u32_var(i1 zeroext %0, i32 zeroext %1, i32 zeroext %2) { define zeroext i32 @select_u32_var(i1 zeroext %0, i32 zeroext %1, i32 zeroext %2) {
; CHECK-LABEL: select_u32_var: ; CHECK-LABEL: select_u32_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i32 %1, i32 %2 %4 = select i1 %0, i32 %1, i32 %2
ret i32 %4 ret i32 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_i64_var(i1 zeroext %0, i64 %1, i64 %2) { define i64 @select_i64_var(i1 zeroext %0, i64 %1, i64 %2) {
; CHECK-LABEL: select_i64_var: ; CHECK-LABEL: select_i64_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i64 %1, i64 %2 %4 = select i1 %0, i64 %1, i64 %2
ret i64 %4 ret i64 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_u64_var(i1 zeroext %0, i64 %1, i64 %2) { define i64 @select_u64_var(i1 zeroext %0, i64 %1, i64 %2) {
; CHECK-LABEL: select_u64_var: ; CHECK-LABEL: select_u64_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i64 %1, i64 %2 %4 = select i1 %0, i64 %1, i64 %2
ret i64 %4 ret i64 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_i128_var(i1 zeroext %0, i128 %1, i128 %2) { define i128 @select_i128_var(i1 zeroext %0, i128 %1, i128 %2) {
; CHECK-LABEL: select_i128_var: ; CHECK-LABEL: select_i128_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s1, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i128 %1, i128 %2 %4 = select i1 %0, i128 %1, i128 %2
ret i128 %4 ret i128 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_u128_var(i1 zeroext %0, i128 %1, i128 %2) { define i128 @select_u128_var(i1 zeroext %0, i128 %1, i128 %2) {
; CHECK-LABEL: select_u128_var: ; CHECK-LABEL: select_u128_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s1, 0, %s4 ; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i128 %1, i128 %2 %4 = select i1 %0, i128 %1, i128 %2
ret i128 %4 ret i128 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_float_var(i1 zeroext %0, float %1, float %2) { define float @select_float_var(i1 zeroext %0, float %1, float %2) {
; CHECK-LABEL: select_float_var: ; CHECK-LABEL: select_float_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select fast i1 %0, float %1, float %2 %4 = select fast i1 %0, float %1, float %2
ret float %4 ret float %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_double_var(i1 zeroext %0, double %1, double %2) { define double @select_double_var(i1 zeroext %0, double %1, double %2) {
; CHECK-LABEL: select_double_var: ; CHECK-LABEL: select_double_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select fast i1 %0, double %1, double %2 %4 = select fast i1 %0, double %1, double %2
ret double %4 ret double %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_quad_var(i1 zeroext %0, fp128 %1, fp128 %2) { define fp128 @select_quad_var(i1 zeroext %0, fp128 %1, fp128 %2) {
; CHECK-LABEL: select_quad_var: ; CHECK-LABEL: select_quad_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = select fast i1 %0, fp128 %1, fp128 %2 %4 = select fast i1 %0, fp128 %1, fp128 %2
ret fp128 %4 ret fp128 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_i1_mimm(i1 zeroext %0, i1 zeroext %1) { define zeroext i1 @select_i1_mimm(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: select_i1_mimm: ; CHECK-LABEL: select_i1_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = or i1 %0, %1 %3 = or i1 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_i8_mimm(i1 zeroext %0, i8 signext %1) { define signext i8 @select_i8_mimm(i1 zeroext %0, i8 signext %1) {
; CHECK-LABEL: select_i8_mimm: ; CHECK-LABEL: select_i8_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (57)1, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (57)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i8 -128, i8 %1 %3 = select i1 %0, i8 -128, i8 %1
ret i8 %3 ret i8 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_u8_mimm(i1 zeroext %0, i8 zeroext %1) { define zeroext i8 @select_u8_mimm(i1 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: select_u8_mimm: ; CHECK-LABEL: select_u8_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (57)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (57)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i8 127, i8 %1 %3 = select i1 %0, i8 127, i8 %1
ret i8 %3 ret i8 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_i16_mimm(i1 zeroext %0, i16 signext %1) { define signext i16 @select_i16_mimm(i1 zeroext %0, i16 signext %1) {
; CHECK-LABEL: select_i16_mimm: ; CHECK-LABEL: select_i16_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (49)1, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (49)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i16 -32768, i16 %1 %3 = select i1 %0, i16 -32768, i16 %1
ret i16 %3 ret i16 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_u16_mimm(i1 zeroext %0, i16 zeroext %1) { define zeroext i16 @select_u16_mimm(i1 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: select_u16_mimm: ; CHECK-LABEL: select_u16_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (49)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (49)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i16 32767, i16 %1 %3 = select i1 %0, i16 32767, i16 %1
ret i16 %3 ret i16 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_i32_mimm(i1 zeroext %0, i32 signext %1) { define signext i32 @select_i32_mimm(i1 zeroext %0, i32 signext %1) {
; CHECK-LABEL: select_i32_mimm: ; CHECK-LABEL: select_i32_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i32 65535, i32 %1 %3 = select i1 %0, i32 65535, i32 %1
ret i32 %3 ret i32 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_u32_mimm(i1 zeroext %0, i32 zeroext %1) { define zeroext i32 @select_u32_mimm(i1 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: select_u32_mimm: ; CHECK-LABEL: select_u32_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i32 65535, i32 %1 %3 = select i1 %0, i32 65535, i32 %1
ret i32 %3 ret i32 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_i64_mimm(i1 zeroext %0, i64 %1) { define i64 @select_i64_mimm(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_i64_mimm: ; CHECK-LABEL: select_i64_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i64 65535, i64 %1 %3 = select i1 %0, i64 65535, i64 %1
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_u64_mimm(i1 zeroext %0, i64 %1) { define i64 @select_u64_mimm(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_u64_mimm: ; CHECK-LABEL: select_u64_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i64 65535, i64 %1 %3 = select i1 %0, i64 65535, i64 %1
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_i128_mimm(i1 zeroext %0, i128 %1) { define i128 @select_i128_mimm(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_i128_mimm: ; CHECK-LABEL: select_i128_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s1, 0, %s2 ; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i128 65535, i128 %1 %3 = select i1 %0, i128 65535, i128 %1
ret i128 %3 ret i128 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_u128_mimm(i1 zeroext %0, i128 %1) { define i128 @select_u128_mimm(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_u128_mimm: ; CHECK-LABEL: select_u128_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0 ; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s1, 0, %s2 ; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i128 65535, i128 %1 %3 = select i1 %0, i128 65535, i128 %1
ret i128 %3 ret i128 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_float_mimm(i1 zeroext %0, float %1) { define float @select_float_mimm(i1 zeroext %0, float %1) {
; CHECK-LABEL: select_float_mimm: ; CHECK-LABEL: select_float_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, float -2.000000e+00, float %1 %3 = select i1 %0, float -2.000000e+00, float %1
ret float %3 ret float %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_double_mimm(i1 zeroext %0, double %1) { define double @select_double_mimm(i1 zeroext %0, double %1) {
; CHECK-LABEL: select_double_mimm: ; CHECK-LABEL: select_double_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select fast i1 %0, double -2.000000e+00, double %1 %3 = select fast i1 %0, double -2.000000e+00, double %1
ret double %3 ret double %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_quad_mimm(i1 zeroext %0, fp128 %1) { define fp128 @select_quad_mimm(i1 zeroext %0, fp128 %1) {
; CHECK-LABEL: select_quad_mimm: ; CHECK-LABEL: select_quad_mimm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
; CHECK-NEXT: ld %s4, 8(, %s1) ; CHECK-NEXT: ld %s4, 8(, %s1)
; CHECK-NEXT: ld %s5, (, %s1) ; CHECK-NEXT: ld %s5, (, %s1)
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3 ; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select fast i1 %0, fp128 0xL0000000000000000C000000000000000, fp128 %1 %3 = select fast i1 %0, fp128 0xL0000000000000000C000000000000000, fp128 %1
ret fp128 %3 ret fp128 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_mimm_i1(i1 zeroext %0, i1 zeroext %1) { define zeroext i1 @select_mimm_i1(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: select_mimm_i1: ; CHECK-LABEL: select_mimm_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, 1, %s0 ; CHECK-NEXT: xor %s0, 1, %s0
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, true %3 = xor i1 %0, true
%4 = or i1 %3, %1 %4 = or i1 %3, %1
ret i1 %4 ret i1 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_mimm_i8(i1 zeroext %0, i8 signext %1) { define signext i8 @select_mimm_i8(i1 zeroext %0, i8 signext %1) {
; CHECK-LABEL: select_mimm_i8: ; CHECK-LABEL: select_mimm_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (57)1, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (57)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i8 %1, i8 -128 %3 = select i1 %0, i8 %1, i8 -128
ret i8 %3 ret i8 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_mimm_u8(i1 zeroext %0, i8 zeroext %1) { define zeroext i8 @select_mimm_u8(i1 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: select_mimm_u8: ; CHECK-LABEL: select_mimm_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (57)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (57)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i8 %1, i8 127 %3 = select i1 %0, i8 %1, i8 127
ret i8 %3 ret i8 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_mimm_i16(i1 zeroext %0, i16 signext %1) { define signext i16 @select_mimm_i16(i1 zeroext %0, i16 signext %1) {
; CHECK-LABEL: select_mimm_i16: ; CHECK-LABEL: select_mimm_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (49)1, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (49)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i16 %1, i16 -32768 %3 = select i1 %0, i16 %1, i16 -32768
ret i16 %3 ret i16 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_mimm_u16(i1 zeroext %0, i16 zeroext %1) { define zeroext i16 @select_mimm_u16(i1 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: select_mimm_u16: ; CHECK-LABEL: select_mimm_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (49)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (49)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i16 %1, i16 32767 %3 = select i1 %0, i16 %1, i16 32767
ret i16 %3 ret i16 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_mimm_i32(i1 zeroext %0, i32 signext %1) { define signext i32 @select_mimm_i32(i1 zeroext %0, i32 signext %1) {
; CHECK-LABEL: select_mimm_i32: ; CHECK-LABEL: select_mimm_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i32 %1, i32 65535 %3 = select i1 %0, i32 %1, i32 65535
ret i32 %3 ret i32 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_mimm_u32(i1 zeroext %0, i32 zeroext %1) { define zeroext i32 @select_mimm_u32(i1 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: select_mimm_u32: ; CHECK-LABEL: select_mimm_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i32 %1, i32 65535 %3 = select i1 %0, i32 %1, i32 65535
ret i32 %3 ret i32 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_mimm_i64(i1 zeroext %0, i64 %1) { define i64 @select_mimm_i64(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_mimm_i64: ; CHECK-LABEL: select_mimm_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i64 %1, i64 65535 %3 = select i1 %0, i64 %1, i64 65535
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_mimm_u64(i1 zeroext %0, i64 %1) { define i64 @select_mimm_u64(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_mimm_u64: ; CHECK-LABEL: select_mimm_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i64 %1, i64 65535 %3 = select i1 %0, i64 %1, i64 65535
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_mimm_i128(i1 zeroext %0, i128 %1) { define i128 @select_mimm_i128(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_mimm_i128: ; CHECK-LABEL: select_mimm_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0 ; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s1, 0, %s2 ; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i128 %1, i128 65535 %3 = select i1 %0, i128 %1, i128 65535
ret i128 %3 ret i128 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_mimm_u128(i1 zeroext %0, i128 %1) { define i128 @select_mimm_u128(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_mimm_u128: ; CHECK-LABEL: select_mimm_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0 ; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s1, 0, %s2 ; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i128 %1, i128 65535 %3 = select i1 %0, i128 %1, i128 65535
ret i128 %3 ret i128 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_mimm_float(i1 zeroext %0, float %1) { define float @select_mimm_float(i1 zeroext %0, float %1) {
; CHECK-LABEL: select_mimm_float: ; CHECK-LABEL: select_mimm_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, float %1, float -2.000000e+00 %3 = select i1 %0, float %1, float -2.000000e+00
ret float %3 ret float %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_mimm_double(i1 zeroext %0, double %1) { define double @select_mimm_double(i1 zeroext %0, double %1) {
; CHECK-LABEL: select_mimm_double: ; CHECK-LABEL: select_mimm_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1 ; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select fast i1 %0, double %1, double -2.000000e+00 %3 = select fast i1 %0, double %1, double -2.000000e+00
ret double %3 ret double %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_mimm_quad(i1 zeroext %0, fp128 %1) { define fp128 @select_mimm_quad(i1 zeroext %0, fp128 %1) {
; CHECK-LABEL: select_mimm_quad: ; CHECK-LABEL: select_mimm_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo ; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
; CHECK-NEXT: ld %s4, 8(, %s1) ; CHECK-NEXT: ld %s4, 8(, %s1)
; CHECK-NEXT: ld %s5, (, %s1) ; CHECK-NEXT: ld %s5, (, %s1)
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = select fast i1 %0, fp128 %1, fp128 0xL0000000000000000C000000000000000 %3 = select fast i1 %0, fp128 %1, fp128 0xL0000000000000000C000000000000000
ret fp128 %3 ret fp128 %3
} }

llvm/test/CodeGen/VE/Scalar/select_cc.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
;;; Test all combination of input type and output type among following types. ;;; Test all combination of input type and output type among following types.
;;; ;;;
;;; Types: ;;; Types:
;;; i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128 ;;; i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_i1_i1(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_i1_i1(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i1_i1: ; CHECK-LABEL: select_cc_i1_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i1 %3, i1 %2 %6 = select i1 %5, i1 %3, i1 %2
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_i8_i1(i8 signext %0, i8 signext %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_i8_i1(i8 signext %0, i8 signext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i8_i1: ; CHECK-LABEL: select_cc_i8_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_u8_i1(i8 zeroext %0, i8 zeroext %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_u8_i1(i8 zeroext %0, i8 zeroext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_u8_i1: ; CHECK-LABEL: select_cc_u8_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_i16_i1(i16 signext %0, i16 signext %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_i16_i1(i16 signext %0, i16 signext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i16_i1: ; CHECK-LABEL: select_cc_i16_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_u16_i1(i16 zeroext %0, i16 zeroext %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_u16_i1(i16 zeroext %0, i16 zeroext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_u16_i1: ; CHECK-LABEL: select_cc_u16_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_i32_i1(i32 signext %0, i32 signext %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_i32_i1(i32 signext %0, i32 signext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i32_i1: ; CHECK-LABEL: select_cc_i32_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_u32_i1(i32 zeroext %0, i32 zeroext %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_u32_i1(i32 zeroext %0, i32 zeroext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_u32_i1: ; CHECK-LABEL: select_cc_u32_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_i64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_i64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i64_i1: ; CHECK-LABEL: select_cc_i64_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_u64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_u64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_u64_i1: ; CHECK-LABEL: select_cc_u64_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_i128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_i128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i128_i1: ; CHECK-LABEL: select_cc_i128_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_u128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_u128_i1(i128 %0, i128 %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_u128_i1: ; CHECK-LABEL: select_cc_u128_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_float_i1(float %0, float %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_float_i1(float %0, float %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_float_i1: ; CHECK-LABEL: select_cc_float_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_double_i1(double %0, double %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_double_i1(double %0, double %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_double_i1: ; CHECK-LABEL: select_cc_double_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_cc_quad_i1(fp128 %0, fp128 %1, i1 zeroext %2, i1 zeroext %3) { define zeroext i1 @select_cc_quad_i1(fp128 %0, fp128 %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_quad_i1: ; CHECK-LABEL: select_cc_quad_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i1 %2, i1 %3 %6 = select i1 %5, i1 %2, i1 %3
ret i1 %6 ret i1 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_i1_i8(i1 zeroext %0, i1 zeroext %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_i1_i8(i1 zeroext %0, i1 zeroext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i1_i8: ; CHECK-LABEL: select_cc_i1_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i8 %3, i8 %2 %6 = select i1 %5, i8 %3, i8 %2
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_i8_i8(i8 signext %0, i8 signext %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_i8_i8(i8 signext %0, i8 signext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i8_i8: ; CHECK-LABEL: select_cc_i8_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_u8_i8(i8 zeroext %0, i8 zeroext %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_u8_i8(i8 zeroext %0, i8 zeroext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_u8_i8: ; CHECK-LABEL: select_cc_u8_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_i16_i8(i16 signext %0, i16 signext %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_i16_i8(i16 signext %0, i16 signext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i16_i8: ; CHECK-LABEL: select_cc_i16_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_u16_i8(i16 zeroext %0, i16 zeroext %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_u16_i8(i16 zeroext %0, i16 zeroext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_u16_i8: ; CHECK-LABEL: select_cc_u16_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_i32_i8(i32 signext %0, i32 signext %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_i32_i8(i32 signext %0, i32 signext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i32_i8: ; CHECK-LABEL: select_cc_i32_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_u32_i8(i32 zeroext %0, i32 zeroext %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_u32_i8(i32 zeroext %0, i32 zeroext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_u32_i8: ; CHECK-LABEL: select_cc_u32_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_i64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_i64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i64_i8: ; CHECK-LABEL: select_cc_i64_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_u64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_u64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_u64_i8: ; CHECK-LABEL: select_cc_u64_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_i128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_i128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i128_i8: ; CHECK-LABEL: select_cc_i128_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_u128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_u128_i8(i128 %0, i128 %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_u128_i8: ; CHECK-LABEL: select_cc_u128_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_float_i8(float %0, float %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_float_i8(float %0, float %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_float_i8: ; CHECK-LABEL: select_cc_float_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_double_i8(double %0, double %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_double_i8(double %0, double %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_double_i8: ; CHECK-LABEL: select_cc_double_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @select_cc_quad_i8(fp128 %0, fp128 %1, i8 signext %2, i8 signext %3) { define signext i8 @select_cc_quad_i8(fp128 %0, fp128 %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_quad_i8: ; CHECK-LABEL: select_cc_quad_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_i1_u8(i1 zeroext %0, i1 zeroext %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_i1_u8(i1 zeroext %0, i1 zeroext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i1_u8: ; CHECK-LABEL: select_cc_i1_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i8 %3, i8 %2 %6 = select i1 %5, i8 %3, i8 %2
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_i8_u8(i8 signext %0, i8 signext %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_i8_u8(i8 signext %0, i8 signext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i8_u8: ; CHECK-LABEL: select_cc_i8_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_u8_u8(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_u8_u8(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_u8_u8: ; CHECK-LABEL: select_cc_u8_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_i16_u8(i16 signext %0, i16 signext %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_i16_u8(i16 signext %0, i16 signext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i16_u8: ; CHECK-LABEL: select_cc_i16_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_u16_u8(i16 zeroext %0, i16 zeroext %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_u16_u8(i16 zeroext %0, i16 zeroext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_u16_u8: ; CHECK-LABEL: select_cc_u16_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_i32_u8(i32 signext %0, i32 signext %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_i32_u8(i32 signext %0, i32 signext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i32_u8: ; CHECK-LABEL: select_cc_i32_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_u32_u8(i32 zeroext %0, i32 zeroext %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_u32_u8(i32 zeroext %0, i32 zeroext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_u32_u8: ; CHECK-LABEL: select_cc_u32_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_i64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_i64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i64_u8: ; CHECK-LABEL: select_cc_i64_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_u64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_u64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_u64_u8: ; CHECK-LABEL: select_cc_u64_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_i128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_i128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i128_u8: ; CHECK-LABEL: select_cc_i128_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_u128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_u128_u8(i128 %0, i128 %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_u128_u8: ; CHECK-LABEL: select_cc_u128_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_float_u8(float %0, float %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_float_u8(float %0, float %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_float_u8: ; CHECK-LABEL: select_cc_float_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_double_u8(double %0, double %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_double_u8(double %0, double %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_double_u8: ; CHECK-LABEL: select_cc_double_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_cc_quad_u8(fp128 %0, fp128 %1, i8 zeroext %2, i8 zeroext %3) { define zeroext i8 @select_cc_quad_u8(fp128 %0, fp128 %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_quad_u8: ; CHECK-LABEL: select_cc_quad_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i8 %2, i8 %3 %6 = select i1 %5, i8 %2, i8 %3
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_i1_i16(i1 zeroext %0, i1 zeroext %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_i1_i16(i1 zeroext %0, i1 zeroext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i1_i16: ; CHECK-LABEL: select_cc_i1_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i16 %3, i16 %2 %6 = select i1 %5, i16 %3, i16 %2
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_i8_i16(i8 signext %0, i8 signext %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_i8_i16(i8 signext %0, i8 signext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i8_i16: ; CHECK-LABEL: select_cc_i8_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_u8_i16(i8 zeroext %0, i8 zeroext %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_u8_i16(i8 zeroext %0, i8 zeroext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_u8_i16: ; CHECK-LABEL: select_cc_u8_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_i16_i16(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_i16_i16(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i16_i16: ; CHECK-LABEL: select_cc_i16_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_u16_i16(i16 zeroext %0, i16 zeroext %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_u16_i16(i16 zeroext %0, i16 zeroext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_u16_i16: ; CHECK-LABEL: select_cc_u16_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_i32_i16(i32 signext %0, i32 signext %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_i32_i16(i32 signext %0, i32 signext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i32_i16: ; CHECK-LABEL: select_cc_i32_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_u32_i16(i32 zeroext %0, i32 zeroext %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_u32_i16(i32 zeroext %0, i32 zeroext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_u32_i16: ; CHECK-LABEL: select_cc_u32_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_i64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_i64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i64_i16: ; CHECK-LABEL: select_cc_i64_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_u64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_u64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_u64_i16: ; CHECK-LABEL: select_cc_u64_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_i128_i16(i128 %0, i128 %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_i128_i16(i128 %0, i128 %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i128_i16: ; CHECK-LABEL: select_cc_i128_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_u128_i16(i128 %0, i128 %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_u128_i16(i128 %0, i128 %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_u128_i16: ; CHECK-LABEL: select_cc_u128_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_float_i16(float %0, float %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_float_i16(float %0, float %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_float_i16: ; CHECK-LABEL: select_cc_float_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_double_i16(double %0, double %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_double_i16(double %0, double %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_double_i16: ; CHECK-LABEL: select_cc_double_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @select_cc_quad_i16(fp128 %0, fp128 %1, i16 signext %2, i16 signext %3) { define signext i16 @select_cc_quad_i16(fp128 %0, fp128 %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_quad_i16: ; CHECK-LABEL: select_cc_quad_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_i1_u16(i1 zeroext %0, i1 zeroext %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_i1_u16(i1 zeroext %0, i1 zeroext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i1_u16: ; CHECK-LABEL: select_cc_i1_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i16 %3, i16 %2 %6 = select i1 %5, i16 %3, i16 %2
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_i8_u16(i8 signext %0, i8 signext %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_i8_u16(i8 signext %0, i8 signext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i8_u16: ; CHECK-LABEL: select_cc_i8_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_u8_u16(i8 zeroext %0, i8 zeroext %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_u8_u16(i8 zeroext %0, i8 zeroext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_u8_u16: ; CHECK-LABEL: select_cc_u8_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_i16_u16(i16 signext %0, i16 signext %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_i16_u16(i16 signext %0, i16 signext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i16_u16: ; CHECK-LABEL: select_cc_i16_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_u16_u16(i16 zeroext %0, i16 zeroext %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_u16_u16(i16 zeroext %0, i16 zeroext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_u16_u16: ; CHECK-LABEL: select_cc_u16_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_i32_u16(i32 signext %0, i32 signext %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_i32_u16(i32 signext %0, i32 signext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i32_u16: ; CHECK-LABEL: select_cc_i32_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_u32_u16(i32 zeroext %0, i32 zeroext %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_u32_u16(i32 zeroext %0, i32 zeroext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_u32_u16: ; CHECK-LABEL: select_cc_u32_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_i64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_i64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i64_u16: ; CHECK-LABEL: select_cc_i64_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_u64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_u64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_u64_u16: ; CHECK-LABEL: select_cc_u64_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_i128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_i128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i128_u16: ; CHECK-LABEL: select_cc_i128_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_u128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_u128_u16(i128 %0, i128 %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_u128_u16: ; CHECK-LABEL: select_cc_u128_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_float_u16(float %0, float %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_float_u16(float %0, float %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_float_u16: ; CHECK-LABEL: select_cc_float_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_double_u16(double %0, double %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_double_u16(double %0, double %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_double_u16: ; CHECK-LABEL: select_cc_double_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_cc_quad_u16(fp128 %0, fp128 %1, i16 zeroext %2, i16 zeroext %3) { define zeroext i16 @select_cc_quad_u16(fp128 %0, fp128 %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_quad_u16: ; CHECK-LABEL: select_cc_quad_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i16 %2, i16 %3 %6 = select i1 %5, i16 %2, i16 %3
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_i1_i32(i1 zeroext %0, i1 zeroext %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_i1_i32(i1 zeroext %0, i1 zeroext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i1_i32: ; CHECK-LABEL: select_cc_i1_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i32 %3, i32 %2 %6 = select i1 %5, i32 %3, i32 %2
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_i8_i32(i8 signext %0, i8 signext %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_i8_i32(i8 signext %0, i8 signext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i8_i32: ; CHECK-LABEL: select_cc_i8_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_u8_i32(i8 zeroext %0, i8 zeroext %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_u8_i32(i8 zeroext %0, i8 zeroext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_u8_i32: ; CHECK-LABEL: select_cc_u8_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_i16_i32(i16 signext %0, i16 signext %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_i16_i32(i16 signext %0, i16 signext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i16_i32: ; CHECK-LABEL: select_cc_i16_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_u16_i32(i16 zeroext %0, i16 zeroext %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_u16_i32(i16 zeroext %0, i16 zeroext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_u16_i32: ; CHECK-LABEL: select_cc_u16_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_i32_i32(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_i32_i32(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i32_i32: ; CHECK-LABEL: select_cc_i32_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_u32_i32(i32 zeroext %0, i32 zeroext %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_u32_i32(i32 zeroext %0, i32 zeroext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_u32_i32: ; CHECK-LABEL: select_cc_u32_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_i64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_i64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i64_i32: ; CHECK-LABEL: select_cc_i64_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_u64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_u64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_u64_i32: ; CHECK-LABEL: select_cc_u64_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_i128_i32(i128 %0, i128 %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_i128_i32(i128 %0, i128 %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i128_i32: ; CHECK-LABEL: select_cc_i128_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_u128_i32(i128 %0, i128 %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_u128_i32(i128 %0, i128 %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_u128_i32: ; CHECK-LABEL: select_cc_u128_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_float_i32(float %0, float %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_float_i32(float %0, float %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_float_i32: ; CHECK-LABEL: select_cc_float_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_double_i32(double %0, double %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_double_i32(double %0, double %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_double_i32: ; CHECK-LABEL: select_cc_double_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @select_cc_quad_i32(fp128 %0, fp128 %1, i32 signext %2, i32 signext %3) { define signext i32 @select_cc_quad_i32(fp128 %0, fp128 %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_quad_i32: ; CHECK-LABEL: select_cc_quad_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_i1_u32(i1 zeroext %0, i1 zeroext %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_i1_u32(i1 zeroext %0, i1 zeroext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i1_u32: ; CHECK-LABEL: select_cc_i1_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i32 %3, i32 %2 %6 = select i1 %5, i32 %3, i32 %2
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_i8_u32(i8 signext %0, i8 signext %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_i8_u32(i8 signext %0, i8 signext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i8_u32: ; CHECK-LABEL: select_cc_i8_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_u8_u32(i8 zeroext %0, i8 zeroext %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_u8_u32(i8 zeroext %0, i8 zeroext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_u8_u32: ; CHECK-LABEL: select_cc_u8_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_i16_u32(i16 signext %0, i16 signext %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_i16_u32(i16 signext %0, i16 signext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i16_u32: ; CHECK-LABEL: select_cc_i16_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_u16_u32(i16 zeroext %0, i16 zeroext %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_u16_u32(i16 zeroext %0, i16 zeroext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_u16_u32: ; CHECK-LABEL: select_cc_u16_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_i32_u32(i32 signext %0, i32 signext %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_i32_u32(i32 signext %0, i32 signext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i32_u32: ; CHECK-LABEL: select_cc_i32_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_u32_u32(i32 zeroext %0, i32 zeroext %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_u32_u32(i32 zeroext %0, i32 zeroext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_u32_u32: ; CHECK-LABEL: select_cc_u32_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_i64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_i64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i64_u32: ; CHECK-LABEL: select_cc_i64_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_u64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_u64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_u64_u32: ; CHECK-LABEL: select_cc_u64_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_i128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_i128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i128_u32: ; CHECK-LABEL: select_cc_i128_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_u128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_u128_u32(i128 %0, i128 %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_u128_u32: ; CHECK-LABEL: select_cc_u128_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_float_u32(float %0, float %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_float_u32(float %0, float %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_float_u32: ; CHECK-LABEL: select_cc_float_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_double_u32(double %0, double %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_double_u32(double %0, double %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_double_u32: ; CHECK-LABEL: select_cc_double_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_cc_quad_u32(fp128 %0, fp128 %1, i32 zeroext %2, i32 zeroext %3) { define zeroext i32 @select_cc_quad_u32(fp128 %0, fp128 %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_quad_u32: ; CHECK-LABEL: select_cc_quad_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i1_i64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i1_i64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i1_i64: ; CHECK-LABEL: select_cc_i1_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i64 %3, i64 %2 %6 = select i1 %5, i64 %3, i64 %2
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i8_i64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) { define i64 @select_cc_i8_i64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i8_i64: ; CHECK-LABEL: select_cc_i8_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u8_i64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_u8_i64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u8_i64: ; CHECK-LABEL: select_cc_u8_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i16_i64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) { define i64 @select_cc_i16_i64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i16_i64: ; CHECK-LABEL: select_cc_i16_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u16_i64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_u16_i64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u16_i64: ; CHECK-LABEL: select_cc_u16_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i32_i64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) { define i64 @select_cc_i32_i64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i32_i64: ; CHECK-LABEL: select_cc_i32_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u32_i64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_u32_i64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u32_i64: ; CHECK-LABEL: select_cc_u32_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i64_i64(i64 %0, i64 %1, i64 %2, i64 %3) { define i64 @select_cc_i64_i64(i64 %0, i64 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i64_i64: ; CHECK-LABEL: select_cc_i64_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u64_i64(i64 %0, i64 %1, i64 %2, i64 %3) { define i64 @select_cc_u64_i64(i64 %0, i64 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u64_i64: ; CHECK-LABEL: select_cc_u64_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i128_i64(i128 %0, i128 %1, i64 %2, i64 %3) { define i64 @select_cc_i128_i64(i128 %0, i128 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i128_i64: ; CHECK-LABEL: select_cc_i128_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u128_i64(i128 %0, i128 %1, i64 %2, i64 %3) { define i64 @select_cc_u128_i64(i128 %0, i128 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u128_i64: ; CHECK-LABEL: select_cc_u128_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_float_i64(float %0, float %1, i64 %2, i64 %3) { define i64 @select_cc_float_i64(float %0, float %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_float_i64: ; CHECK-LABEL: select_cc_float_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_double_i64(double %0, double %1, i64 %2, i64 %3) { define i64 @select_cc_double_i64(double %0, double %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_double_i64: ; CHECK-LABEL: select_cc_double_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_quad_i64(fp128 %0, fp128 %1, i64 %2, i64 %3) { define i64 @select_cc_quad_i64(fp128 %0, fp128 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_quad_i64: ; CHECK-LABEL: select_cc_quad_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i1_u64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_i1_u64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i1_u64: ; CHECK-LABEL: select_cc_i1_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i64 %3, i64 %2 %6 = select i1 %5, i64 %3, i64 %2
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i8_u64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) { define i64 @select_cc_i8_u64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i8_u64: ; CHECK-LABEL: select_cc_i8_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u8_u64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_u8_u64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u8_u64: ; CHECK-LABEL: select_cc_u8_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i16_u64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) { define i64 @select_cc_i16_u64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i16_u64: ; CHECK-LABEL: select_cc_i16_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u16_u64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_u16_u64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u16_u64: ; CHECK-LABEL: select_cc_u16_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i32_u64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) { define i64 @select_cc_i32_u64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i32_u64: ; CHECK-LABEL: select_cc_i32_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u32_u64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) { define i64 @select_cc_u32_u64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u32_u64: ; CHECK-LABEL: select_cc_u32_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i64_u64(i64 %0, i64 %1, i64 %2, i64 %3) { define i64 @select_cc_i64_u64(i64 %0, i64 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i64_u64: ; CHECK-LABEL: select_cc_i64_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u64_u64(i64 %0, i64 %1, i64 %2, i64 %3) { define i64 @select_cc_u64_u64(i64 %0, i64 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u64_u64: ; CHECK-LABEL: select_cc_u64_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_i128_u64(i128 %0, i128 %1, i64 %2, i64 %3) { define i64 @select_cc_i128_u64(i128 %0, i128 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i128_u64: ; CHECK-LABEL: select_cc_i128_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_u128_u64(i128 %0, i128 %1, i64 %2, i64 %3) { define i64 @select_cc_u128_u64(i128 %0, i128 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u128_u64: ; CHECK-LABEL: select_cc_u128_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_float_u64(float %0, float %1, i64 %2, i64 %3) { define i64 @select_cc_float_u64(float %0, float %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_float_u64: ; CHECK-LABEL: select_cc_float_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_double_u64(double %0, double %1, i64 %2, i64 %3) { define i64 @select_cc_double_u64(double %0, double %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_double_u64: ; CHECK-LABEL: select_cc_double_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @select_cc_quad_u64(fp128 %0, fp128 %1, i64 %2, i64 %3) { define i64 @select_cc_quad_u64(fp128 %0, fp128 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_quad_u64: ; CHECK-LABEL: select_cc_quad_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i1_i128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_i1_i128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i1_i128: ; CHECK-LABEL: select_cc_i1_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3 ; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i128 %3, i128 %2 %6 = select i1 %5, i128 %3, i128 %2
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i8_i128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) { define i128 @select_cc_i8_i128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i8_i128: ; CHECK-LABEL: select_cc_i8_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u8_i128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_u8_i128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u8_i128: ; CHECK-LABEL: select_cc_u8_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i16_i128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) { define i128 @select_cc_i16_i128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i16_i128: ; CHECK-LABEL: select_cc_i16_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u16_i128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_u16_i128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u16_i128: ; CHECK-LABEL: select_cc_u16_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i32_i128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) { define i128 @select_cc_i32_i128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i32_i128: ; CHECK-LABEL: select_cc_i32_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u32_i128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_u32_i128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u32_i128: ; CHECK-LABEL: select_cc_u32_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i64_i128(i64 %0, i64 %1, i128 %2, i128 %3) { define i128 @select_cc_i64_i128(i64 %0, i64 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i64_i128: ; CHECK-LABEL: select_cc_i64_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u64_i128(i64 %0, i64 %1, i128 %2, i128 %3) { define i128 @select_cc_u64_i128(i64 %0, i64 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u64_i128: ; CHECK-LABEL: select_cc_u64_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i128_i128(i128 %0, i128 %1, i128 %2, i128 %3) { define i128 @select_cc_i128_i128(i128 %0, i128 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i128_i128: ; CHECK-LABEL: select_cc_i128_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: or %s1, 0, %s7 ; CHECK-NEXT: or %s1, 0, %s7
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u128_i128(i128 %0, i128 %1, i128 %2, i128 %3) { define i128 @select_cc_u128_i128(i128 %0, i128 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u128_i128: ; CHECK-LABEL: select_cc_u128_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: or %s1, 0, %s7 ; CHECK-NEXT: or %s1, 0, %s7
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_float_i128(float %0, float %1, i128 %2, i128 %3) { define i128 @select_cc_float_i128(float %0, float %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_float_i128: ; CHECK-LABEL: select_cc_float_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.s.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.s.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_double_i128(double %0, double %1, i128 %2, i128 %3) { define i128 @select_cc_double_i128(double %0, double %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_double_i128: ; CHECK-LABEL: select_cc_double_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.d.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_quad_i128(fp128 %0, fp128 %1, i128 %2, i128 %3) { define i128 @select_cc_quad_i128(fp128 %0, fp128 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_quad_i128: ; CHECK-LABEL: select_cc_quad_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.d.eq %s7, %s5, %s0 ; CHECK-NEXT: cmov.d.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: or %s1, 0, %s7 ; CHECK-NEXT: or %s1, 0, %s7
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i1_u128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_i1_u128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i1_u128: ; CHECK-LABEL: select_cc_i1_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3 ; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select i1 %5, i128 %3, i128 %2 %6 = select i1 %5, i128 %3, i128 %2
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i8_u128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) { define i128 @select_cc_i8_u128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i8_u128: ; CHECK-LABEL: select_cc_i8_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u8_u128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_u8_u128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u8_u128: ; CHECK-LABEL: select_cc_u8_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i16_u128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) { define i128 @select_cc_i16_u128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i16_u128: ; CHECK-LABEL: select_cc_i16_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u16_u128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_u16_u128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u16_u128: ; CHECK-LABEL: select_cc_u16_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i32_u128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) { define i128 @select_cc_i32_u128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i32_u128: ; CHECK-LABEL: select_cc_i32_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u32_u128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) { define i128 @select_cc_u32_u128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u32_u128: ; CHECK-LABEL: select_cc_u32_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i64_u128(i64 %0, i64 %1, i128 %2, i128 %3) { define i128 @select_cc_i64_u128(i64 %0, i64 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i64_u128: ; CHECK-LABEL: select_cc_i64_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u64_u128(i64 %0, i64 %1, i128 %2, i128 %3) { define i128 @select_cc_u64_u128(i64 %0, i64 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u64_u128: ; CHECK-LABEL: select_cc_u64_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_i128_u128(i128 %0, i128 %1, i128 %2, i128 %3) { define i128 @select_cc_i128_u128(i128 %0, i128 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i128_u128: ; CHECK-LABEL: select_cc_i128_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: or %s1, 0, %s7 ; CHECK-NEXT: or %s1, 0, %s7
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_u128_u128(i128 %0, i128 %1, i128 %2, i128 %3) { define i128 @select_cc_u128_u128(i128 %0, i128 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u128_u128: ; CHECK-LABEL: select_cc_u128_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: or %s1, 0, %s7 ; CHECK-NEXT: or %s1, 0, %s7
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_float_u128(float %0, float %1, i128 %2, i128 %3) { define i128 @select_cc_float_u128(float %0, float %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_float_u128: ; CHECK-LABEL: select_cc_float_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.s.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.s.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_double_u128(double %0, double %1, i128 %2, i128 %3) { define i128 @select_cc_double_u128(double %0, double %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_double_u128: ; CHECK-LABEL: select_cc_double_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.d.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @select_cc_quad_u128(fp128 %0, fp128 %1, i128 %2, i128 %3) { define i128 @select_cc_quad_u128(fp128 %0, fp128 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_quad_u128: ; CHECK-LABEL: select_cc_quad_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.d.eq %s7, %s5, %s0 ; CHECK-NEXT: cmov.d.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: or %s1, 0, %s7 ; CHECK-NEXT: or %s1, 0, %s7
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select i1 %5, i128 %2, i128 %3 %6 = select i1 %5, i128 %2, i128 %3
ret i128 %6 ret i128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_i1_float(i1 zeroext %0, i1 zeroext %1, float %2, float %3) { define float @select_cc_i1_float(i1 zeroext %0, i1 zeroext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i1_float: ; CHECK-LABEL: select_cc_i1_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select fast i1 %5, float %3, float %2 %6 = select fast i1 %5, float %3, float %2
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_i8_float(i8 signext %0, i8 signext %1, float %2, float %3) { define float @select_cc_i8_float(i8 signext %0, i8 signext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i8_float: ; CHECK-LABEL: select_cc_i8_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_u8_float(i8 zeroext %0, i8 zeroext %1, float %2, float %3) { define float @select_cc_u8_float(i8 zeroext %0, i8 zeroext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_u8_float: ; CHECK-LABEL: select_cc_u8_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_i16_float(i16 signext %0, i16 signext %1, float %2, float %3) { define float @select_cc_i16_float(i16 signext %0, i16 signext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i16_float: ; CHECK-LABEL: select_cc_i16_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_u16_float(i16 zeroext %0, i16 zeroext %1, float %2, float %3) { define float @select_cc_u16_float(i16 zeroext %0, i16 zeroext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_u16_float: ; CHECK-LABEL: select_cc_u16_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_i32_float(i32 signext %0, i32 signext %1, float %2, float %3) { define float @select_cc_i32_float(i32 signext %0, i32 signext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i32_float: ; CHECK-LABEL: select_cc_i32_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_u32_float(i32 zeroext %0, i32 zeroext %1, float %2, float %3) { define float @select_cc_u32_float(i32 zeroext %0, i32 zeroext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_u32_float: ; CHECK-LABEL: select_cc_u32_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_i64_float(i64 %0, i64 %1, float %2, float %3) { define float @select_cc_i64_float(i64 %0, i64 %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i64_float: ; CHECK-LABEL: select_cc_i64_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_u64_float(i64 %0, i64 %1, float %2, float %3) { define float @select_cc_u64_float(i64 %0, i64 %1, float %2, float %3) {
; CHECK-LABEL: select_cc_u64_float: ; CHECK-LABEL: select_cc_u64_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_i128_float(i128 %0, i128 %1, float %2, float %3) { define float @select_cc_i128_float(i128 %0, i128 %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i128_float: ; CHECK-LABEL: select_cc_i128_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_u128_float(i128 %0, i128 %1, float %2, float %3) { define float @select_cc_u128_float(i128 %0, i128 %1, float %2, float %3) {
; CHECK-LABEL: select_cc_u128_float: ; CHECK-LABEL: select_cc_u128_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_float_float(float %0, float %1, float %2, float %3) { define float @select_cc_float_float(float %0, float %1, float %2, float %3) {
; CHECK-LABEL: select_cc_float_float: ; CHECK-LABEL: select_cc_float_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_double_float(double %0, double %1, float %2, float %3) { define float @select_cc_double_float(double %0, double %1, float %2, float %3) {
; CHECK-LABEL: select_cc_double_float: ; CHECK-LABEL: select_cc_double_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @select_cc_quad_float(fp128 %0, fp128 %1, float %2, float %3) { define float @select_cc_quad_float(fp128 %0, fp128 %1, float %2, float %3) {
; CHECK-LABEL: select_cc_quad_float: ; CHECK-LABEL: select_cc_quad_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select fast i1 %5, float %2, float %3 %6 = select fast i1 %5, float %2, float %3
ret float %6 ret float %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_i1_double(i1 zeroext %0, i1 zeroext %1, double %2, double %3) { define double @select_cc_i1_double(i1 zeroext %0, i1 zeroext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i1_double: ; CHECK-LABEL: select_cc_i1_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select fast i1 %5, double %3, double %2 %6 = select fast i1 %5, double %3, double %2
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_i8_double(i8 signext %0, i8 signext %1, double %2, double %3) { define double @select_cc_i8_double(i8 signext %0, i8 signext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i8_double: ; CHECK-LABEL: select_cc_i8_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_u8_double(i8 zeroext %0, i8 zeroext %1, double %2, double %3) { define double @select_cc_u8_double(i8 zeroext %0, i8 zeroext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_u8_double: ; CHECK-LABEL: select_cc_u8_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_i16_double(i16 signext %0, i16 signext %1, double %2, double %3) { define double @select_cc_i16_double(i16 signext %0, i16 signext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i16_double: ; CHECK-LABEL: select_cc_i16_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_u16_double(i16 zeroext %0, i16 zeroext %1, double %2, double %3) { define double @select_cc_u16_double(i16 zeroext %0, i16 zeroext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_u16_double: ; CHECK-LABEL: select_cc_u16_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_i32_double(i32 signext %0, i32 signext %1, double %2, double %3) { define double @select_cc_i32_double(i32 signext %0, i32 signext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i32_double: ; CHECK-LABEL: select_cc_i32_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_u32_double(i32 zeroext %0, i32 zeroext %1, double %2, double %3) { define double @select_cc_u32_double(i32 zeroext %0, i32 zeroext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_u32_double: ; CHECK-LABEL: select_cc_u32_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_i64_double(i64 %0, i64 %1, double %2, double %3) { define double @select_cc_i64_double(i64 %0, i64 %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i64_double: ; CHECK-LABEL: select_cc_i64_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_u64_double(i64 %0, i64 %1, double %2, double %3) { define double @select_cc_u64_double(i64 %0, i64 %1, double %2, double %3) {
; CHECK-LABEL: select_cc_u64_double: ; CHECK-LABEL: select_cc_u64_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_i128_double(i128 %0, i128 %1, double %2, double %3) { define double @select_cc_i128_double(i128 %0, i128 %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i128_double: ; CHECK-LABEL: select_cc_i128_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_u128_double(i128 %0, i128 %1, double %2, double %3) { define double @select_cc_u128_double(i128 %0, i128 %1, double %2, double %3) {
; CHECK-LABEL: select_cc_u128_double: ; CHECK-LABEL: select_cc_u128_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_float_double(float %0, float %1, double %2, double %3) { define double @select_cc_float_double(float %0, float %1, double %2, double %3) {
; CHECK-LABEL: select_cc_float_double: ; CHECK-LABEL: select_cc_float_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_double_double(double %0, double %1, double %2, double %3) { define double @select_cc_double_double(double %0, double %1, double %2, double %3) {
; CHECK-LABEL: select_cc_double_double: ; CHECK-LABEL: select_cc_double_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define double @select_cc_quad_double(fp128 %0, fp128 %1, double %2, double %3) { define double @select_cc_quad_double(fp128 %0, fp128 %1, double %2, double %3) {
; CHECK-LABEL: select_cc_quad_double: ; CHECK-LABEL: select_cc_quad_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select fast i1 %5, double %2, double %3 %6 = select fast i1 %5, double %2, double %3
ret double %6 ret double %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_i1_quad(i1 zeroext %0, i1 zeroext %1, fp128 %2, fp128 %3) { define fp128 @select_cc_i1_quad(i1 zeroext %0, i1 zeroext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i1_quad: ; CHECK-LABEL: select_cc_i1_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3 ; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = xor i1 %0, %1 %5 = xor i1 %0, %1
%6 = select fast i1 %5, fp128 %3, fp128 %2 %6 = select fast i1 %5, fp128 %3, fp128 %2
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_i8_quad(i8 signext %0, i8 signext %1, fp128 %2, fp128 %3) { define fp128 @select_cc_i8_quad(i8 signext %0, i8 signext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i8_quad: ; CHECK-LABEL: select_cc_i8_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_u8_quad(i8 zeroext %0, i8 zeroext %1, fp128 %2, fp128 %3) { define fp128 @select_cc_u8_quad(i8 zeroext %0, i8 zeroext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_u8_quad: ; CHECK-LABEL: select_cc_u8_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i8 %0, %1 %5 = icmp eq i8 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_i16_quad(i16 signext %0, i16 signext %1, fp128 %2, fp128 %3) { define fp128 @select_cc_i16_quad(i16 signext %0, i16 signext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i16_quad: ; CHECK-LABEL: select_cc_i16_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_u16_quad(i16 zeroext %0, i16 zeroext %1, fp128 %2, fp128 %3) { define fp128 @select_cc_u16_quad(i16 zeroext %0, i16 zeroext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_u16_quad: ; CHECK-LABEL: select_cc_u16_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i16 %0, %1 %5 = icmp eq i16 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_i32_quad(i32 signext %0, i32 signext %1, fp128 %2, fp128 %3) { define fp128 @select_cc_i32_quad(i32 signext %0, i32 signext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i32_quad: ; CHECK-LABEL: select_cc_i32_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_u32_quad(i32 zeroext %0, i32 zeroext %1, fp128 %2, fp128 %3) { define fp128 @select_cc_u32_quad(i32 zeroext %0, i32 zeroext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_u32_quad: ; CHECK-LABEL: select_cc_u32_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_i64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) { define fp128 @select_cc_i64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i64_quad: ; CHECK-LABEL: select_cc_i64_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_u64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) { define fp128 @select_cc_u64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_u64_quad: ; CHECK-LABEL: select_cc_u64_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_i128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) { define fp128 @select_cc_i128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i128_quad: ; CHECK-LABEL: select_cc_i128_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: or %s1, 0, %s7 ; CHECK-NEXT: or %s1, 0, %s7
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_u128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) { define fp128 @select_cc_u128_quad(i128 %0, i128 %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_u128_quad: ; CHECK-LABEL: select_cc_u128_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0 ; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: or %s1, 0, %s7 ; CHECK-NEXT: or %s1, 0, %s7
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i128 %0, %1 %5 = icmp eq i128 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_float_quad(float %0, float %1, fp128 %2, fp128 %3) { define fp128 @select_cc_float_quad(float %0, float %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_float_quad: ; CHECK-LABEL: select_cc_float_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.s.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.s.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq float %0, %1 %5 = fcmp fast oeq float %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_double_quad(double %0, double %1, fp128 %2, fp128 %3) { define fp128 @select_cc_double_quad(double %0, double %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_double_quad: ; CHECK-LABEL: select_cc_double_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s4, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.d.eq %s5, %s3, %s0 ; CHECK-NEXT: cmov.d.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4 ; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5 ; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq double %0, %1 %5 = fcmp fast oeq double %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @select_cc_quad_quad(fp128 %0, fp128 %1, fp128 %2, fp128 %3) { define fp128 @select_cc_quad_quad(fp128 %0, fp128 %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_quad_quad: ; CHECK-LABEL: select_cc_quad_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: cmov.d.eq %s6, %s4, %s0 ; CHECK-NEXT: cmov.d.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.d.eq %s7, %s5, %s0 ; CHECK-NEXT: cmov.d.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6 ; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: or %s1, 0, %s7 ; CHECK-NEXT: or %s1, 0, %s7
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp fast oeq fp128 %0, %1 %5 = fcmp fast oeq fp128 %0, %1
%6 = select fast i1 %5, fp128 %2, fp128 %3 %6 = select fast i1 %5, fp128 %2, fp128 %3
ret fp128 %6 ret fp128 %6
} }

llvm/test/CodeGen/VE/Scalar/selectccf32.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @selectccaf(float, float, float, float) { define float @selectccaf(float, float, float, float) {
; CHECK-LABEL: selectccaf: ; CHECK-LABEL: selectccaf:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp false float %0, %1 %5 = fcmp false float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccat(float, float, float, float) { define float @selectccat(float, float, float, float) {
; CHECK-LABEL: selectccat: ; CHECK-LABEL: selectccat:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp true float %0, %1 %5 = fcmp true float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccoeq(float, float, float, float) { define float @selectccoeq(float, float, float, float) {
; CHECK-LABEL: selectccoeq: ; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oeq float %0, %1 %5 = fcmp oeq float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccone(float, float, float, float) { define float @selectccone(float, float, float, float) {
; CHECK-LABEL: selectccone: ; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp one float %0, %1 %5 = fcmp one float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccogt(float, float, float, float) { define float @selectccogt(float, float, float, float) {
; CHECK-LABEL: selectccogt: ; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1 %5 = fcmp ogt float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccoge(float, float, float, float) { define float @selectccoge(float, float, float, float) {
; CHECK-LABEL: selectccoge: ; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oge float %0, %1 %5 = fcmp oge float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccolt(float, float, float, float) { define float @selectccolt(float, float, float, float) {
; CHECK-LABEL: selectccolt: ; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp olt float %0, %1 %5 = fcmp olt float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccole(float, float, float, float) { define float @selectccole(float, float, float, float) {
; CHECK-LABEL: selectccole: ; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ole float %0, %1 %5 = fcmp ole float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccord(float, float, float, float) { define float @selectccord(float, float, float, float) {
; CHECK-LABEL: selectccord: ; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.num %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ord float %0, %1 %5 = fcmp ord float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccuno(float, float, float, float) { define float @selectccuno(float, float, float, float) {
; CHECK-LABEL: selectccuno: ; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uno float %0, %1 %5 = fcmp uno float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccueq(float, float, float, float) { define float @selectccueq(float, float, float, float) {
; CHECK-LABEL: selectccueq: ; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ueq float %0, %1 %5 = fcmp ueq float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccune(float, float, float, float) { define float @selectccune(float, float, float, float) {
; CHECK-LABEL: selectccune: ; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp une float %0, %1 %5 = fcmp une float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccugt(float, float, float, float) { define float @selectccugt(float, float, float, float) {
; CHECK-LABEL: selectccugt: ; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ugt float %0, %1 %5 = fcmp ugt float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccuge(float, float, float, float) { define float @selectccuge(float, float, float, float) {
; CHECK-LABEL: selectccuge: ; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uge float %0, %1 %5 = fcmp uge float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccult(float, float, float, float) { define float @selectccult(float, float, float, float) {
; CHECK-LABEL: selectccult: ; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ult float %0, %1 %5 = fcmp ult float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccule(float, float, float, float) { define float @selectccule(float, float, float, float) {
; CHECK-LABEL: selectccule: ; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ule float %0, %1 %5 = fcmp ule float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }

llvm/test/CodeGen/VE/Scalar/selectccf32c.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @selectccsgti8(i8, i8, float, float) { define float @selectccsgti8(i8, i8, float, float) {
; CHECK-LABEL: selectccsgti8: ; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 56 ; CHECK-NEXT: sll %s1, %s1, 56
; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i8 %0, %1 %5 = icmp sgt i8 %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccsgti16(i16, i16, float, float) { define float @selectccsgti16(i16, i16, float, float) {
; CHECK-LABEL: selectccsgti16: ; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 48 ; CHECK-NEXT: sll %s1, %s1, 48
; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i16 %0, %1 %5 = icmp sgt i16 %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccsgti32(i32, i32, float, float) { define float @selectccsgti32(i32, i32, float, float) {
; CHECK-LABEL: selectccsgti32: ; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1 %5 = icmp sgt i32 %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccsgti64(i64, i64, float, float) { define float @selectccsgti64(i64, i64, float, float) {
; CHECK-LABEL: selectccsgti64: ; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1 %5 = icmp sgt i64 %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccsgti128(i128, i128, float, float) { define float @selectccsgti128(i128, i128, float, float) {
; CHECK-LABEL: selectccsgti128: ; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1 ; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1 ; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2 ; CHECK-NEXT: cmpu.l %s0, %s0, %s2
; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1 ; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 ; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1 %5 = icmp sgt i128 %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccogtf32(float, float, float, float) { define float @selectccogtf32(float, float, float, float) {
; CHECK-LABEL: selectccogtf32: ; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1 %5 = fcmp ogt float %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccogtf64(double, double, float, float) { define float @selectccogtf64(double, double, float, float) {
; CHECK-LABEL: selectccogtf64: ; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1 %5 = fcmp ogt double %0, %1
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }

llvm/test/CodeGen/VE/Scalar/selectccf32i.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @selectccaf(float, float, float, float) { define float @selectccaf(float, float, float, float) {
; CHECK-LABEL: selectccaf: ; CHECK-LABEL: selectccaf:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp false float %0, 0.0 %5 = fcmp false float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccat(float, float, float, float) { define float @selectccat(float, float, float, float) {
; CHECK-LABEL: selectccat: ; CHECK-LABEL: selectccat:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp true float %0, 0.0 %5 = fcmp true float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccoeq(float, float, float, float) { define float @selectccoeq(float, float, float, float) {
; CHECK-LABEL: selectccoeq: ; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oeq float %0, 0.0 %5 = fcmp oeq float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccone(float, float, float, float) { define float @selectccone(float, float, float, float) {
; CHECK-LABEL: selectccone: ; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp one float %0, 0.0 %5 = fcmp one float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccogt(float, float, float, float) { define float @selectccogt(float, float, float, float) {
; CHECK-LABEL: selectccogt: ; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, 0.0 %5 = fcmp ogt float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccoge(float, float, float, float) { define float @selectccoge(float, float, float, float) {
; CHECK-LABEL: selectccoge: ; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oge float %0, 0.0 %5 = fcmp oge float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccolt(float, float, float, float) { define float @selectccolt(float, float, float, float) {
; CHECK-LABEL: selectccolt: ; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp olt float %0, 0.0 %5 = fcmp olt float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccole(float, float, float, float) { define float @selectccole(float, float, float, float) {
; CHECK-LABEL: selectccole: ; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ole float %0, 0.0 %5 = fcmp ole float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccord(float, float, float, float) { define float @selectccord(float, float, float, float) {
; CHECK-LABEL: selectccord: ; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: cmov.s.num %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ord float %0, 0.0 %5 = fcmp ord float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccuno(float, float, float, float) { define float @selectccuno(float, float, float, float) {
; CHECK-LABEL: selectccuno: ; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uno float %0, 0.0 %5 = fcmp uno float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccueq(float, float, float, float) { define float @selectccueq(float, float, float, float) {
; CHECK-LABEL: selectccueq: ; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ueq float %0, 0.0 %5 = fcmp ueq float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccune(float, float, float, float) { define float @selectccune(float, float, float, float) {
; CHECK-LABEL: selectccune: ; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp une float %0, 0.0 %5 = fcmp une float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccugt(float, float, float, float) { define float @selectccugt(float, float, float, float) {
; CHECK-LABEL: selectccugt: ; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ugt float %0, 0.0 %5 = fcmp ugt float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccuge(float, float, float, float) { define float @selectccuge(float, float, float, float) {
; CHECK-LABEL: selectccuge: ; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uge float %0, 0.0 %5 = fcmp uge float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccult(float, float, float, float) { define float @selectccult(float, float, float, float) {
; CHECK-LABEL: selectccult: ; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ult float %0, 0.0 %5 = fcmp ult float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }
define float @selectccule(float, float, float, float) { define float @selectccule(float, float, float, float) {
; CHECK-LABEL: selectccule: ; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ule float %0, 0.0 %5 = fcmp ule float %0, 0.0
%6 = select i1 %5, float %2, float %3 %6 = select i1 %5, float %2, float %3
ret float %6 ret float %6
} }

llvm/test/CodeGen/VE/Scalar/selectccf64.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define double @selectccaf(double, double, double, double) { define double @selectccaf(double, double, double, double) {
; CHECK-LABEL: selectccaf: ; CHECK-LABEL: selectccaf:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp false double %0, %1 %5 = fcmp false double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccat(double, double, double, double) { define double @selectccat(double, double, double, double) {
; CHECK-LABEL: selectccat: ; CHECK-LABEL: selectccat:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp true double %0, %1 %5 = fcmp true double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccoeq(double, double, double, double) { define double @selectccoeq(double, double, double, double) {
; CHECK-LABEL: selectccoeq: ; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oeq double %0, %1 %5 = fcmp oeq double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccone(double, double, double, double) { define double @selectccone(double, double, double, double) {
; CHECK-LABEL: selectccone: ; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp one double %0, %1 %5 = fcmp one double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccogt(double, double, double, double) { define double @selectccogt(double, double, double, double) {
; CHECK-LABEL: selectccogt: ; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1 %5 = fcmp ogt double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccoge(double, double, double, double) { define double @selectccoge(double, double, double, double) {
; CHECK-LABEL: selectccoge: ; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oge double %0, %1 %5 = fcmp oge double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccolt(double, double, double, double) { define double @selectccolt(double, double, double, double) {
; CHECK-LABEL: selectccolt: ; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp olt double %0, %1 %5 = fcmp olt double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccole(double, double, double, double) { define double @selectccole(double, double, double, double) {
; CHECK-LABEL: selectccole: ; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ole double %0, %1 %5 = fcmp ole double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccord(double, double, double, double) { define double @selectccord(double, double, double, double) {
; CHECK-LABEL: selectccord: ; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.num %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ord double %0, %1 %5 = fcmp ord double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccuno(double, double, double, double) { define double @selectccuno(double, double, double, double) {
; CHECK-LABEL: selectccuno: ; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uno double %0, %1 %5 = fcmp uno double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccueq(double, double, double, double) { define double @selectccueq(double, double, double, double) {
; CHECK-LABEL: selectccueq: ; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ueq double %0, %1 %5 = fcmp ueq double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccune(double, double, double, double) { define double @selectccune(double, double, double, double) {
; CHECK-LABEL: selectccune: ; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp une double %0, %1 %5 = fcmp une double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccugt(double, double, double, double) { define double @selectccugt(double, double, double, double) {
; CHECK-LABEL: selectccugt: ; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ugt double %0, %1 %5 = fcmp ugt double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccuge(double, double, double, double) { define double @selectccuge(double, double, double, double) {
; CHECK-LABEL: selectccuge: ; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uge double %0, %1 %5 = fcmp uge double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccult(double, double, double, double) { define double @selectccult(double, double, double, double) {
; CHECK-LABEL: selectccult: ; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ult double %0, %1 %5 = fcmp ult double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccule(double, double, double, double) { define double @selectccule(double, double, double, double) {
; CHECK-LABEL: selectccule: ; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ule double %0, %1 %5 = fcmp ule double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }

llvm/test/CodeGen/VE/Scalar/selectccf64c.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define double @selectccsgti8(i8, i8, double, double) { define double @selectccsgti8(i8, i8, double, double) {
; CHECK-LABEL: selectccsgti8: ; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 56 ; CHECK-NEXT: sll %s1, %s1, 56
; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i8 %0, %1 %5 = icmp sgt i8 %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccsgti16(i16, i16, double, double) { define double @selectccsgti16(i16, i16, double, double) {
; CHECK-LABEL: selectccsgti16: ; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 48 ; CHECK-NEXT: sll %s1, %s1, 48
; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i16 %0, %1 %5 = icmp sgt i16 %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccsgti32(i32, i32, double, double) { define double @selectccsgti32(i32, i32, double, double) {
; CHECK-LABEL: selectccsgti32: ; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1 %5 = icmp sgt i32 %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccsgti64(i64, i64, double, double) { define double @selectccsgti64(i64, i64, double, double) {
; CHECK-LABEL: selectccsgti64: ; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1 %5 = icmp sgt i64 %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccsgti128(i128, i128, double, double) { define double @selectccsgti128(i128, i128, double, double) {
; CHECK-LABEL: selectccsgti128: ; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1 ; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1 ; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2 ; CHECK-NEXT: cmpu.l %s0, %s0, %s2
; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1 ; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 ; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1 %5 = icmp sgt i128 %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccogtf32(float, float, double, double) { define double @selectccogtf32(float, float, double, double) {
; CHECK-LABEL: selectccogtf32: ; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1 %5 = fcmp ogt float %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccogtf64(double, double, double, double) { define double @selectccogtf64(double, double, double, double) {
; CHECK-LABEL: selectccogtf64: ; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1 %5 = fcmp ogt double %0, %1
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }

llvm/test/CodeGen/VE/Scalar/selectccf64i.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define double @selectccaf(double, double, double, double) { define double @selectccaf(double, double, double, double) {
; CHECK-LABEL: selectccaf: ; CHECK-LABEL: selectccaf:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp false double %0, 0.0 %5 = fcmp false double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccat(double, double, double, double) { define double @selectccat(double, double, double, double) {
; CHECK-LABEL: selectccat: ; CHECK-LABEL: selectccat:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp true double %0, 0.0 %5 = fcmp true double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccoeq(double, double, double, double) { define double @selectccoeq(double, double, double, double) {
; CHECK-LABEL: selectccoeq: ; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oeq double %0, 0.0 %5 = fcmp oeq double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccone(double, double, double, double) { define double @selectccone(double, double, double, double) {
; CHECK-LABEL: selectccone: ; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp one double %0, 0.0 %5 = fcmp one double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccogt(double, double, double, double) { define double @selectccogt(double, double, double, double) {
; CHECK-LABEL: selectccogt: ; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, 0.0 %5 = fcmp ogt double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccoge(double, double, double, double) { define double @selectccoge(double, double, double, double) {
; CHECK-LABEL: selectccoge: ; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oge double %0, 0.0 %5 = fcmp oge double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccolt(double, double, double, double) { define double @selectccolt(double, double, double, double) {
; CHECK-LABEL: selectccolt: ; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp olt double %0, 0.0 %5 = fcmp olt double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccole(double, double, double, double) { define double @selectccole(double, double, double, double) {
; CHECK-LABEL: selectccole: ; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ole double %0, 0.0 %5 = fcmp ole double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccord(double, double, double, double) { define double @selectccord(double, double, double, double) {
; CHECK-LABEL: selectccord: ; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s0
; CHECK-NEXT: cmov.d.num %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ord double %0, 0.0 %5 = fcmp ord double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccuno(double, double, double, double) { define double @selectccuno(double, double, double, double) {
; CHECK-LABEL: selectccuno: ; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s0
; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uno double %0, 0.0 %5 = fcmp uno double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccueq(double, double, double, double) { define double @selectccueq(double, double, double, double) {
; CHECK-LABEL: selectccueq: ; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ueq double %0, 0.0 %5 = fcmp ueq double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccune(double, double, double, double) { define double @selectccune(double, double, double, double) {
; CHECK-LABEL: selectccune: ; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp une double %0, 0.0 %5 = fcmp une double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccugt(double, double, double, double) { define double @selectccugt(double, double, double, double) {
; CHECK-LABEL: selectccugt: ; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ugt double %0, 0.0 %5 = fcmp ugt double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccuge(double, double, double, double) { define double @selectccuge(double, double, double, double) {
; CHECK-LABEL: selectccuge: ; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uge double %0, 0.0 %5 = fcmp uge double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccult(double, double, double, double) { define double @selectccult(double, double, double, double) {
; CHECK-LABEL: selectccult: ; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ult double %0, 0.0 %5 = fcmp ult double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }
define double @selectccule(double, double, double, double) { define double @selectccule(double, double, double, double) {
; CHECK-LABEL: selectccule: ; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ule double %0, 0.0 %5 = fcmp ule double %0, 0.0
%6 = select i1 %5, double %2, double %3 %6 = select i1 %5, double %2, double %3
ret double %6 ret double %6
} }

llvm/test/CodeGen/VE/Scalar/selectcci32.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define i32 @selectcceq(i32, i32, i32, i32) { define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq: ; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1 %5 = icmp eq i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccne(i32, i32, i32, i32) { define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne: ; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ne i32 %0, %1 %5 = icmp ne i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsgt(i32, i32, i32, i32) { define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt: ; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1 %5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsge(i32, i32, i32, i32) { define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge: ; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i32 %0, %1 %5 = icmp sge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccslt(i32, i32, i32, i32) { define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt: ; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i32 %0, %1 %5 = icmp slt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsle(i32, i32, i32, i32) { define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle: ; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i32 %0, %1 %5 = icmp sle i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccugt(i32, i32, i32, i32) { define i32 @selectccugt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt: ; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, %1 %5 = icmp ugt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccuge(i32, i32, i32, i32) { define i32 @selectccuge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge: ; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, %1 %5 = icmp uge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccult(i32, i32, i32, i32) { define i32 @selectccult(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult: ; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, %1 %5 = icmp ult i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccule(i32, i32, i32, i32) { define i32 @selectccule(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule: ; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, %1 %5 = icmp ule i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccugt2(i32, i32, i32, i32) { define i32 @selectccugt2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt2: ; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, %1 %5 = icmp ugt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccuge2(i32, i32, i32, i32) { define i32 @selectccuge2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge2: ; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, %1 %5 = icmp uge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccult2(i32, i32, i32, i32) { define i32 @selectccult2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult2: ; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, %1 %5 = icmp ult i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccule2(i32, i32, i32, i32) { define i32 @selectccule2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule2: ; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, %1 %5 = icmp ule i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }

llvm/test/CodeGen/VE/Scalar/selectcci32c.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define i32 @selectccsgti8(i8, i8, i32, i32) { define i32 @selectccsgti8(i8, i8, i32, i32) {
; CHECK-LABEL: selectccsgti8: ; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 56 ; CHECK-NEXT: sll %s1, %s1, 56
; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i8 %0, %1 %5 = icmp sgt i8 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsgti16(i16, i16, i32, i32) { define i32 @selectccsgti16(i16, i16, i32, i32) {
; CHECK-LABEL: selectccsgti16: ; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 48 ; CHECK-NEXT: sll %s1, %s1, 48
; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i16 %0, %1 %5 = icmp sgt i16 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsgti32(i32, i32, i32, i32) { define i32 @selectccsgti32(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgti32: ; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1 %5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsgti64(i64, i64, i32, i32) { define i32 @selectccsgti64(i64, i64, i32, i32) {
; CHECK-LABEL: selectccsgti64: ; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1 %5 = icmp sgt i64 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsgti128(i128, i128, i32, i32) { define i32 @selectccsgti128(i128, i128, i32, i32) {
; CHECK-LABEL: selectccsgti128: ; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1 ; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1 ; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2 ; CHECK-NEXT: cmpu.l %s0, %s0, %s2
; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1 ; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 ; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1 %5 = icmp sgt i128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccogtf32(float, float, i32, i32) { define i32 @selectccogtf32(float, float, i32, i32) {
; CHECK-LABEL: selectccogtf32: ; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1 %5 = fcmp ogt float %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccogtf64(double, double, i32, i32) { define i32 @selectccogtf64(double, double, i32, i32) {
; CHECK-LABEL: selectccogtf64: ; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1 %5 = fcmp ogt double %0, %1
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }

llvm/test/CodeGen/VE/Scalar/selectcci32i.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define i32 @selectcceq(i32, i32, i32, i32) { define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq: ; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, 12 %5 = icmp eq i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccne(i32, i32, i32, i32) { define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne: ; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ne i32 %0, 12 %5 = icmp ne i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsgt(i32, i32, i32, i32) { define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt: ; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, 12 %5 = icmp sgt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsge(i32, i32, i32, i32) { define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge: ; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i32 %0, 12 %5 = icmp sge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccslt(i32, i32, i32, i32) { define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt: ; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i32 %0, 12 %5 = icmp slt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccsle(i32, i32, i32, i32) { define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle: ; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i32 %0, 12 %5 = icmp sle i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccugt(i32, i32, i32, i32) { define i32 @selectccugt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt: ; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, 12 %5 = icmp ugt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccuge(i32, i32, i32, i32) { define i32 @selectccuge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge: ; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, 12 %5 = icmp uge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccult(i32, i32, i32, i32) { define i32 @selectccult(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult: ; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, 12 %5 = icmp ult i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccule(i32, i32, i32, i32) { define i32 @selectccule(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule: ; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, 12 %5 = icmp ule i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccugt2(i32, i32, i32, i32) { define i32 @selectccugt2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt2: ; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, 12 %5 = icmp ugt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccuge2(i32, i32, i32, i32) { define i32 @selectccuge2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge2: ; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, 12 %5 = icmp uge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccult2(i32, i32, i32, i32) { define i32 @selectccult2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult2: ; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, 12 %5 = icmp ult i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }
define i32 @selectccule2(i32, i32, i32, i32) { define i32 @selectccule2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule2: ; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, 12 %5 = icmp ule i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3 %6 = select i1 %5, i32 %2, i32 %3
ret i32 %6 ret i32 %6
} }

llvm/test/CodeGen/VE/Scalar/selectcci64.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define i64 @selectcceq(i64, i64, i64, i64) { define i64 @selectcceq(i64, i64, i64, i64) {
; CHECK-LABEL: selectcceq: ; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1 %5 = icmp eq i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccne(i64, i64, i64, i64) { define i64 @selectccne(i64, i64, i64, i64) {
; CHECK-LABEL: selectccne: ; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ne i64 %0, %1 %5 = icmp ne i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsgt(i64, i64, i64, i64) { define i64 @selectccsgt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsgt: ; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1 %5 = icmp sgt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsge(i64, i64, i64, i64) { define i64 @selectccsge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsge: ; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i64 %0, %1 %5 = icmp sge i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccslt(i64, i64, i64, i64) { define i64 @selectccslt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccslt: ; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i64 %0, %1 %5 = icmp slt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsle(i64, i64, i64, i64) { define i64 @selectccsle(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsle: ; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i64 %0, %1 %5 = icmp sle i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccugt(i64, i64, i64, i64) { define i64 @selectccugt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt: ; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, %1 %5 = icmp ugt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccuge(i64, i64, i64, i64) { define i64 @selectccuge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge: ; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, %1 %5 = icmp uge i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccult(i64, i64, i64, i64) { define i64 @selectccult(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult: ; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, %1 %5 = icmp ult i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccule(i64, i64, i64, i64) { define i64 @selectccule(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule: ; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, %1 %5 = icmp ule i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccugt2(i64, i64, i64, i64) { define i64 @selectccugt2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt2: ; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, %1 %5 = icmp ugt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccuge2(i64, i64, i64, i64) { define i64 @selectccuge2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge2: ; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, %1 %5 = icmp uge i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccult2(i64, i64, i64, i64) { define i64 @selectccult2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult2: ; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, %1 %5 = icmp ult i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccule2(i64, i64, i64, i64) { define i64 @selectccule2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule2: ; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.le %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, %1 %5 = icmp ule i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }

llvm/test/CodeGen/VE/Scalar/selectcci64c.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define i64 @selectccsgti8(i8, i8, i64, i64) { define i64 @selectccsgti8(i8, i8, i64, i64) {
; CHECK-LABEL: selectccsgti8: ; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 56 ; CHECK-NEXT: sll %s1, %s1, 56
; CHECK-NEXT: sra.l %s1, %s1, 56 ; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i8 %0, %1 %5 = icmp sgt i8 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsgti16(i16, i16, i64, i64) { define i64 @selectccsgti16(i16, i16, i64, i64) {
; CHECK-LABEL: selectccsgti16: ; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 48 ; CHECK-NEXT: sll %s1, %s1, 48
; CHECK-NEXT: sra.l %s1, %s1, 48 ; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i16 %0, %1 %5 = icmp sgt i16 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsgti32(i32, i32, i64, i64) { define i64 @selectccsgti32(i32, i32, i64, i64) {
; CHECK-LABEL: selectccsgti32: ; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1 %5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsgti64(i64, i64, i64, i64) { define i64 @selectccsgti64(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsgti64: ; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1 %5 = icmp sgt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsgti128(i128, i128, i64, i64) { define i64 @selectccsgti128(i128, i128, i64, i64) {
; CHECK-LABEL: selectccsgti128: ; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, %s3 ; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1 ; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1 ; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2 ; CHECK-NEXT: cmpu.l %s0, %s0, %s2
; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1 ; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3 ; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 ; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5 ; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1 %5 = icmp sgt i128 %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccogtf32(float, float, i64, i64) { define i64 @selectccogtf32(float, float, i64, i64) {
; CHECK-LABEL: selectccogtf32: ; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1 %5 = fcmp ogt float %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccogtf64(double, double, i64, i64) { define i64 @selectccogtf64(double, double, i64, i64) {
; CHECK-LABEL: selectccogtf64: ; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1 %5 = fcmp ogt double %0, %1
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }

llvm/test/CodeGen/VE/Scalar/selectcci64i.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define i64 @selectcceq(i64, i64, i64, i64) { define i64 @selectcceq(i64, i64, i64, i64) {
; CHECK-LABEL: selectcceq: ; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, 12 %5 = icmp eq i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccne(i64, i64, i64, i64) { define i64 @selectccne(i64, i64, i64, i64) {
; CHECK-LABEL: selectccne: ; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ne i64 %0, 12 %5 = icmp ne i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsgt(i64, i64, i64, i64) { define i64 @selectccsgt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsgt: ; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, 12 %5 = icmp sgt i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsge(i64, i64, i64, i64) { define i64 @selectccsge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsge: ; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i64 %0, 12 %5 = icmp sge i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccslt(i64, i64, i64, i64) { define i64 @selectccslt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccslt: ; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i64 %0, 12 %5 = icmp slt i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccsle(i64, i64, i64, i64) { define i64 @selectccsle(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsle: ; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i64 %0, 12 %5 = icmp sle i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccugt(i64, i64, i64, i64) { define i64 @selectccugt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt: ; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, 12 %5 = icmp ugt i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccuge(i64, i64, i64, i64) { define i64 @selectccuge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge: ; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, 12 %5 = icmp uge i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccult(i64, i64, i64, i64) { define i64 @selectccult(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult: ; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, 12 %5 = icmp ult i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccule(i64, i64, i64, i64) { define i64 @selectccule(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule: ; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, 12 %5 = icmp ule i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccugt2(i64, i64, i64, i64) { define i64 @selectccugt2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt2: ; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, 12 %5 = icmp ugt i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccuge2(i64, i64, i64, i64) { define i64 @selectccuge2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge2: ; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, 12 %5 = icmp uge i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccult2(i64, i64, i64, i64) { define i64 @selectccult2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult2: ; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, 12 %5 = icmp ult i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }
define i64 @selectccule2(i64, i64, i64, i64) { define i64 @selectccule2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule2: ; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 ; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3 ; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, 12 %5 = icmp ule i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3 %6 = select i1 %5, i64 %2, i64 %3
ret i64 %6 ret i64 %6
} }

llvm/test/CodeGen/VE/Scalar/setcc.ll

; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve | FileCheck %s
;;; Test all combination of input type and output type among following types. ;;; Test all combination of input type and output type among following types.
;;; ;;;
;;; Types: ;;; Types:
;;; i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128 ;;; i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i1(i1 zeroext %0, i1 zeroext %1) { define zeroext i1 @setcc_i1(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: setcc_i1: ; CHECK-LABEL: setcc_i1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: xor %s0, 1, %s0 ; CHECK-NEXT: xor %s0, 1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, %1 %3 = xor i1 %0, %1
%4 = xor i1 %3, true %4 = xor i1 %3, true
ret i1 %4 ret i1 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i8(i8 signext %0, i8 signext %1) { define zeroext i1 @setcc_i8(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: setcc_i8: ; CHECK-LABEL: setcc_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1 %3 = icmp eq i8 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u8(i8 zeroext %0, i8 zeroext %1) { define zeroext i1 @setcc_u8(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: setcc_u8: ; CHECK-LABEL: setcc_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1 %3 = icmp eq i8 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i16(i16 signext %0, i16 signext %1) { define zeroext i1 @setcc_i16(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: setcc_i16: ; CHECK-LABEL: setcc_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1 %3 = icmp eq i16 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u16(i16 zeroext %0, i16 zeroext %1) { define zeroext i1 @setcc_u16(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: setcc_u16: ; CHECK-LABEL: setcc_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1 %3 = icmp eq i16 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i32(i32 signext %0, i32 signext %1) { define zeroext i1 @setcc_i32(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: setcc_i32: ; CHECK-LABEL: setcc_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1 %3 = icmp eq i32 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u32(i32 zeroext %0, i32 zeroext %1) { define zeroext i1 @setcc_u32(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: setcc_u32: ; CHECK-LABEL: setcc_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1 %3 = icmp eq i32 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i64(i64 %0, i64 %1) { define zeroext i1 @setcc_i64(i64 %0, i64 %1) {
; CHECK-LABEL: setcc_i64: ; CHECK-LABEL: setcc_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1 %3 = icmp eq i64 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u64(i64 %0, i64 %1) { define zeroext i1 @setcc_u64(i64 %0, i64 %1) {
; CHECK-LABEL: setcc_u64: ; CHECK-LABEL: setcc_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1 %3 = icmp eq i64 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i128(i128 %0, i128 %1) { define zeroext i1 @setcc_i128(i128 %0, i128 %1) {
; CHECK-LABEL: setcc_i128: ; CHECK-LABEL: setcc_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1 %3 = icmp eq i128 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u128(i128 %0, i128 %1) { define zeroext i1 @setcc_u128(i128 %0, i128 %1) {
; CHECK-LABEL: setcc_u128: ; CHECK-LABEL: setcc_u128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3 ; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2 ; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1 ; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, (0)1 ; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1 %3 = icmp eq i128 %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_float(float %0, float %1) { define zeroext i1 @setcc_float(float %0, float %1) {
; CHECK-LABEL: setcc_float: ; CHECK-LABEL: setcc_float:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq float %0, %1 %3 = fcmp fast oeq float %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_double(double %0, double %1) { define zeroext i1 @setcc_double(double %0, double %1) {
; CHECK-LABEL: setcc_double: ; CHECK-LABEL: setcc_double:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq double %0, %1 %3 = fcmp fast oeq double %0, %1
ret i1 %3 ret i1 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_quad(fp128 %0, fp128 %1) { define zeroext i1 @setcc_quad(fp128 %0, fp128 %1) {
; CHECK-LABEL: setcc_quad: ; CHECK-LABEL: setcc_quad:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2 ; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq fp128 %0, %1 %3 = fcmp fast oeq fp128 %0, %1
ret i1 %3 ret i1 %3
} }

llvm/test/CodeGen/VE/Scalar/setccf32.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setccaf(float, float) { define zeroext i1 @setccaf(float, float) {
; CHECK-LABEL: setccaf: ; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp false float %0, %1 %3 = fcmp false float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccat(float, float) { define zeroext i1 @setccat(float, float) {
; CHECK-LABEL: setccat: ; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp true float %0, %1 %3 = fcmp true float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccoeq(float, float) { define zeroext i1 @setccoeq(float, float) {
; CHECK-LABEL: setccoeq: ; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oeq float %0, %1 %3 = fcmp oeq float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccone(float, float) { define zeroext i1 @setccone(float, float) {
; CHECK-LABEL: setccone: ; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp one float %0, %1 %3 = fcmp one float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccogt(float, float) { define zeroext i1 @setccogt(float, float) {
; CHECK-LABEL: setccogt: ; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt float %0, %1 %3 = fcmp ogt float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccoge(float, float) { define zeroext i1 @setccoge(float, float) {
; CHECK-LABEL: setccoge: ; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge float %0, %1 %3 = fcmp oge float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccolt(float, float) { define zeroext i1 @setccolt(float, float) {
; CHECK-LABEL: setccolt: ; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt float %0, %1 %3 = fcmp olt float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccole(float, float) { define zeroext i1 @setccole(float, float) {
; CHECK-LABEL: setccole: ; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole float %0, %1 %3 = fcmp ole float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccord(float, float) { define zeroext i1 @setccord(float, float) {
; CHECK-LABEL: setccord: ; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ord float %0, %1 %3 = fcmp ord float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuno(float, float) { define zeroext i1 @setccuno(float, float) {
; CHECK-LABEL: setccuno: ; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uno float %0, %1 %3 = fcmp uno float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccueq(float, float) { define zeroext i1 @setccueq(float, float) {
; CHECK-LABEL: setccueq: ; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ueq float %0, %1 %3 = fcmp ueq float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccune(float, float) { define zeroext i1 @setccune(float, float) {
; CHECK-LABEL: setccune: ; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp une float %0, %1 %3 = fcmp une float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccugt(float, float) { define zeroext i1 @setccugt(float, float) {
; CHECK-LABEL: setccugt: ; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt float %0, %1 %3 = fcmp ugt float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuge(float, float) { define zeroext i1 @setccuge(float, float) {
; CHECK-LABEL: setccuge: ; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge float %0, %1 %3 = fcmp uge float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccult(float, float) { define zeroext i1 @setccult(float, float) {
; CHECK-LABEL: setccult: ; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult float %0, %1 %3 = fcmp ult float %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccule(float, float) { define zeroext i1 @setccule(float, float) {
; CHECK-LABEL: setccule: ; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule float %0, %1 %3 = fcmp ule float %0, %1
ret i1 %3 ret i1 %3
} }

llvm/test/CodeGen/VE/Scalar/setccf32i.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setccaf(float, float) { define zeroext i1 @setccaf(float, float) {
; CHECK-LABEL: setccaf: ; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp false float %0, 0.0 %3 = fcmp false float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccat(float, float) { define zeroext i1 @setccat(float, float) {
; CHECK-LABEL: setccat: ; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp true float %0, 0.0 %3 = fcmp true float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccoeq(float, float) { define zeroext i1 @setccoeq(float, float) {
; CHECK-LABEL: setccoeq: ; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oeq float %0, 0.0 %3 = fcmp oeq float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccone(float, float) { define zeroext i1 @setccone(float, float) {
; CHECK-LABEL: setccone: ; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp one float %0, 0.0 %3 = fcmp one float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccogt(float, float) { define zeroext i1 @setccogt(float, float) {
; CHECK-LABEL: setccogt: ; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt float %0, 0.0 %3 = fcmp ogt float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccoge(float, float) { define zeroext i1 @setccoge(float, float) {
; CHECK-LABEL: setccoge: ; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge float %0, 0.0 %3 = fcmp oge float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccolt(float, float) { define zeroext i1 @setccolt(float, float) {
; CHECK-LABEL: setccolt: ; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt float %0, 0.0 %3 = fcmp olt float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccole(float, float) { define zeroext i1 @setccole(float, float) {
; CHECK-LABEL: setccole: ; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole float %0, 0.0 %3 = fcmp ole float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccord(float, float) { define zeroext i1 @setccord(float, float) {
; CHECK-LABEL: setccord: ; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ord float %0, 0.0 %3 = fcmp ord float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuno(float, float) { define zeroext i1 @setccuno(float, float) {
; CHECK-LABEL: setccuno: ; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s0 ; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uno float %0, 0.0 %3 = fcmp uno float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccueq(float, float) { define zeroext i1 @setccueq(float, float) {
; CHECK-LABEL: setccueq: ; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ueq float %0, 0.0 %3 = fcmp ueq float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccune(float, float) { define zeroext i1 @setccune(float, float) {
; CHECK-LABEL: setccune: ; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp une float %0, 0.0 %3 = fcmp une float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccugt(float, float) { define zeroext i1 @setccugt(float, float) {
; CHECK-LABEL: setccugt: ; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt float %0, 0.0 %3 = fcmp ugt float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuge(float, float) { define zeroext i1 @setccuge(float, float) {
; CHECK-LABEL: setccuge: ; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge float %0, 0.0 %3 = fcmp uge float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccult(float, float) { define zeroext i1 @setccult(float, float) {
; CHECK-LABEL: setccult: ; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult float %0, 0.0 %3 = fcmp ult float %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccule(float, float) { define zeroext i1 @setccule(float, float) {
; CHECK-LABEL: setccule: ; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule float %0, 0.0 %3 = fcmp ule float %0, 0.0
ret i1 %3 ret i1 %3
} }

llvm/test/CodeGen/VE/Scalar/setccf64.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setccaf(double, double) { define zeroext i1 @setccaf(double, double) {
; CHECK-LABEL: setccaf: ; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp false double %0, %1 %3 = fcmp false double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccat(double, double) { define zeroext i1 @setccat(double, double) {
; CHECK-LABEL: setccat: ; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp true double %0, %1 %3 = fcmp true double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccoeq(double, double) { define zeroext i1 @setccoeq(double, double) {
; CHECK-LABEL: setccoeq: ; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oeq double %0, %1 %3 = fcmp oeq double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccone(double, double) { define zeroext i1 @setccone(double, double) {
; CHECK-LABEL: setccone: ; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp one double %0, %1 %3 = fcmp one double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccogt(double, double) { define zeroext i1 @setccogt(double, double) {
; CHECK-LABEL: setccogt: ; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt double %0, %1 %3 = fcmp ogt double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccoge(double, double) { define zeroext i1 @setccoge(double, double) {
; CHECK-LABEL: setccoge: ; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge double %0, %1 %3 = fcmp oge double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccolt(double, double) { define zeroext i1 @setccolt(double, double) {
; CHECK-LABEL: setccolt: ; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt double %0, %1 %3 = fcmp olt double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccole(double, double) { define zeroext i1 @setccole(double, double) {
; CHECK-LABEL: setccole: ; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole double %0, %1 %3 = fcmp ole double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccord(double, double) { define zeroext i1 @setccord(double, double) {
; CHECK-LABEL: setccord: ; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ord double %0, %1 %3 = fcmp ord double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuno(double, double) { define zeroext i1 @setccuno(double, double) {
; CHECK-LABEL: setccuno: ; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uno double %0, %1 %3 = fcmp uno double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccueq(double, double) { define zeroext i1 @setccueq(double, double) {
; CHECK-LABEL: setccueq: ; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ueq double %0, %1 %3 = fcmp ueq double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccune(double, double) { define zeroext i1 @setccune(double, double) {
; CHECK-LABEL: setccune: ; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp une double %0, %1 %3 = fcmp une double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccugt(double, double) { define zeroext i1 @setccugt(double, double) {
; CHECK-LABEL: setccugt: ; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt double %0, %1 %3 = fcmp ugt double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuge(double, double) { define zeroext i1 @setccuge(double, double) {
; CHECK-LABEL: setccuge: ; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge double %0, %1 %3 = fcmp uge double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccult(double, double) { define zeroext i1 @setccult(double, double) {
; CHECK-LABEL: setccult: ; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult double %0, %1 %3 = fcmp ult double %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccule(double, double) { define zeroext i1 @setccule(double, double) {
; CHECK-LABEL: setccule: ; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule double %0, %1 %3 = fcmp ule double %0, %1
ret i1 %3 ret i1 %3
} }

llvm/test/CodeGen/VE/Scalar/setccf64i.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setccaf(double, double) { define zeroext i1 @setccaf(double, double) {
; CHECK-LABEL: setccaf: ; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp false double %0, 0.0 %3 = fcmp false double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccat(double, double) { define zeroext i1 @setccat(double, double) {
; CHECK-LABEL: setccat: ; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp true double %0, 0.0 %3 = fcmp true double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccoeq(double, double) { define zeroext i1 @setccoeq(double, double) {
; CHECK-LABEL: setccoeq: ; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oeq double %0, 0.0 %3 = fcmp oeq double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccone(double, double) { define zeroext i1 @setccone(double, double) {
; CHECK-LABEL: setccone: ; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp one double %0, 0.0 %3 = fcmp one double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccogt(double, double) { define zeroext i1 @setccogt(double, double) {
; CHECK-LABEL: setccogt: ; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt double %0, 0.0 %3 = fcmp ogt double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccoge(double, double) { define zeroext i1 @setccoge(double, double) {
; CHECK-LABEL: setccoge: ; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge double %0, 0.0 %3 = fcmp oge double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccolt(double, double) { define zeroext i1 @setccolt(double, double) {
; CHECK-LABEL: setccolt: ; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt double %0, 0.0 %3 = fcmp olt double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccole(double, double) { define zeroext i1 @setccole(double, double) {
; CHECK-LABEL: setccole: ; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole double %0, 0.0 %3 = fcmp ole double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccord(double, double) { define zeroext i1 @setccord(double, double) {
; CHECK-LABEL: setccord: ; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s0
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ord double %0, 0.0 %3 = fcmp ord double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuno(double, double) { define zeroext i1 @setccuno(double, double) {
; CHECK-LABEL: setccuno: ; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s0 ; CHECK-NEXT: fcmp.d %s0, %s0, %s0
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uno double %0, 0.0 %3 = fcmp uno double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccueq(double, double) { define zeroext i1 @setccueq(double, double) {
; CHECK-LABEL: setccueq: ; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ueq double %0, 0.0 %3 = fcmp ueq double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccune(double, double) { define zeroext i1 @setccune(double, double) {
; CHECK-LABEL: setccune: ; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp une double %0, 0.0 %3 = fcmp une double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccugt(double, double) { define zeroext i1 @setccugt(double, double) {
; CHECK-LABEL: setccugt: ; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt double %0, 0.0 %3 = fcmp ugt double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuge(double, double) { define zeroext i1 @setccuge(double, double) {
; CHECK-LABEL: setccuge: ; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge double %0, 0.0 %3 = fcmp uge double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccult(double, double) { define zeroext i1 @setccult(double, double) {
; CHECK-LABEL: setccult: ; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult double %0, 0.0 %3 = fcmp ult double %0, 0.0
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccule(double, double) { define zeroext i1 @setccule(double, double) {
; CHECK-LABEL: setccule: ; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0 ; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0 ; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule double %0, 0.0 %3 = fcmp ule double %0, 0.0
ret i1 %3 ret i1 %3
} }

llvm/test/CodeGen/VE/Scalar/setcci32.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setcceq(i32, i32) { define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq: ; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1 %3 = icmp eq i32 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccne(i32, i32) { define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne: ; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ne i32 %0, %1 %3 = icmp ne i32 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccugt(i32, i32) { define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt: ; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i32 %0, %1 %3 = icmp ugt i32 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuge(i32, i32) { define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge: ; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i32 %0, %1 %3 = icmp uge i32 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccult(i32, i32) { define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult: ; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i32 %0, %1 %3 = icmp ult i32 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccule(i32, i32) { define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule: ; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i32 %0, %1 %3 = icmp ule i32 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsgt(i32, i32) { define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt: ; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i32 %0, %1 %3 = icmp sgt i32 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsge(i32, i32) { define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge: ; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i32 %0, %1 %3 = icmp sge i32 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccslt(i32, i32) { define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt: ; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i32 %0, %1 %3 = icmp slt i32 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsle(i32, i32) { define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle: ; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i32 %0, %1 %3 = icmp sle i32 %0, %1
ret i1 %3 ret i1 %3
} }

llvm/test/CodeGen/VE/Scalar/setcci32i.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setcceq(i32, i32) { define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq: ; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, 12 %3 = icmp eq i32 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccne(i32, i32) { define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne: ; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ne i32 %0, 12 %3 = icmp ne i32 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccugt(i32, i32) { define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt: ; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i32 %0, 12 %3 = icmp ugt i32 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuge(i32, i32) { define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge: ; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i32 %0, 12 %3 = icmp uge i32 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccult(i32, i32) { define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult: ; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i32 %0, 12 %3 = icmp ult i32 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccule(i32, i32) { define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule: ; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i32 %0, 12 %3 = icmp ule i32 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsgt(i32, i32) { define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt: ; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i32 %0, 12 %3 = icmp sgt i32 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsge(i32, i32) { define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge: ; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i32 %0, 12 %3 = icmp sge i32 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccslt(i32, i32) { define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt: ; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i32 %0, 12 %3 = icmp slt i32 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsle(i32, i32) { define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle: ; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i32 %0, 12 %3 = icmp sle i32 %0, 12
ret i1 %3 ret i1 %3
} }

llvm/test/CodeGen/VE/Scalar/setcci64.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setcceq(i64, i64) { define zeroext i1 @setcceq(i64, i64) {
; CHECK-LABEL: setcceq: ; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1 %3 = icmp eq i64 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccne(i64, i64) { define zeroext i1 @setccne(i64, i64) {
; CHECK-LABEL: setccne: ; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ne i64 %0, %1 %3 = icmp ne i64 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccugt(i64, i64) { define zeroext i1 @setccugt(i64, i64) {
; CHECK-LABEL: setccugt: ; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i64 %0, %1 %3 = icmp ugt i64 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuge(i64, i64) { define zeroext i1 @setccuge(i64, i64) {
; CHECK-LABEL: setccuge: ; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i64 %0, %1 %3 = icmp uge i64 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccult(i64, i64) { define zeroext i1 @setccult(i64, i64) {
; CHECK-LABEL: setccult: ; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i64 %0, %1 %3 = icmp ult i64 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccule(i64, i64) { define zeroext i1 @setccule(i64, i64) {
; CHECK-LABEL: setccule: ; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i64 %0, %1 %3 = icmp ule i64 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsgt(i64, i64) { define zeroext i1 @setccsgt(i64, i64) {
; CHECK-LABEL: setccsgt: ; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i64 %0, %1 %3 = icmp sgt i64 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsge(i64, i64) { define zeroext i1 @setccsge(i64, i64) {
; CHECK-LABEL: setccsge: ; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i64 %0, %1 %3 = icmp sge i64 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccslt(i64, i64) { define zeroext i1 @setccslt(i64, i64) {
; CHECK-LABEL: setccslt: ; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i64 %0, %1 %3 = icmp slt i64 %0, %1
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsle(i64, i64) { define zeroext i1 @setccsle(i64, i64) {
; CHECK-LABEL: setccsle: ; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i64 %0, %1 %3 = icmp sle i64 %0, %1
ret i1 %3 ret i1 %3
} }

llvm/test/CodeGen/VE/Scalar/setcci64i.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setcceq(i64, i64) { define zeroext i1 @setcceq(i64, i64) {
; CHECK-LABEL: setcceq: ; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, 12 %3 = icmp eq i64 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccne(i64, i64) { define zeroext i1 @setccne(i64, i64) {
; CHECK-LABEL: setccne: ; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ne i64 %0, 12 %3 = icmp ne i64 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccugt(i64, i64) { define zeroext i1 @setccugt(i64, i64) {
; CHECK-LABEL: setccugt: ; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i64 %0, 12 %3 = icmp ugt i64 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccuge(i64, i64) { define zeroext i1 @setccuge(i64, i64) {
; CHECK-LABEL: setccuge: ; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i64 %0, 12 %3 = icmp uge i64 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccult(i64, i64) { define zeroext i1 @setccult(i64, i64) {
; CHECK-LABEL: setccult: ; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i64 %0, 12 %3 = icmp ult i64 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccule(i64, i64) { define zeroext i1 @setccule(i64, i64) {
; CHECK-LABEL: setccule: ; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1 ; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i64 %0, 12 %3 = icmp ule i64 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsgt(i64, i64) { define zeroext i1 @setccsgt(i64, i64) {
; CHECK-LABEL: setccsgt: ; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i64 %0, 12 %3 = icmp sgt i64 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsge(i64, i64) { define zeroext i1 @setccsge(i64, i64) {
; CHECK-LABEL: setccsge: ; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1 ; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i64 %0, 12 %3 = icmp sge i64 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccslt(i64, i64) { define zeroext i1 @setccslt(i64, i64) {
; CHECK-LABEL: setccslt: ; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1 ; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i64 %0, 12 %3 = icmp slt i64 %0, 12
ret i1 %3 ret i1 %3
} }
define zeroext i1 @setccsle(i64, i64) { define zeroext i1 @setccsle(i64, i64) {
; CHECK-LABEL: setccsle: ; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1 ; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i64 %0, 12 %3 = icmp sle i64 %0, 12
ret i1 %3 ret i1 %3
} }

llvm/test/CodeGen/VE/Scalar/shl.ll

Show All 36 Lines
;;; ; yields: result=<2 x i32> < i32 2, i32 4> ;;; ; yields: result=<2 x i32> < i32 2, i32 4>
;;; ;;;
;;; Note: ;;; Note:
;;; We test only i8/i16/i32/i64/i128 and unsigned of them. ;;; We test only i8/i16/i32/i64/i128 and unsigned of them.
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) { define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: shl_i8_var: ; CHECK-LABEL: shl_i8_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (56)0 ; CHECK-NEXT: and %s1, %s1, (56)0
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i8 %0 to i32 %3 = sext i8 %0 to i32
%4 = zext i8 %1 to i32 %4 = zext i8 %1 to i32
%5 = shl i32 %3, %4 %5 = shl i32 %3, %4
%6 = trunc i32 %5 to i8 %6 = trunc i32 %5 to i8
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) { define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: shl_u8_var: ; CHECK-LABEL: shl_u8_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i8 %0 to i32 %3 = zext i8 %0 to i32
%4 = zext i8 %1 to i32 %4 = zext i8 %1 to i32
%5 = shl i32 %3, %4 %5 = shl i32 %3, %4
%6 = trunc i32 %5 to i8 %6 = trunc i32 %5 to i8
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) { define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: shl_i16_var: ; CHECK-LABEL: shl_i16_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (48)0 ; CHECK-NEXT: and %s1, %s1, (48)0
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i16 %0 to i32 %3 = sext i16 %0 to i32
%4 = zext i16 %1 to i32 %4 = zext i16 %1 to i32
%5 = shl i32 %3, %4 %5 = shl i32 %3, %4
%6 = trunc i32 %5 to i16 %6 = trunc i32 %5 to i16
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) { define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: shl_u16_var: ; CHECK-LABEL: shl_u16_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i16 %0 to i32 %3 = zext i16 %0 to i32
%4 = zext i16 %1 to i32 %4 = zext i16 %1 to i32
%5 = shl i32 %3, %4 %5 = shl i32 %3, %4
%6 = trunc i32 %5 to i16 %6 = trunc i32 %5 to i16
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) { define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: shl_i32_var: ; CHECK-LABEL: shl_i32_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i32 %0, %1 %3 = shl i32 %0, %1
ret i32 %3 ret i32 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) { define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: shl_u32_var: ; CHECK-LABEL: shl_u32_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i32 %0, %1 %3 = shl i32 %0, %1
ret i32 %3 ret i32 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_i64_var(i64 %0, i64 %1) { define i64 @shl_i64_var(i64 %0, i64 %1) {
; CHECK-LABEL: shl_i64_var: ; CHECK-LABEL: shl_i64_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i64 %0, %1 %3 = shl i64 %0, %1
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_u64_var(i64 %0, i64 %1) { define i64 @shl_u64_var(i64 %0, i64 %1) {
; CHECK-LABEL: shl_u64_var: ; CHECK-LABEL: shl_u64_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, %s1 ; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i64 %0, %1 %3 = shl i64 %0, %1
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @shl_i128_var(i128 %0, i128 %1) { define i128 @shl_i128_var(i128 %0, i128 %1) {
; CHECK-LABEL: shl_i128_var: ; CHECK-LABEL: shl_i128_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
Show All 19 Lines
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = shl i128 %0, %1 %3 = shl i128 %0, %1
ret i128 %3 ret i128 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_const_i8(i8 signext %0) { define signext i8 @shl_const_i8(i8 signext %0) {
; CHECK-LABEL: shl_const_i8: ; CHECK-LABEL: shl_const_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32 %2 = zext i8 %0 to i32
%3 = shl i32 -4, %2 %3 = shl i32 -4, %2
%4 = trunc i32 %3 to i8 %4 = trunc i32 %3 to i8
ret i8 %4 ret i8 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_const_u8(i8 zeroext %0) { define zeroext i8 @shl_const_u8(i8 zeroext %0) {
; CHECK-LABEL: shl_const_u8: ; CHECK-LABEL: shl_const_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: lea %s1, 252 ; CHECK-NEXT: lea %s1, 252
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32 %2 = zext i8 %0 to i32
%3 = shl i32 -4, %2 %3 = shl i32 -4, %2
%4 = trunc i32 %3 to i8 %4 = trunc i32 %3 to i8
ret i8 %4 ret i8 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_const_i16(i16 signext %0) { define signext i16 @shl_const_i16(i16 signext %0) {
; CHECK-LABEL: shl_const_i16: ; CHECK-LABEL: shl_const_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32 %2 = zext i16 %0 to i32
%3 = shl i32 -4, %2 %3 = shl i32 -4, %2
%4 = trunc i32 %3 to i16 %4 = trunc i32 %3 to i16
ret i16 %4 ret i16 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_const_u16(i16 zeroext %0) { define zeroext i16 @shl_const_u16(i16 zeroext %0) {
; CHECK-LABEL: shl_const_u16: ; CHECK-LABEL: shl_const_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: lea %s1, 65532 ; CHECK-NEXT: lea %s1, 65532
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32 %2 = zext i16 %0 to i32
%3 = shl i32 -4, %2 %3 = shl i32 -4, %2
%4 = trunc i32 %3 to i16 %4 = trunc i32 %3 to i16
ret i16 %4 ret i16 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_const_i32(i32 signext %0) { define signext i32 @shl_const_i32(i32 signext %0) {
; CHECK-LABEL: shl_const_i32: ; CHECK-LABEL: shl_const_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 -4, %0 %2 = shl i32 -4, %0
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_const_u32(i32 zeroext %0) { define zeroext i32 @shl_const_u32(i32 zeroext %0) {
; CHECK-LABEL: shl_const_u32: ; CHECK-LABEL: shl_const_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 -4, %0 %2 = shl i32 -4, %0
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_const_i64(i64 %0) { define i64 @shl_const_i64(i64 %0) {
; CHECK-LABEL: shl_const_i64: ; CHECK-LABEL: shl_const_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, (62)1, %s0 ; CHECK-NEXT: sll %s0, (62)1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 -4, %0 %2 = shl i64 -4, %0
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_const_u64(i64 %0) { define i64 @shl_const_u64(i64 %0) {
; CHECK-LABEL: shl_const_u64: ; CHECK-LABEL: shl_const_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, (62)1, %s0 ; CHECK-NEXT: sll %s0, (62)1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 -4, %0 %2 = shl i64 -4, %0
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @shl_const_i128(i128 %0) { define i128 @shl_const_i128(i128 %0) {
; CHECK-LABEL: shl_const_i128: ; CHECK-LABEL: shl_const_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
Show All 23 Lines
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = shl i128 -4, %0 %2 = shl i128 -4, %0
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_i8_const(i8 signext %0) { define signext i8 @shl_i8_const(i8 signext %0) {
; CHECK-LABEL: shl_i8_const: ; CHECK-LABEL: shl_i8_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 3 ; CHECK-NEXT: sla.w.sx %s0, %s0, 3
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i8 %0, 3 %2 = shl i8 %0, 3
ret i8 %2 ret i8 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_u8_const(i8 zeroext %0) { define zeroext i8 @shl_u8_const(i8 zeroext %0) {
; CHECK-LABEL: shl_u8_const: ; CHECK-LABEL: shl_u8_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 3 ; CHECK-NEXT: sla.w.sx %s0, %s0, 3
; CHECK-NEXT: lea %s1, 248 ; CHECK-NEXT: lea %s1, 248
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i8 %0, 3 %2 = shl i8 %0, 3
ret i8 %2 ret i8 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_i16_const(i16 signext %0) { define signext i16 @shl_i16_const(i16 signext %0) {
; CHECK-LABEL: shl_i16_const: ; CHECK-LABEL: shl_i16_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 7 ; CHECK-NEXT: sla.w.sx %s0, %s0, 7
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i16 %0, 7 %2 = shl i16 %0, 7
ret i16 %2 ret i16 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_u16_const(i16 zeroext %0) { define zeroext i16 @shl_u16_const(i16 zeroext %0) {
; CHECK-LABEL: shl_u16_const: ; CHECK-LABEL: shl_u16_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 7 ; CHECK-NEXT: sla.w.sx %s0, %s0, 7
; CHECK-NEXT: lea %s1, 65408 ; CHECK-NEXT: lea %s1, 65408
; CHECK-NEXT: and %s0, %s0, %s1 ; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i16 %0, 7 %2 = shl i16 %0, 7
ret i16 %2 ret i16 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_i32_const(i32 signext %0) { define signext i32 @shl_i32_const(i32 signext %0) {
; CHECK-LABEL: shl_i32_const: ; CHECK-LABEL: shl_i32_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 15 ; CHECK-NEXT: sla.w.sx %s0, %s0, 15
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 %0, 15 %2 = shl i32 %0, 15
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_u32_const(i32 zeroext %0) { define zeroext i32 @shl_u32_const(i32 zeroext %0) {
; CHECK-LABEL: shl_u32_const: ; CHECK-LABEL: shl_u32_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 15 ; CHECK-NEXT: sla.w.sx %s0, %s0, 15
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 %0, 15 %2 = shl i32 %0, 15
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_i64_const(i64 %0) { define i64 @shl_i64_const(i64 %0) {
; CHECK-LABEL: shl_i64_const: ; CHECK-LABEL: shl_i64_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 63 ; CHECK-NEXT: sll %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 %0, 63 %2 = shl i64 %0, 63
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_u64_const(i64 %0) { define i64 @shl_u64_const(i64 %0) {
; CHECK-LABEL: shl_u64_const: ; CHECK-LABEL: shl_u64_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 63 ; CHECK-NEXT: sll %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 %0, 63 %2 = shl i64 %0, 63
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @shl_i128_const(i128 %0) { define i128 @shl_i128_const(i128 %0) {
; CHECK-LABEL: shl_i128_const: ; CHECK-LABEL: shl_i128_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s0, 63 ; CHECK-NEXT: sll %s1, %s0, 63
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i128 %0, 127 %2 = shl i128 %0, 127
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @shl_u128_const(i128 %0) { define i128 @shl_u128_const(i128 %0) {
; CHECK-LABEL: shl_u128_const: ; CHECK-LABEL: shl_u128_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s0, 63 ; CHECK-NEXT: sll %s1, %s0, 63
; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i128 %0, 127 %2 = shl i128 %0, 127
ret i128 %2 ret i128 %2
} }

llvm/test/CodeGen/VE/Scalar/shr.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
;;; ; yields: result=<2 x i32> < i32 -1, i32 0> ;;; ; yields: result=<2 x i32> < i32 -1, i32 0>
;;; ;;;
;;; Note: ;;; Note:
;;; We test only i8/i16/i32/i64/i128 and unsigned of them. ;;; We test only i8/i16/i32/i64/i128 and unsigned of them.
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) { define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: shl_i8_var: ; CHECK-LABEL: shl_i8_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (56)0 ; CHECK-NEXT: and %s1, %s1, (56)0
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i8 %0 to i32 %3 = sext i8 %0 to i32
%4 = zext i8 %1 to i32 %4 = zext i8 %1 to i32
%5 = ashr i32 %3, %4 %5 = ashr i32 %3, %4
%6 = trunc i32 %5 to i8 %6 = trunc i32 %5 to i8
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) { define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: shl_u8_var: ; CHECK-LABEL: shl_u8_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i8 %0 to i32 %3 = zext i8 %0 to i32
%4 = zext i8 %1 to i32 %4 = zext i8 %1 to i32
%5 = lshr i32 %3, %4 %5 = lshr i32 %3, %4
%6 = trunc i32 %5 to i8 %6 = trunc i32 %5 to i8
ret i8 %6 ret i8 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) { define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: shl_i16_var: ; CHECK-LABEL: shl_i16_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (48)0 ; CHECK-NEXT: and %s1, %s1, (48)0
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i16 %0 to i32 %3 = sext i16 %0 to i32
%4 = zext i16 %1 to i32 %4 = zext i16 %1 to i32
%5 = ashr i32 %3, %4 %5 = ashr i32 %3, %4
%6 = trunc i32 %5 to i16 %6 = trunc i32 %5 to i16
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) { define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: shl_u16_var: ; CHECK-LABEL: shl_u16_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i16 %0 to i32 %3 = zext i16 %0 to i32
%4 = zext i16 %1 to i32 %4 = zext i16 %1 to i32
%5 = lshr i32 %3, %4 %5 = lshr i32 %3, %4
%6 = trunc i32 %5 to i16 %6 = trunc i32 %5 to i16
ret i16 %6 ret i16 %6
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) { define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: shl_i32_var: ; CHECK-LABEL: shl_i32_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = ashr i32 %0, %1 %3 = ashr i32 %0, %1
ret i32 %3 ret i32 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) { define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: shl_u32_var: ; CHECK-LABEL: shl_u32_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = lshr i32 %0, %1 %3 = lshr i32 %0, %1
ret i32 %3 ret i32 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_i64_var(i64 %0, i64 %1) { define i64 @shl_i64_var(i64 %0, i64 %1) {
; CHECK-LABEL: shl_i64_var: ; CHECK-LABEL: shl_i64_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, %s1 ; CHECK-NEXT: sra.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = ashr i64 %0, %1 %3 = ashr i64 %0, %1
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_u64_var(i64 %0, i64 %1) { define i64 @shl_u64_var(i64 %0, i64 %1) {
; CHECK-LABEL: shl_u64_var: ; CHECK-LABEL: shl_u64_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s0, %s1 ; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = lshr i64 %0, %1 %3 = lshr i64 %0, %1
ret i64 %3 ret i64 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @shl_i128_var(i128 %0, i128 %1) { define i128 @shl_i128_var(i128 %0, i128 %1) {
; CHECK-LABEL: shl_i128_var: ; CHECK-LABEL: shl_i128_var:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
Show All 19 Lines
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%3 = lshr i128 %0, %1 %3 = lshr i128 %0, %1
ret i128 %3 ret i128 %3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_const_i8(i8 signext %0) { define signext i8 @shl_const_i8(i8 signext %0) {
; CHECK-LABEL: shl_const_i8: ; CHECK-LABEL: shl_const_i8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32 %2 = zext i8 %0 to i32
%3 = ashr i32 -4, %2 %3 = ashr i32 -4, %2
%4 = trunc i32 %3 to i8 %4 = trunc i32 %3 to i8
ret i8 %4 ret i8 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_const_u8(i8 zeroext %0) { define zeroext i8 @shl_const_u8(i8 zeroext %0) {
; CHECK-LABEL: shl_const_u8: ; CHECK-LABEL: shl_const_u8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32 %2 = zext i8 %0 to i32
%3 = ashr i32 -4, %2 %3 = ashr i32 -4, %2
%4 = trunc i32 %3 to i8 %4 = trunc i32 %3 to i8
ret i8 %4 ret i8 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_const_i16(i16 signext %0) { define signext i16 @shl_const_i16(i16 signext %0) {
; CHECK-LABEL: shl_const_i16: ; CHECK-LABEL: shl_const_i16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32 %2 = zext i16 %0 to i32
%3 = ashr i32 -4, %2 %3 = ashr i32 -4, %2
%4 = trunc i32 %3 to i16 %4 = trunc i32 %3 to i16
ret i16 %4 ret i16 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_const_u16(i16 zeroext %0) { define zeroext i16 @shl_const_u16(i16 zeroext %0) {
; CHECK-LABEL: shl_const_u16: ; CHECK-LABEL: shl_const_u16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32 %2 = zext i16 %0 to i32
%3 = ashr i32 -4, %2 %3 = ashr i32 -4, %2
%4 = trunc i32 %3 to i16 %4 = trunc i32 %3 to i16
ret i16 %4 ret i16 %4
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_const_i32(i32 signext %0) { define signext i32 @shl_const_i32(i32 signext %0) {
; CHECK-LABEL: shl_const_i32: ; CHECK-LABEL: shl_const_i32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i32 -4, %0 %2 = ashr i32 -4, %0
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_const_u32(i32 zeroext %0) { define zeroext i32 @shl_const_u32(i32 zeroext %0) {
; CHECK-LABEL: shl_const_u32: ; CHECK-LABEL: shl_const_u32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0 ; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i32 -4, %0 %2 = ashr i32 -4, %0
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_const_i64(i64 %0) { define i64 @shl_const_i64(i64 %0) {
; CHECK-LABEL: shl_const_i64: ; CHECK-LABEL: shl_const_i64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, (62)1, %s0 ; CHECK-NEXT: sra.l %s0, (62)1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i64 -4, %0 %2 = ashr i64 -4, %0
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_const_u64(i64 %0) { define i64 @shl_const_u64(i64 %0) {
; CHECK-LABEL: shl_const_u64: ; CHECK-LABEL: shl_const_u64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, (62)1, %s0 ; CHECK-NEXT: sra.l %s0, (62)1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i64 -4, %0 %2 = ashr i64 -4, %0
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @shl_const_i128(i128 %0) { define i128 @shl_const_i128(i128 %0) {
; CHECK-LABEL: shl_const_i128: ; CHECK-LABEL: shl_const_i128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: .LBB{{[0-9]+}}_2:
Show All 23 Lines
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: or %s11, 0, %s9
%2 = ashr i128 -4, %0 %2 = ashr i128 -4, %0
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_i8_const(i8 signext %0) { define signext i8 @shl_i8_const(i8 signext %0) {
; CHECK-LABEL: shl_i8_const: ; CHECK-LABEL: shl_i8_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 3 ; CHECK-NEXT: sra.w.sx %s0, %s0, 3
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i8 %0, 3 %2 = ashr i8 %0, 3
ret i8 %2 ret i8 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_u8_const(i8 zeroext %0) { define zeroext i8 @shl_u8_const(i8 zeroext %0) {
; CHECK-LABEL: shl_u8_const: ; CHECK-LABEL: shl_u8_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 3 ; CHECK-NEXT: srl %s0, %s0, 3
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i8 %0, 3 %2 = lshr i8 %0, 3
ret i8 %2 ret i8 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_i16_const(i16 signext %0) { define signext i16 @shl_i16_const(i16 signext %0) {
; CHECK-LABEL: shl_i16_const: ; CHECK-LABEL: shl_i16_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 7 ; CHECK-NEXT: sra.w.sx %s0, %s0, 7
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i16 %0, 7 %2 = ashr i16 %0, 7
ret i16 %2 ret i16 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_u16_const(i16 zeroext %0) { define zeroext i16 @shl_u16_const(i16 zeroext %0) {
; CHECK-LABEL: shl_u16_const: ; CHECK-LABEL: shl_u16_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 7 ; CHECK-NEXT: srl %s0, %s0, 7
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i16 %0, 7 %2 = lshr i16 %0, 7
ret i16 %2 ret i16 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_i32_const(i32 signext %0) { define signext i32 @shl_i32_const(i32 signext %0) {
; CHECK-LABEL: shl_i32_const: ; CHECK-LABEL: shl_i32_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 15 ; CHECK-NEXT: sra.w.sx %s0, %s0, 15
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i32 %0, 15 %2 = ashr i32 %0, 15
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_u32_const(i32 zeroext %0) { define zeroext i32 @shl_u32_const(i32 zeroext %0) {
; CHECK-LABEL: shl_u32_const: ; CHECK-LABEL: shl_u32_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 15 ; CHECK-NEXT: srl %s0, %s0, 15
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i32 %0, 15 %2 = lshr i32 %0, 15
ret i32 %2 ret i32 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_i64_const(i64 %0) { define i64 @shl_i64_const(i64 %0) {
; CHECK-LABEL: shl_i64_const: ; CHECK-LABEL: shl_i64_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 63 ; CHECK-NEXT: sra.l %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i64 %0, 63 %2 = ashr i64 %0, 63
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @shl_u64_const(i64 %0) { define i64 @shl_u64_const(i64 %0) {
; CHECK-LABEL: shl_u64_const: ; CHECK-LABEL: shl_u64_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s0, 63 ; CHECK-NEXT: srl %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i64 %0, 63 %2 = lshr i64 %0, 63
ret i64 %2 ret i64 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @shl_i128_const(i128 %0) { define i128 @shl_i128_const(i128 %0) {
; CHECK-LABEL: shl_i128_const: ; CHECK-LABEL: shl_i128_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s1, 63 ; CHECK-NEXT: sra.l %s0, %s1, 63
; CHECK-NEXT: or %s1, 0, %s0 ; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i128 %0, 127 %2 = ashr i128 %0, 127
ret i128 %2 ret i128 %2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i128 @shl_u128_const(i128 %0) { define i128 @shl_u128_const(i128 %0) {
; CHECK-LABEL: shl_u128_const: ; CHECK-LABEL: shl_u128_const:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s1, 63 ; CHECK-NEXT: srl %s0, %s1, 63
; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i128 %0, 127 %2 = lshr i128 %0, 127
ret i128 %2 ret i128 %2
} }

llvm/test/CodeGen/VE/Scalar/simple_prologue_epilogue.ll

  • This file was deleted.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define void @func() {
; CHECK-LABEL: func:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s13, -176
; CHECK-NEXT: and %s13, %s13, (32)0
; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
ret void
}
define i64 @func1(i64) {
; CHECK-LABEL: func1:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s13, -176
; CHECK-NEXT: and %s13, %s13, (32)0
; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
ret i64 %0
}
define i64 @func2(i64, i64, i64, i64, i64) {
; CHECK-LABEL: func2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s13, -176
; CHECK-NEXT: and %s13, %s13, (32)0
; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
ret i64 %4
}

llvm/test/CodeGen/VE/Scalar/store-align1.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: or %s11, 0, %s9
%addr = alloca i8, align 1 %addr = alloca i8, align 1
store i8 %0, i8* %addr, align 1 store i8 %0, i8* %addr, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) { define void @storef64com(double %0) {
; CHECK-LABEL: storef64com: ; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 1 store double %0, double* @vf64, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) { define void @storef32com(float %0) {
; CHECK-LABEL: storef32com: ; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1) ; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 1 store float %0, float* @vf32, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) { define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com: ; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 1 store i64 %0, i64* @vi64, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) { define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com: ; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1) ; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 1 store i32 %0, i32* @vi32, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) { define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com: ; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1) ; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 1 store i16 %0, i16* @vi16, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) { define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com: ; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1) ; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 1 store i8 %0, i8* @vi8, align 1
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/store-align2.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: or %s11, 0, %s9
%addr = alloca i8, align 2 %addr = alloca i8, align 2
store i8 %0, i8* %addr, align 2 store i8 %0, i8* %addr, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) { define void @storef64com(double %0) {
; CHECK-LABEL: storef64com: ; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 2 store double %0, double* @vf64, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) { define void @storef32com(float %0) {
; CHECK-LABEL: storef32com: ; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1) ; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 2 store float %0, float* @vf32, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) { define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com: ; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 2 store i64 %0, i64* @vi64, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) { define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com: ; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1) ; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 2 store i32 %0, i32* @vi32, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) { define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com: ; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1) ; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 2 store i16 %0, i16* @vi16, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) { define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com: ; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1) ; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 2 store i8 %0, i8* @vi8, align 2
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/store-align4.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: or %s11, 0, %s9
%addr = alloca i8, align 4 %addr = alloca i8, align 4
store i8 %0, i8* %addr, align 4 store i8 %0, i8* %addr, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) { define void @storef64com(double %0) {
; CHECK-LABEL: storef64com: ; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 4 store double %0, double* @vf64, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) { define void @storef32com(float %0) {
; CHECK-LABEL: storef32com: ; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1) ; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 4 store float %0, float* @vf32, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) { define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com: ; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 4 store i64 %0, i64* @vi64, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) { define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com: ; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1) ; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 4 store i32 %0, i32* @vi32, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) { define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com: ; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1) ; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 4 store i16 %0, i16* @vi16, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) { define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com: ; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1) ; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 4 store i8 %0, i8* @vi8, align 4
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/store-align8.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: or %s11, 0, %s9
%addr = alloca i8, align 8 %addr = alloca i8, align 8
store i8 %0, i8* %addr, align 8 store i8 %0, i8* %addr, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) { define void @storef64com(double %0) {
; CHECK-LABEL: storef64com: ; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 8 store double %0, double* @vf64, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) { define void @storef32com(float %0) {
; CHECK-LABEL: storef32com: ; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1) ; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 8 store float %0, float* @vf32, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) { define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com: ; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 8 store i64 %0, i64* @vi64, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) { define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com: ; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1) ; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 8 store i32 %0, i32* @vi32, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) { define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com: ; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1) ; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 8 store i16 %0, i16* @vi16, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) { define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com: ; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1) ; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 8 store i8 %0, i8* @vi8, align 8
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/store.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef128(fp128* nocapture %0, fp128 %1) { define void @storef128(fp128* nocapture %0, fp128 %1) {
; CHECK-LABEL: storef128: ; CHECK-LABEL: storef128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s2, 8(, %s0) ; CHECK-NEXT: st %s2, 8(, %s0)
; CHECK-NEXT: st %s3, (, %s0) ; CHECK-NEXT: st %s3, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store fp128 %1, fp128* %0, align 16 store fp128 %1, fp128* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef64(double* nocapture %0, double %1) { define void @storef64(double* nocapture %0, double %1) {
; CHECK-LABEL: storef64: ; CHECK-LABEL: storef64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store double %1, double* %0, align 16 store double %1, double* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef32(float* nocapture %0, float %1) { define void @storef32(float* nocapture %0, float %1) {
; CHECK-LABEL: storef32: ; CHECK-LABEL: storef32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: stu %s1, (, %s0) ; CHECK-NEXT: stu %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store float %1, float* %0, align 16 store float %1, float* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei128(i128* nocapture %0, i128 %1) { define void @storei128(i128* nocapture %0, i128 %1) {
; CHECK-LABEL: storei128: ; CHECK-LABEL: storei128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s2, 8(, %s0) ; CHECK-NEXT: st %s2, 8(, %s0)
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i128 %1, i128* %0, align 16 store i128 %1, i128* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei64(i64* nocapture %0, i64 %1) { define void @storei64(i64* nocapture %0, i64 %1) {
; CHECK-LABEL: storei64: ; CHECK-LABEL: storei64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s1, (, %s0) ; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i64 %1, i64* %0, align 16 store i64 %1, i64* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei32(i32* nocapture %0, i32 %1) { define void @storei32(i32* nocapture %0, i32 %1) {
; CHECK-LABEL: storei32: ; CHECK-LABEL: storei32:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i32 %1, i32* %0, align 16 store i32 %1, i32* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei32tr(i32* nocapture %0, i64 %1) { define void @storei32tr(i32* nocapture %0, i64 %1) {
; CHECK-LABEL: storei32tr: ; CHECK-LABEL: storei32tr:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0) ; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = trunc i64 %1 to i32 %3 = trunc i64 %1 to i32
store i32 %3, i32* %0, align 16 store i32 %3, i32* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei16(i16* nocapture %0, i16 %1) { define void @storei16(i16* nocapture %0, i16 %1) {
; CHECK-LABEL: storei16: ; CHECK-LABEL: storei16:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i16 %1, i16* %0, align 16 store i16 %1, i16* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei16tr(i16* nocapture %0, i64 %1) { define void @storei16tr(i16* nocapture %0, i64 %1) {
; CHECK-LABEL: storei16tr: ; CHECK-LABEL: storei16tr:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s1, (, %s0) ; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = trunc i64 %1 to i16 %3 = trunc i64 %1 to i16
store i16 %3, i16* %0, align 16 store i16 %3, i16* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei8(i8* nocapture %0, i8 %1) { define void @storei8(i8* nocapture %0, i8 %1) {
; CHECK-LABEL: storei8: ; CHECK-LABEL: storei8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i8 %1, i8* %0, align 16 store i8 %1, i8* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei8tr(i8* nocapture %0, i64 %1) { define void @storei8tr(i8* nocapture %0, i64 %1) {
; CHECK-LABEL: storei8tr: ; CHECK-LABEL: storei8tr:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0) ; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = trunc i64 %1 to i8 %3 = trunc i64 %1 to i8
store i8 %3, i8* %0, align 16 store i8 %3, i8* %0, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef128stk(fp128 %0) { define void @storef128stk(fp128 %0) {
; CHECK-LABEL: storef128stk: ; CHECK-LABEL: storef128stk:
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/Scalar/store_gv.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
@vi8 = common dso_local local_unnamed_addr global i8 0, align 1 @vi8 = common dso_local local_unnamed_addr global i8 0, align 1
@vi16 = common dso_local local_unnamed_addr global i16 0, align 2 @vi16 = common dso_local local_unnamed_addr global i16 0, align 2
@vi32 = common dso_local local_unnamed_addr global i32 0, align 4 @vi32 = common dso_local local_unnamed_addr global i32 0, align 4
@vi64 = common dso_local local_unnamed_addr global i64 0, align 8 @vi64 = common dso_local local_unnamed_addr global i64 0, align 8
@vi128 = common dso_local local_unnamed_addr global i128 0, align 16 @vi128 = common dso_local local_unnamed_addr global i128 0, align 16
@vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 4 @vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 4
@vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 8 @vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 8
@vf128 = common dso_local local_unnamed_addr global fp128 0xL00000000000000000000000000000000, align 16 @vf128 = common dso_local local_unnamed_addr global fp128 0xL00000000000000000000000000000000, align 16
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef128com(fp128 %0) { define void @storef128com(fp128 %0) {
; CHECK-LABEL: storef128com: ; CHECK-LABEL: storef128com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, vf128@lo ; CHECK-NEXT: lea %s2, vf128@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, vf128@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, vf128@hi(, %s2)
; CHECK-NEXT: st %s0, 8(, %s2) ; CHECK-NEXT: st %s0, 8(, %s2)
; CHECK-NEXT: st %s1, (, %s2) ; CHECK-NEXT: st %s1, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store fp128 %0, fp128* @vf128, align 16 store fp128 %0, fp128* @vf128, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) { define void @storef64com(double %0) {
; CHECK-LABEL: storef64com: ; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo ; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 8 store double %0, double* @vf64, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) { define void @storef32com(float %0) {
; CHECK-LABEL: storef32com: ; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo ; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1) ; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 4 store float %0, float* @vf32, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei128com(i128 %0) { define void @storei128com(i128 %0) {
; CHECK-LABEL: storei128com: ; CHECK-LABEL: storei128com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, vi128@lo ; CHECK-NEXT: lea %s2, vi128@lo
; CHECK-NEXT: and %s2, %s2, (32)0 ; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, vi128@hi(, %s2) ; CHECK-NEXT: lea.sl %s2, vi128@hi(, %s2)
; CHECK-NEXT: st %s1, 8(, %s2) ; CHECK-NEXT: st %s1, 8(, %s2)
; CHECK-NEXT: st %s0, (, %s2) ; CHECK-NEXT: st %s0, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i128 %0, i128* @vi128, align 16 store i128 %0, i128* @vi128, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) { define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com: ; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo ; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 8 store i64 %0, i64* @vi64, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) { define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com: ; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo ; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1) ; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 4 store i32 %0, i32* @vi32, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) { define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com: ; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo ; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1) ; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 2 store i16 %0, i16* @vi16, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) { define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com: ; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo ; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1) ; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1) ; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 1 store i8 %0, i8* @vi8, align 1
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/subtraction.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func8s(i8 signext %0, i8 signext %1) { define signext i8 @func8s(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i8 %0, %1 %3 = sub i8 %0, %1
ret i8 %3 ret i8 %3
} }
define signext i16 @func16s(i16 signext %0, i16 signext %1) { define signext i16 @func16s(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i16 %0, %1 %3 = sub i16 %0, %1
ret i16 %3 ret i16 %3
} }
define signext i32 @func32s(i32 signext %0, i32 signext %1) { define signext i32 @func32s(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub nsw i32 %0, %1 %3 = sub nsw i32 %0, %1
ret i32 %3 ret i32 %3
} }
define i64 @func64s(i64 %0, i64 %1) { define i64 @func64s(i64 %0, i64 %1) {
; CHECK-LABEL: func64s: ; CHECK-LABEL: func64s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub nsw i64 %0, %1 %3 = sub nsw i64 %0, %1
ret i64 %3 ret i64 %3
} }
define i128 @func128s(i128 %0, i128 %1) { define i128 @func128s(i128 %0, i128 %1) {
; CHECK-LABEL: func128s: ; CHECK-LABEL: func128s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.l %s1, %s1, %s3 ; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: cmpu.l %s3, %s0, %s2 ; CHECK-NEXT: cmpu.l %s3, %s0, %s2
; CHECK-NEXT: or %s4, 0, (0)1 ; CHECK-NEXT: or %s4, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s4, (63)0, %s3 ; CHECK-NEXT: cmov.l.lt %s4, (63)0, %s3
; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1 ; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1
; CHECK-NEXT: subs.l %s1, %s1, %s3 ; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: subs.l %s0, %s0, %s2 ; CHECK-NEXT: subs.l %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub nsw i128 %0, %1 %3 = sub nsw i128 %0, %1
ret i128 %3 ret i128 %3
} }
define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) { define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i8 %0, %1 %3 = sub i8 %0, %1
ret i8 %3 ret i8 %3
} }
define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) { define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i16 %0, %1 %3 = sub i16 %0, %1
ret i16 %3 ret i16 %3
} }
define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) { define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i32 %0, %1 %3 = sub i32 %0, %1
ret i32 %3 ret i32 %3
} }
define i64 @func64z(i64 %0, i64 %1) { define i64 @func64z(i64 %0, i64 %1) {
; CHECK-LABEL: func64z: ; CHECK-LABEL: func64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.l %s0, %s0, %s1 ; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i64 %0, %1 %3 = sub i64 %0, %1
ret i64 %3 ret i64 %3
} }
define i128 @func128z(i128 %0, i128 %1) { define i128 @func128z(i128 %0, i128 %1) {
; CHECK-LABEL: func128z: ; CHECK-LABEL: func128z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: subs.l %s1, %s1, %s3 ; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: cmpu.l %s3, %s0, %s2 ; CHECK-NEXT: cmpu.l %s3, %s0, %s2
; CHECK-NEXT: or %s4, 0, (0)1 ; CHECK-NEXT: or %s4, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s4, (63)0, %s3 ; CHECK-NEXT: cmov.l.lt %s4, (63)0, %s3
; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1 ; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1
; CHECK-NEXT: subs.l %s1, %s1, %s3 ; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: subs.l %s0, %s0, %s2 ; CHECK-NEXT: subs.l %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i128 %0, %1 %3 = sub i128 %0, %1
ret i128 %3 ret i128 %3
} }
define signext i8 @funci8s(i8 signext %a) { define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s: ; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: sll %s0, %s0, 56 ; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56 ; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%ret = add i8 %a, -5 %ret = add i8 %a, -5
ret i8 %ret ret i8 %ret
} }
define signext i16 @funci16s(i16 signext %a) { define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: sll %s0, %s0, 48 ; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48 ; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%ret = add i16 %a, -5 %ret = add i16 %a, -5
ret i16 %ret ret i16 %ret
} }
define signext i32 @funci32s(i32 signext %a) { define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%ret = add i32 %a, -5 %ret = add i32 %a, -5
ret i32 %ret ret i32 %ret
} }
define i64 @funci64s(i64 %a) { define i64 @funci64s(i64 %a) {
; CHECK-LABEL: funci64s: ; CHECK-LABEL: funci64s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -5(, %s0) ; CHECK-NEXT: lea %s0, -5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%ret = add nsw i64 %a, -5 %ret = add nsw i64 %a, -5
ret i64 %ret ret i64 %ret
} }
define i128 @funci128s(i128 %0) { define i128 @funci128s(i128 %0) {
; CHECK-LABEL: funci128s: ; CHECK-LABEL: funci128s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, -5(, %s0) ; CHECK-NEXT: lea %s2, -5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: lea %s1, -1(%s0, %s1) ; CHECK-NEXT: lea %s1, -1(%s0, %s1)
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i128 %0, -5 %2 = add nsw i128 %0, -5
ret i128 %2 ret i128 %2
} }
define zeroext i8 @funci8z(i8 zeroext %a) { define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z: ; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0 ; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%ret = add i8 %a, -5 %ret = add i8 %a, -5
ret i8 %ret ret i8 %ret
} }
define zeroext i16 @funci16z(i16 zeroext %a) { define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0 ; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%ret = add i16 %a, -5 %ret = add i16 %a, -5
ret i16 %ret ret i16 %ret
} }
define zeroext i32 @funci32z(i32 zeroext %a) { define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0 ; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%ret = add i32 %a, -5 %ret = add i32 %a, -5
ret i32 %ret ret i32 %ret
} }
define i64 @funci64z(i64 %a) { define i64 @funci64z(i64 %a) {
; CHECK-LABEL: funci64z: ; CHECK-LABEL: funci64z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -5(, %s0) ; CHECK-NEXT: lea %s0, -5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%ret = add i64 %a, -5 %ret = add i64 %a, -5
ret i64 %ret ret i64 %ret
} }
define i128 @funci128z(i128 %0) { define i128 @funci128z(i128 %0) {
; CHECK-LABEL: funci128z: ; CHECK-LABEL: funci128z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, -5(, %s0) ; CHECK-NEXT: lea %s2, -5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: lea %s1, -1(%s0, %s1) ; CHECK-NEXT: lea %s1, -1(%s0, %s1)
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add i128 %0, -5 %2 = add i128 %0, -5
ret i128 %2 ret i128 %2
} }
define i64 @funci64_2(i64 %a) { define i64 @funci64_2(i64 %a) {
; CHECK-LABEL: funci64_2: ; CHECK-LABEL: funci64_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648(, %s0) ; CHECK-NEXT: lea %s0, -2147483648(, %s0)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%ret = add nsw i64 %a, -2147483648 %ret = add nsw i64 %a, -2147483648
ret i64 %ret ret i64 %ret
} }
define i128 @funci128_2(i128 %0) { define i128 @funci128_2(i128 %0) {
; CHECK-LABEL: funci128_2: ; CHECK-LABEL: funci128_2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, -2147483648(, %s0) ; CHECK-NEXT: lea %s2, -2147483648(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0 ; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1 ; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 ; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: lea %s1, -1(%s0, %s1) ; CHECK-NEXT: lea %s1, -1(%s0, %s1)
; CHECK-NEXT: or %s0, 0, %s2 ; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i128 %0, -2147483648 %2 = add nsw i128 %0, -2147483648
ret i128 %2 ret i128 %2
} }

llvm/test/CodeGen/VE/Scalar/symbol_relocation_tls.ll

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; GENDYN-NEXT: R_VE_TLS_GD_HI32 x ; GENDYN-NEXT: R_VE_TLS_GD_HI32 x
; GENDYN-NEXT: lea %s12, (8) ; GENDYN-NEXT: lea %s12, (8)
; GENDYN-NEXT: R_VE_PLT_LO32 __tls_get_addr ; GENDYN-NEXT: R_VE_PLT_LO32 __tls_get_addr
; GENDYN-NEXT: and %s12, %s12, (32)0 ; GENDYN-NEXT: and %s12, %s12, (32)0
; GENDYN-NEXT: lea.sl %s12, (%s10, %s12) ; GENDYN-NEXT: lea.sl %s12, (%s10, %s12)
; GENDYN-NEXT: R_VE_PLT_HI32 __tls_get_addr ; GENDYN-NEXT: R_VE_PLT_HI32 __tls_get_addr
; GENDYN-NEXT: bsic %s10, (, %s12) ; GENDYN-NEXT: bsic %s10, (, %s12)
; GENDYN-NEXT: stl %s18, (, %s0) ; GENDYN-NEXT: stl %s18, (, %s0)
; GENDYN-NEXT: ld %s18, 48(, %s9) ; GENDYN-NEXT: ld %s18, 288(, %s11)
; GENDYN-NEXT: or %s11, 0, %s9 ; GENDYN-NEXT: or %s11, 0, %s9
; ;
; GENDYNPIC: lea %s15, (-24) ; GENDYNPIC: lea %s15, (-24)
; GENDYNPIC-NEXT: R_VE_PC_LO32 _GLOBAL_OFFSET_TABLE_ ; GENDYNPIC-NEXT: R_VE_PC_LO32 _GLOBAL_OFFSET_TABLE_
; GENDYNPIC-NEXT: and %s15, %s15, (32)0 ; GENDYNPIC-NEXT: and %s15, %s15, (32)0
; GENDYNPIC-NEXT: sic %s16 ; GENDYNPIC-NEXT: sic %s16
; GENDYNPIC-NEXT: lea.sl %s15, (%s16, %s15) ; GENDYNPIC-NEXT: lea.sl %s15, (%s16, %s15)
; GENDYNPIC-NEXT: R_VE_PC_HI32 _GLOBAL_OFFSET_TABLE_ ; GENDYNPIC-NEXT: R_VE_PC_HI32 _GLOBAL_OFFSET_TABLE_
; GENDYNPIC-NEXT: lea %s0, (-24) ; GENDYNPIC-NEXT: lea %s0, (-24)
; GENDYNPIC-NEXT: R_VE_TLS_GD_LO32 x ; GENDYNPIC-NEXT: R_VE_TLS_GD_LO32 x
; GENDYNPIC-NEXT: and %s0, %s0, (32)0 ; GENDYNPIC-NEXT: and %s0, %s0, (32)0
; GENDYNPIC-NEXT: sic %s10 ; GENDYNPIC-NEXT: sic %s10
; GENDYNPIC-NEXT: lea.sl %s0, (%s10, %s0) ; GENDYNPIC-NEXT: lea.sl %s0, (%s10, %s0)
; GENDYNPIC-NEXT: R_VE_TLS_GD_HI32 x ; GENDYNPIC-NEXT: R_VE_TLS_GD_HI32 x
; GENDYNPIC-NEXT: lea %s12, (8) ; GENDYNPIC-NEXT: lea %s12, (8)
; GENDYNPIC-NEXT: R_VE_PLT_LO32 __tls_get_addr ; GENDYNPIC-NEXT: R_VE_PLT_LO32 __tls_get_addr
; GENDYNPIC-NEXT: and %s12, %s12, (32)0 ; GENDYNPIC-NEXT: and %s12, %s12, (32)0
; GENDYNPIC-NEXT: lea.sl %s12, (%s10, %s12) ; GENDYNPIC-NEXT: lea.sl %s12, (%s10, %s12)
; GENDYNPIC-NEXT: R_VE_PLT_HI32 __tls_get_addr ; GENDYNPIC-NEXT: R_VE_PLT_HI32 __tls_get_addr
; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: stl %s18, (, %s0) ; GENDYNPIC-NEXT: stl %s18, (, %s0)
; GENDYNPIC-NEXT: ld %s18, 48(, %s9) ; GENDYNPIC-NEXT: ld %s18, 288(, %s11)
; GENDYNPIC-NEXT: or %s11, 0, %s9 ; GENDYNPIC-NEXT: or %s11, 0, %s9
entry: entry:
store i32 %v, i32* @x, align 4 store i32 %v, i32* @x, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @set_local(i32 %v) { define void @set_local(i32 %v) {
; GENDYN: lea %s0, (-24) ; GENDYN: lea %s0, (-24)
; GENDYN-NEXT: R_VE_TLS_GD_LO32 y ; GENDYN-NEXT: R_VE_TLS_GD_LO32 y
; GENDYN-NEXT: and %s0, %s0, (32)0 ; GENDYN-NEXT: and %s0, %s0, (32)0
; GENDYN-NEXT: sic %s10 ; GENDYN-NEXT: sic %s10
; GENDYN-NEXT: lea.sl %s0, (%s10, %s0) ; GENDYN-NEXT: lea.sl %s0, (%s10, %s0)
; GENDYN-NEXT: R_VE_TLS_GD_HI32 y ; GENDYN-NEXT: R_VE_TLS_GD_HI32 y
; GENDYN-NEXT: lea %s12, (8) ; GENDYN-NEXT: lea %s12, (8)
; GENDYN-NEXT: R_VE_PLT_LO32 __tls_get_addr ; GENDYN-NEXT: R_VE_PLT_LO32 __tls_get_addr
; GENDYN-NEXT: and %s12, %s12, (32)0 ; GENDYN-NEXT: and %s12, %s12, (32)0
; GENDYN-NEXT: lea.sl %s12, (%s10, %s12) ; GENDYN-NEXT: lea.sl %s12, (%s10, %s12)
; GENDYN-NEXT: R_VE_PLT_HI32 __tls_get_addr ; GENDYN-NEXT: R_VE_PLT_HI32 __tls_get_addr
; GENDYN-NEXT: bsic %s10, (, %s12) ; GENDYN-NEXT: bsic %s10, (, %s12)
; GENDYN-NEXT: stl %s18, (, %s0) ; GENDYN-NEXT: stl %s18, (, %s0)
; GENDYN-NEXT: ld %s18, 48(, %s9) ; GENDYN-NEXT: ld %s18, 288(, %s11)
; GENDYN-NEXT: or %s11, 0, %s9 ; GENDYN-NEXT: or %s11, 0, %s9
; ;
; GENDYNPIC: lea %s15, (-24) ; GENDYNPIC: lea %s15, (-24)
; GENDYNPIC-NEXT: R_VE_PC_LO32 _GLOBAL_OFFSET_TABLE_ ; GENDYNPIC-NEXT: R_VE_PC_LO32 _GLOBAL_OFFSET_TABLE_
; GENDYNPIC-NEXT: and %s15, %s15, (32)0 ; GENDYNPIC-NEXT: and %s15, %s15, (32)0
; GENDYNPIC-NEXT: sic %s16 ; GENDYNPIC-NEXT: sic %s16
; GENDYNPIC-NEXT: lea.sl %s15, (%s16, %s15) ; GENDYNPIC-NEXT: lea.sl %s15, (%s16, %s15)
; GENDYNPIC-NEXT: R_VE_PC_HI32 _GLOBAL_OFFSET_TABLE_ ; GENDYNPIC-NEXT: R_VE_PC_HI32 _GLOBAL_OFFSET_TABLE_
; GENDYNPIC-NEXT: lea %s0, (-24) ; GENDYNPIC-NEXT: lea %s0, (-24)
; GENDYNPIC-NEXT: R_VE_TLS_GD_LO32 y ; GENDYNPIC-NEXT: R_VE_TLS_GD_LO32 y
; GENDYNPIC-NEXT: and %s0, %s0, (32)0 ; GENDYNPIC-NEXT: and %s0, %s0, (32)0
; GENDYNPIC-NEXT: sic %s10 ; GENDYNPIC-NEXT: sic %s10
; GENDYNPIC-NEXT: lea.sl %s0, (%s10, %s0) ; GENDYNPIC-NEXT: lea.sl %s0, (%s10, %s0)
; GENDYNPIC-NEXT: R_VE_TLS_GD_HI32 y ; GENDYNPIC-NEXT: R_VE_TLS_GD_HI32 y
; GENDYNPIC-NEXT: lea %s12, (8) ; GENDYNPIC-NEXT: lea %s12, (8)
; GENDYNPIC-NEXT: R_VE_PLT_LO32 __tls_get_addr ; GENDYNPIC-NEXT: R_VE_PLT_LO32 __tls_get_addr
; GENDYNPIC-NEXT: and %s12, %s12, (32)0 ; GENDYNPIC-NEXT: and %s12, %s12, (32)0
; GENDYNPIC-NEXT: lea.sl %s12, (%s10, %s12) ; GENDYNPIC-NEXT: lea.sl %s12, (%s10, %s12)
; GENDYNPIC-NEXT: R_VE_PLT_HI32 __tls_get_addr ; GENDYNPIC-NEXT: R_VE_PLT_HI32 __tls_get_addr
; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: stl %s18, (, %s0) ; GENDYNPIC-NEXT: stl %s18, (, %s0)
; GENDYNPIC-NEXT: ld %s18, 48(, %s9) ; GENDYNPIC-NEXT: ld %s18, 288(, %s11)
; GENDYNPIC-NEXT: or %s11, 0, %s9 ; GENDYNPIC-NEXT: or %s11, 0, %s9
entry: entry:
store i32 %v, i32* @y, align 4 store i32 %v, i32* @y, align 4
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/tls.ll

Show All 31 Lines
; GENDYNPIC-NEXT: and %s0, %s0, (32)0 ; GENDYNPIC-NEXT: and %s0, %s0, (32)0
; GENDYNPIC-NEXT: sic %s10 ; GENDYNPIC-NEXT: sic %s10
; GENDYNPIC-NEXT: lea.sl %s0, x@tls_gd_hi(%s10, %s0) ; GENDYNPIC-NEXT: lea.sl %s0, x@tls_gd_hi(%s10, %s0)
; GENDYNPIC-NEXT: lea %s12, __tls_get_addr@plt_lo(8) ; GENDYNPIC-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
; GENDYNPIC-NEXT: and %s12, %s12, (32)0 ; GENDYNPIC-NEXT: and %s12, %s12, (32)0
; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: or %s11, 0, %s9 ; GENDYNPIC-NEXT: or %s11, 0, %s9
;
; LOCAL-LABEL: get_global: ; LOCAL-LABEL: get_global:
; LOCAL: .LBB{{[0-9]+}}_2: ; LOCAL: .LBB{{[0-9]+}}_2:
; LOCAL-NEXT: lea %s34, x@tpoff_lo ; LOCAL-NEXT: lea %s34, x@tpoff_lo
; LOCAL-NEXT: and %s34, %s34, (32)0 ; LOCAL-NEXT: and %s34, %s34, (32)0
; LOCAL-NEXT: lea.sl %s34, x@tpoff_hi(%s34) ; LOCAL-NEXT: lea.sl %s34, x@tpoff_hi(%s34)
; LOCAL-NEXT: adds.l %s0, %s14, %s34 ; LOCAL-NEXT: adds.l %s0, %s14, %s34
; LOCAL-NEXT: or %s11, 0, %s9 ; LOCAL-NEXT: or %s11, 0, %s9
entry: entry:
Show All 24 Lines
; GENDYNPIC-NEXT: and %s0, %s0, (32)0 ; GENDYNPIC-NEXT: and %s0, %s0, (32)0
; GENDYNPIC-NEXT: sic %s10 ; GENDYNPIC-NEXT: sic %s10
; GENDYNPIC-NEXT: lea.sl %s0, y@tls_gd_hi(%s10, %s0) ; GENDYNPIC-NEXT: lea.sl %s0, y@tls_gd_hi(%s10, %s0)
; GENDYNPIC-NEXT: lea %s12, __tls_get_addr@plt_lo(8) ; GENDYNPIC-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
; GENDYNPIC-NEXT: and %s12, %s12, (32)0 ; GENDYNPIC-NEXT: and %s12, %s12, (32)0
; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: or %s11, 0, %s9 ; GENDYNPIC-NEXT: or %s11, 0, %s9
;
; LOCAL-LABEL: get_local: ; LOCAL-LABEL: get_local:
; LOCAL: .LBB{{[0-9]+}}_2: ; LOCAL: .LBB{{[0-9]+}}_2:
; LOCAL-NEXT: lea %s34, y@tpoff_lo ; LOCAL-NEXT: lea %s34, y@tpoff_lo
; LOCAL-NEXT: and %s34, %s34, (32)0 ; LOCAL-NEXT: and %s34, %s34, (32)0
; LOCAL-NEXT: lea.sl %s34, y@tpoff_hi(%s34) ; LOCAL-NEXT: lea.sl %s34, y@tpoff_hi(%s34)
; LOCAL-NEXT: adds.l %s0, %s14, %s34 ; LOCAL-NEXT: adds.l %s0, %s14, %s34
; LOCAL-NEXT: or %s11, 0, %s9 ; LOCAL-NEXT: or %s11, 0, %s9
entry: entry:
ret i32* @y ret i32* @y
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @set_global(i32 %v) { define void @set_global(i32 %v) {
; GENDYN-LABEL: set_global: ; GENDYN-LABEL: set_global:
; GENDYN: .LBB{{[0-9]+}}_2: ; GENDYN: .LBB{{[0-9]+}}_2:
; GENDYN-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; GENDYN-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; GENDYN-NEXT: or %s18, 0, %s0 ; GENDYN-NEXT: or %s18, 0, %s0
; GENDYN-NEXT: lea %s0, x@tls_gd_lo(-24) ; GENDYN-NEXT: lea %s0, x@tls_gd_lo(-24)
; GENDYN-NEXT: and %s0, %s0, (32)0 ; GENDYN-NEXT: and %s0, %s0, (32)0
; GENDYN-NEXT: sic %s10 ; GENDYN-NEXT: sic %s10
; GENDYN-NEXT: lea.sl %s0, x@tls_gd_hi(%s10, %s0) ; GENDYN-NEXT: lea.sl %s0, x@tls_gd_hi(%s10, %s0)
; GENDYN-NEXT: lea %s12, __tls_get_addr@plt_lo(8) ; GENDYN-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
; GENDYN-NEXT: and %s12, %s12, (32)0 ; GENDYN-NEXT: and %s12, %s12, (32)0
; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYN-NEXT: bsic %s10, (, %s12) ; GENDYN-NEXT: bsic %s10, (, %s12)
; GENDYN-NEXT: stl %s18, (, %s0) ; GENDYN-NEXT: stl %s18, (, %s0)
; GENDYN-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; GENDYN-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; GENDYN-NEXT: or %s11, 0, %s9 ; GENDYN-NEXT: or %s11, 0, %s9
; ;
; GENDYNPIC-LABEL: set_global: ; GENDYNPIC-LABEL: set_global:
; GENDYNPIC: .LBB{{[0-9]+}}_2: ; GENDYNPIC: .LBB{{[0-9]+}}_2:
; GENDYNPIC-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; GENDYNPIC-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; GENDYNPIC-NEXT: or %s18, 0, %s0 ; GENDYNPIC-NEXT: or %s18, 0, %s0
; GENDYNPIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; GENDYNPIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; GENDYNPIC-NEXT: and %s15, %s15, (32)0 ; GENDYNPIC-NEXT: and %s15, %s15, (32)0
; GENDYNPIC-NEXT: sic %s16 ; GENDYNPIC-NEXT: sic %s16
; GENDYNPIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; GENDYNPIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; GENDYNPIC-NEXT: lea %s0, x@tls_gd_lo(-24) ; GENDYNPIC-NEXT: lea %s0, x@tls_gd_lo(-24)
; GENDYNPIC-NEXT: and %s0, %s0, (32)0 ; GENDYNPIC-NEXT: and %s0, %s0, (32)0
; GENDYNPIC-NEXT: sic %s10 ; GENDYNPIC-NEXT: sic %s10
; GENDYNPIC-NEXT: lea.sl %s0, x@tls_gd_hi(%s10, %s0) ; GENDYNPIC-NEXT: lea.sl %s0, x@tls_gd_hi(%s10, %s0)
; GENDYNPIC-NEXT: lea %s12, __tls_get_addr@plt_lo(8) ; GENDYNPIC-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
; GENDYNPIC-NEXT: and %s12, %s12, (32)0 ; GENDYNPIC-NEXT: and %s12, %s12, (32)0
; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: stl %s18, (, %s0) ; GENDYNPIC-NEXT: stl %s18, (, %s0)
; GENDYNPIC-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; GENDYNPIC-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; GENDYNPIC-NEXT: or %s11, 0, %s9 ; GENDYNPIC-NEXT: or %s11, 0, %s9
;
; LOCAL-LABEL: set_global: ; LOCAL-LABEL: set_global:
; LOCAL: .LBB{{[0-9]+}}_2: ; LOCAL: .LBB{{[0-9]+}}_2:
; LOCAL-NEXT: lea %s34, x@tpoff_lo ; LOCAL-NEXT: lea %s34, x@tpoff_lo
; LOCAL-NEXT: and %s34, %s34, (32)0 ; LOCAL-NEXT: and %s34, %s34, (32)0
; LOCAL-NEXT: lea.sl %s34, x@tpoff_hi(%s34) ; LOCAL-NEXT: lea.sl %s34, x@tpoff_hi(%s34)
; LOCAL-NEXT: adds.l %s34, %s14, %s34 ; LOCAL-NEXT: adds.l %s34, %s14, %s34
; LOCAL-NEXT: stl %s0, (, %s34) ; LOCAL-NEXT: stl %s0, (, %s34)
; LOCAL-NEXT: or %s11, 0, %s9 ; LOCAL-NEXT: or %s11, 0, %s9
entry: entry:
store i32 %v, i32* @x, align 4 store i32 %v, i32* @x, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @set_local(i32 %v) { define void @set_local(i32 %v) {
; GENDYN-LABEL: set_local: ; GENDYN-LABEL: set_local:
; GENDYN: .LBB{{[0-9]+}}_2: ; GENDYN: .LBB{{[0-9]+}}_2:
; GENDYN-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; GENDYN-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; GENDYN-NEXT: or %s18, 0, %s0 ; GENDYN-NEXT: or %s18, 0, %s0
; GENDYN-NEXT: lea %s0, y@tls_gd_lo(-24) ; GENDYN-NEXT: lea %s0, y@tls_gd_lo(-24)
; GENDYN-NEXT: and %s0, %s0, (32)0 ; GENDYN-NEXT: and %s0, %s0, (32)0
; GENDYN-NEXT: sic %s10 ; GENDYN-NEXT: sic %s10
; GENDYN-NEXT: lea.sl %s0, y@tls_gd_hi(%s10, %s0) ; GENDYN-NEXT: lea.sl %s0, y@tls_gd_hi(%s10, %s0)
; GENDYN-NEXT: lea %s12, __tls_get_addr@plt_lo(8) ; GENDYN-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
; GENDYN-NEXT: and %s12, %s12, (32)0 ; GENDYN-NEXT: and %s12, %s12, (32)0
; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYN-NEXT: bsic %s10, (, %s12) ; GENDYN-NEXT: bsic %s10, (, %s12)
; GENDYN-NEXT: stl %s18, (, %s0) ; GENDYN-NEXT: stl %s18, (, %s0)
; GENDYN-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; GENDYN-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; GENDYN-NEXT: or %s11, 0, %s9 ; GENDYN-NEXT: or %s11, 0, %s9
; ;
; GENDYNPIC-LABEL: set_local: ; GENDYNPIC-LABEL: set_local:
; GENDYNPIC: .LBB{{[0-9]+}}_2: ; GENDYNPIC: .LBB{{[0-9]+}}_2:
; GENDYNPIC-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; GENDYNPIC-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; GENDYNPIC-NEXT: or %s18, 0, %s0 ; GENDYNPIC-NEXT: or %s18, 0, %s0
; GENDYNPIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; GENDYNPIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; GENDYNPIC-NEXT: and %s15, %s15, (32)0 ; GENDYNPIC-NEXT: and %s15, %s15, (32)0
; GENDYNPIC-NEXT: sic %s16 ; GENDYNPIC-NEXT: sic %s16
; GENDYNPIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) ; GENDYNPIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; GENDYNPIC-NEXT: lea %s0, y@tls_gd_lo(-24) ; GENDYNPIC-NEXT: lea %s0, y@tls_gd_lo(-24)
; GENDYNPIC-NEXT: and %s0, %s0, (32)0 ; GENDYNPIC-NEXT: and %s0, %s0, (32)0
; GENDYNPIC-NEXT: sic %s10 ; GENDYNPIC-NEXT: sic %s10
; GENDYNPIC-NEXT: lea.sl %s0, y@tls_gd_hi(%s10, %s0) ; GENDYNPIC-NEXT: lea.sl %s0, y@tls_gd_hi(%s10, %s0)
; GENDYNPIC-NEXT: lea %s12, __tls_get_addr@plt_lo(8) ; GENDYNPIC-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
; GENDYNPIC-NEXT: and %s12, %s12, (32)0 ; GENDYNPIC-NEXT: and %s12, %s12, (32)0
; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12) ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYNPIC-NEXT: bsic %s10, (, %s12) ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: stl %s18, (, %s0) ; GENDYNPIC-NEXT: stl %s18, (, %s0)
; GENDYNPIC-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; GENDYNPIC-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; GENDYNPIC-NEXT: or %s11, 0, %s9 ; GENDYNPIC-NEXT: or %s11, 0, %s9
;
; LOCAL-LABEL: set_local: ; LOCAL-LABEL: set_local:
; LOCAL: .LBB{{[0-9]+}}_2: ; LOCAL: .LBB{{[0-9]+}}_2:
; LOCAL-NEXT: lea %s34, y@tpoff_lo ; LOCAL-NEXT: lea %s34, y@tpoff_lo
; LOCAL-NEXT: and %s34, %s34, (32)0 ; LOCAL-NEXT: and %s34, %s34, (32)0
; LOCAL-NEXT: lea.sl %s34, y@tpoff_hi(%s34) ; LOCAL-NEXT: lea.sl %s34, y@tpoff_hi(%s34)
; LOCAL-NEXT: adds.l %s34, %s14, %s34 ; LOCAL-NEXT: adds.l %s34, %s14, %s34
; LOCAL-NEXT: stl %s0, (, %s34) ; LOCAL-NEXT: stl %s0, (, %s34)
; LOCAL-NEXT: or %s11, 0, %s9 ; LOCAL-NEXT: or %s11, 0, %s9
entry: entry:
store i32 %v, i32* @y, align 4 store i32 %v, i32* @y, align 4
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/truncstore.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define void @func0(i1 signext %p, i8* %a) { define void @func0(i1 signext %p, i8* %a) {
; CHECK-LABEL: func0: ; CHECK-LABEL: func0:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s0, (, %s1) ; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i1 %p to i8 %p.conv = sext i1 %p to i8
store i8 %p.conv, i8* %a, align 2 store i8 %p.conv, i8* %a, align 2
ret void ret void
} }
define void @func1(i8 signext %p, i16* %a) { define void @func1(i8 signext %p, i16* %a) {
; CHECK-LABEL: func1: ; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s0, (, %s1) ; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i8 %p to i16 %p.conv = sext i8 %p to i16
store i16 %p.conv, i16* %a, align 2 store i16 %p.conv, i16* %a, align 2
ret void ret void
} }
define void @func2(i8 signext %p, i32* %a) { define void @func2(i8 signext %p, i32* %a) {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: stl %s0, (, %s1) ; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i8 %p to i32 %p.conv = sext i8 %p to i32
store i32 %p.conv, i32* %a, align 4 store i32 %p.conv, i32* %a, align 4
ret void ret void
} }
define void @func3(i8 signext %p, i64* %a) { define void @func3(i8 signext %p, i64* %a) {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i8 %p to i64 %p.conv = sext i8 %p to i64
store i64 %p.conv, i64* %a, align 8 store i64 %p.conv, i64* %a, align 8
ret void ret void
} }
define void @func5(i16 signext %p, i32* %a) { define void @func5(i16 signext %p, i32* %a) {
; CHECK-LABEL: func5: ; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: stl %s0, (, %s1) ; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i16 %p to i32 %p.conv = sext i16 %p to i32
store i32 %p.conv, i32* %a, align 4 store i32 %p.conv, i32* %a, align 4
ret void ret void
} }
define void @func6(i16 signext %p, i64* %a) { define void @func6(i16 signext %p, i64* %a) {
; CHECK-LABEL: func6: ; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i16 %p to i64 %p.conv = sext i16 %p to i64
store i64 %p.conv, i64* %a, align 8 store i64 %p.conv, i64* %a, align 8
ret void ret void
} }
define void @func8(i32 %p, i64* %a) { define void @func8(i32 %p, i64* %a) {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i32 %p to i64 %p.conv = sext i32 %p to i64
store i64 %p.conv, i64* %a, align 8 store i64 %p.conv, i64* %a, align 8
ret void ret void
} }

llvm/test/CodeGen/VE/Scalar/xor.ll

; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i8 @func8s(i8 signext %a, i8 signext %b) { define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s: ; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i8 %a, %b %res = xor i8 %a, %b
ret i8 %res ret i8 %res
} }
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) { define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z: ; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s1, %s0 ; CHECK-NEXT: xor %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i8 %b, %a %res = xor i8 %b, %a
ret i8 %res ret i8 %res
} }
define signext i8 @funci8s(i8 signext %a) { define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s: ; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, 5, %s0 ; CHECK-NEXT: xor %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i8 %a, 5 %res = xor i8 %a, 5
ret i8 %res ret i8 %res
} }
define zeroext i8 @funci8z(i8 zeroext %a) { define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z: ; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 251 ; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i8 -5, %a %res = xor i8 -5, %a
ret i8 %res ret i8 %res
} }
define signext i16 @func16s(i16 signext %a, i16 signext %b) { define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s: ; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i16 %a, %b %res = xor i16 %a, %b
ret i16 %res ret i16 %res
} }
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z: ; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s1, %s0 ; CHECK-NEXT: xor %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i16 %b, %a %res = xor i16 %b, %a
ret i16 %res ret i16 %res
} }
define signext i16 @funci16s(i16 signext %a) { define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s: ; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, -1, %s0 ; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i16 %a, 65535 %res = xor i16 %a, 65535
ret i16 %res ret i16 %res
} }
define zeroext i16 @funci16z(i16 zeroext %a) { define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z: ; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (52)0 ; CHECK-NEXT: xor %s0, %s0, (52)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i16 4095, %a %res = xor i16 4095, %a
ret i16 %res ret i16 %res
} }
define signext i32 @func32s(i32 signext %a, i32 signext %b) { define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s: ; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i32 %a, %b %res = xor i32 %a, %b
ret i32 %res ret i32 %res
} }
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) { define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z: ; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i32 %a, %b %res = xor i32 %a, %b
ret i32 %res ret i32 %res
} }
define signext i32 @funci32s(i32 signext %a) { define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s: ; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (36)0 ; CHECK-NEXT: xor %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i32 %a, 268435455 %res = xor i32 %a, 268435455
ret i32 %res ret i32 %res
} }
define zeroext i32 @funci32z(i32 zeroext %a) { define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z: ; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (36)0 ; CHECK-NEXT: xor %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i32 %a, 268435455 %res = xor i32 %a, 268435455
ret i32 %res ret i32 %res
} }
define i32 @funci32_another(i32 %0) { define i32 @funci32_another(i32 %0) {
; CHECK-LABEL: funci32_another: ; CHECK-LABEL: funci32_another:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = xor i32 %0, -2147483648 %2 = xor i32 %0, -2147483648
ret i32 %2 ret i32 %2
} }
define i64 @func64(i64 %a, i64 %b) { define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1 ; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i64 %a, %b %res = xor i64 %a, %b
ret i64 %res ret i64 %res
} }
define i64 @func64i(i64 %a) { define i64 @func64i(i64 %a) {
; CHECK-LABEL: func64i: ; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (24)0 ; CHECK-NEXT: xor %s0, %s0, (24)0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i64 %a, 1099511627775 %res = xor i64 %a, 1099511627775
ret i64 %res ret i64 %res
} }
define i128 @func128(i128 %a, i128 %b) { define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func128: ; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s2, %s0 ; CHECK-NEXT: xor %s0, %s2, %s0
; CHECK-NEXT: xor %s1, %s3, %s1 ; CHECK-NEXT: xor %s1, %s3, %s1
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i128 %b, %a %res = xor i128 %b, %a
ret i128 %res ret i128 %res
} }
define i128 @funci128(i128 %a) { define i128 @funci128(i128 %a) {
; CHECK-LABEL: funci128: ; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, 5, %s0 ; CHECK-NEXT: xor %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%res = xor i128 %a, 5 %res = xor i128 %a, 5
ret i128 %res ret i128 %res
} }

llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll

; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
; Test for correct placement of 'lvl' instructions ; Test for correct placement of 'lvl' instructions
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32)
declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32)
; Check that the backend can handle constant VL as well as parametric VL ; Check that the backend can handle constant VL as well as parametric VL
; sources. ; sources.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8* %Q) { define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8* %Q) {
; CHECK-LABEL: switching_vl: ; CHECK-LABEL: switching_vl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s4, 256 ; CHECK-NEXT: lea %s4, 256
; CHECK-NEXT: lvl %s4 ; CHECK-NEXT: lvl %s4
; CHECK-NEXT: vld %v0, 8, %s2 ; CHECK-NEXT: vld %v0, 8, %s2
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vst %v0, 16, %s3 ; CHECK-NEXT: vst %v0, 16, %s3
; CHECK-NEXT: lea %s4, 128 ; CHECK-NEXT: lea %s4, 128
; CHECK-NEXT: lvl %s4 ; CHECK-NEXT: lvl %s4
; CHECK-NEXT: vld %v0, 16, %s2 ; CHECK-NEXT: vld %v0, 16, %s2
; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1 ; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vst %v0, 16, %s3 ; CHECK-NEXT: vst %v0, 16, %s3
; CHECK-NEXT: lvl %s4 ; CHECK-NEXT: lvl %s4
; CHECK-NEXT: vld %v0, 8, %s2 ; CHECK-NEXT: vld %v0, 8, %s2
; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vst %v0, 16, %s3 ; CHECK-NEXT: vst %v0, 16, %s3
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 256) %l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 256)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl)
%l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 128) %l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 128)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l1, i64 16, i8* %Q, i32 %evl2) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l1, i64 16, i8* %Q, i32 %evl2)
%l2 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 128) %l2 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 128)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l2, i64 16, i8* %Q, i32 %evl) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l2, i64 16, i8* %Q, i32 %evl)
ret void ret void
} }
; Check that no redundant 'lvl' is inserted when vector length does not change ; Check that no redundant 'lvl' is inserted when vector length does not change
; in a basic block. ; in a basic block.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @stable_vl(i32 %evl, i8* %P, i8* %Q) { define void @stable_vl(i32 %evl, i8* %P, i8* %Q) {
; CHECK-LABEL: stable_vl: ; CHECK-LABEL: stable_vl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: lvl %s0 ; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vld %v0, 8, %s1 ; CHECK-NEXT: vld %v0, 8, %s1
; CHECK-NEXT: vst %v0, 16, %s2 ; CHECK-NEXT: vst %v0, 16, %s2
; CHECK-NEXT: vld %v0, 16, %s1 ; CHECK-NEXT: vld %v0, 16, %s1
; CHECK-NEXT: vst %v0, 16, %s2 ; CHECK-NEXT: vst %v0, 16, %s2
; CHECK-NEXT: vld %v0, 8, %s1 ; CHECK-NEXT: vld %v0, 8, %s1
; CHECK-NEXT: vst %v0, 16, %s2 ; CHECK-NEXT: vst %v0, 16, %s2
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 %evl) %l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 %evl)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl)
%l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 %evl) %l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 %evl)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l1, i64 16, i8* %Q, i32 %evl) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l1, i64 16, i8* %Q, i32 %evl)
%l2 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 %evl) %l2 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 %evl)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l2, i64 16, i8* %Q, i32 %evl) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l2, i64 16, i8* %Q, i32 %evl)
ret void ret void
} }

llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll

; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
;;; Test prefetch vector intrinsic instructions ;;; Test prefetch vector intrinsic instructions
;;; ;;;
;;; Note: ;;; Note:
;;; We test PFCHVrrl, PFCHVirl, PFCHVNCrrl, and PFCHVNCirl instructions. ;;; We test PFCHVrrl, PFCHVirl, PFCHVNCrrl, and PFCHVNCirl instructions.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @pfchv_vssl(i8* %0, i64 %1) { define void @pfchv_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: pfchv_vssl: ; CHECK-LABEL: pfchv_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: pfchv %s1, %s0 ; CHECK-NEXT: pfchv %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
tail call void @llvm.ve.vl.pfchv.ssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.pfchv.ssl(i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: inaccessiblemem_or_argmemonly nounwind ; Function Attrs: inaccessiblemem_or_argmemonly nounwind
declare void @llvm.ve.vl.pfchv.ssl(i64, i8*, i32) declare void @llvm.ve.vl.pfchv.ssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @pfchv_vssl_imm(i8* %0) { define void @pfchv_vssl_imm(i8* %0) {
; CHECK-LABEL: pfchv_vssl_imm: ; CHECK-LABEL: pfchv_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pfchv 8, %s0 ; CHECK-NEXT: pfchv 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
tail call void @llvm.ve.vl.pfchv.ssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.pfchv.ssl(i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @pfchvnc_vssl(i8* %0, i64 %1) { define void @pfchvnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: pfchvnc_vssl: ; CHECK-LABEL: pfchvnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: pfchv.nc %s1, %s0 ; CHECK-NEXT: pfchv.nc %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
tail call void @llvm.ve.vl.pfchvnc.ssl(i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.pfchvnc.ssl(i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: inaccessiblemem_or_argmemonly nounwind ; Function Attrs: inaccessiblemem_or_argmemonly nounwind
declare void @llvm.ve.vl.pfchvnc.ssl(i64, i8*, i32) declare void @llvm.ve.vl.pfchvnc.ssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @pfchvnc_vssl_imm(i8* %0) { define void @pfchvnc_vssl_imm(i8* %0) {
; CHECK-LABEL: pfchvnc_vssl_imm: ; CHECK-LABEL: pfchvnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pfchv.nc 8, %s0 ; CHECK-NEXT: pfchv.nc 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
tail call void @llvm.ve.vl.pfchvnc.ssl(i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.pfchvnc.ssl(i64 8, i8* %0, i32 256)
ret void ret void
} }

llvm/test/CodeGen/VE/VELIntrinsics/vld.ll

; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
;;; Test vector load intrinsic instructions ;;; Test vector load intrinsic instructions
;;; ;;;
;;; Note: ;;; Note:
;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, VLD*irl_v ;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, VLD*irl_v
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld_vssl(i8* %0, i64 %1) { define void @vld_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vld_vssl: ; CHECK-LABEL: vld_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld_vssvl(i8* %0, i64 %1, i8* %2) { define void @vld_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vld_vssvl: ; CHECK-LABEL: vld_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld %v0, %s1, %s2 ; CHECK-NEXT: vld %v0, %s1, %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vld.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld_vssl_imm(i8* %0) { define void @vld_vssl_imm(i8* %0) {
; CHECK-LABEL: vld_vssl_imm: ; CHECK-LABEL: vld_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld_vssvl_imm(i8* %0, i8* %1) { define void @vld_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vld_vssvl_imm: ; CHECK-LABEL: vld_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s1 ; CHECK-NEXT: vld %v0, 8, %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldnc_vssl(i8* %0, i64 %1) { define void @vldnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldnc_vssl: ; CHECK-LABEL: vldnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld.nc %v0, %s1, %s0 ; CHECK-NEXT: vld.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldnc_vssvl: ; CHECK-LABEL: vldnc_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld.nc %v0, %s1, %s2 ; CHECK-NEXT: vld.nc %v0, %s1, %s2
; CHECK-NEXT: vld.nc %v0, %s1, %s0 ; CHECK-NEXT: vld.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldnc_vssl_imm(i8* %0) { define void @vldnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldnc_vssl_imm: ; CHECK-LABEL: vldnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld.nc %v0, 8, %s0 ; CHECK-NEXT: vld.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldnc_vssvl_imm(i8* %0, i8* %1) { define void @vldnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldnc_vssvl_imm: ; CHECK-LABEL: vldnc_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld.nc %v0, 8, %s1 ; CHECK-NEXT: vld.nc %v0, 8, %s1
; CHECK-NEXT: vld.nc %v0, 8, %s0 ; CHECK-NEXT: vld.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu_vssl(i8* %0, i64 %1) { define void @vldu_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldu_vssl: ; CHECK-LABEL: vldu_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu %v0, %s1, %s0 ; CHECK-NEXT: vldu %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldu.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldu_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldu_vssvl: ; CHECK-LABEL: vldu_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldu %v0, %s1, %s2 ; CHECK-NEXT: vldu %v0, %s1, %s2
; CHECK-NEXT: vldu %v0, %s1, %s0 ; CHECK-NEXT: vldu %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldu.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu_vssl_imm(i8* %0) { define void @vldu_vssl_imm(i8* %0) {
; CHECK-LABEL: vldu_vssl_imm: ; CHECK-LABEL: vldu_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldu %v0, 8, %s0 ; CHECK-NEXT: vldu %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu_vssvl_imm(i8* %0, i8* %1) { define void @vldu_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldu_vssvl_imm: ; CHECK-LABEL: vldu_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu %v0, 8, %s1 ; CHECK-NEXT: vldu %v0, 8, %s1
; CHECK-NEXT: vldu %v0, 8, %s0 ; CHECK-NEXT: vldu %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldunc_vssl(i8* %0, i64 %1) { define void @vldunc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldunc_vssl: ; CHECK-LABEL: vldunc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu.nc %v0, %s1, %s0 ; CHECK-NEXT: vldu.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldunc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldunc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldunc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldunc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldunc_vssvl: ; CHECK-LABEL: vldunc_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldu.nc %v0, %s1, %s2 ; CHECK-NEXT: vldu.nc %v0, %s1, %s2
; CHECK-NEXT: vldu.nc %v0, %s1, %s0 ; CHECK-NEXT: vldu.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldunc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldunc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldunc_vssl_imm(i8* %0) { define void @vldunc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldunc_vssl_imm: ; CHECK-LABEL: vldunc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldu.nc %v0, 8, %s0 ; CHECK-NEXT: vldu.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldunc_vssvl_imm(i8* %0, i8* %1) { define void @vldunc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldunc_vssvl_imm: ; CHECK-LABEL: vldunc_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu.nc %v0, 8, %s1 ; CHECK-NEXT: vldu.nc %v0, 8, %s1
; CHECK-NEXT: vldu.nc %v0, 8, %s0 ; CHECK-NEXT: vldu.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldunc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsx_vssl(i8* %0, i64 %1) { define void @vldlsx_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldlsx_vssl: ; CHECK-LABEL: vldlsx_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.sx %v0, %s1, %s0 ; CHECK-NEXT: vldl.sx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldlsx.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsx_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldlsx_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldlsx_vssvl: ; CHECK-LABEL: vldlsx_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl.sx %v0, %s1, %s2 ; CHECK-NEXT: vldl.sx %v0, %s1, %s2
; CHECK-NEXT: vldl.sx %v0, %s1, %s0 ; CHECK-NEXT: vldl.sx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsx_vssl_imm(i8* %0) { define void @vldlsx_vssl_imm(i8* %0) {
; CHECK-LABEL: vldlsx_vssl_imm: ; CHECK-LABEL: vldlsx_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl.sx %v0, 8, %s0 ; CHECK-NEXT: vldl.sx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsx_vssvl_imm(i8* %0, i8* %1) { define void @vldlsx_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldlsx_vssvl_imm: ; CHECK-LABEL: vldlsx_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.sx %v0, 8, %s1 ; CHECK-NEXT: vldl.sx %v0, 8, %s1
; CHECK-NEXT: vldl.sx %v0, 8, %s0 ; CHECK-NEXT: vldl.sx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsxnc_vssl(i8* %0, i64 %1) { define void @vldlsxnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldlsxnc_vssl: ; CHECK-LABEL: vldlsxnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsxnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldlsxnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldlsxnc_vssvl: ; CHECK-LABEL: vldlsxnc_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s2 ; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s2
; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl.sx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsxnc_vssl_imm(i8* %0) { define void @vldlsxnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldlsxnc_vssl_imm: ; CHECK-LABEL: vldlsxnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlsxnc_vssvl_imm(i8* %0, i8* %1) { define void @vldlsxnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldlsxnc_vssvl_imm: ; CHECK-LABEL: vldlsxnc_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.sx.nc %v0, 8, %s1 ; CHECK-NEXT: vldl.sx.nc %v0, 8, %s1
; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl.sx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzx_vssl(i8* %0, i64 %1) { define void @vldlzx_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldlzx_vssl: ; CHECK-LABEL: vldlzx_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.zx %v0, %s1, %s0 ; CHECK-NEXT: vldl.zx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldlzx.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzx_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldlzx_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldlzx_vssvl: ; CHECK-LABEL: vldlzx_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl.zx %v0, %s1, %s2 ; CHECK-NEXT: vldl.zx %v0, %s1, %s2
; CHECK-NEXT: vldl.zx %v0, %s1, %s0 ; CHECK-NEXT: vldl.zx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzx_vssl_imm(i8* %0) { define void @vldlzx_vssl_imm(i8* %0) {
; CHECK-LABEL: vldlzx_vssl_imm: ; CHECK-LABEL: vldlzx_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl.zx %v0, 8, %s0 ; CHECK-NEXT: vldl.zx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzx_vssvl_imm(i8* %0, i8* %1) { define void @vldlzx_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldlzx_vssvl_imm: ; CHECK-LABEL: vldlzx_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.zx %v0, 8, %s1 ; CHECK-NEXT: vldl.zx %v0, 8, %s1
; CHECK-NEXT: vldl.zx %v0, 8, %s0 ; CHECK-NEXT: vldl.zx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzxnc_vssl(i8* %0, i64 %1) { define void @vldlzxnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldlzxnc_vssl: ; CHECK-LABEL: vldlzxnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzxnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldlzxnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldlzxnc_vssvl: ; CHECK-LABEL: vldlzxnc_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s2 ; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s2
; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl.zx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzxnc_vssl_imm(i8* %0) { define void @vldlzxnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldlzxnc_vssl_imm: ; CHECK-LABEL: vldlzxnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldlzxnc_vssvl_imm(i8* %0, i8* %1) { define void @vldlzxnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldlzxnc_vssvl_imm: ; CHECK-LABEL: vldlzxnc_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl.zx.nc %v0, 8, %s1 ; CHECK-NEXT: vldl.zx.nc %v0, 8, %s1
; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl.zx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldlzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2d_vssl(i8* %0, i64 %1) { define void @vld2d_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vld2d_vssl: ; CHECK-LABEL: vld2d_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld2d %v0, %s1, %s0 ; CHECK-NEXT: vld2d %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld2d.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vld2d.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2d_vssvl(i8* %0, i64 %1, i8* %2) { define void @vld2d_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vld2d_vssvl: ; CHECK-LABEL: vld2d_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld2d %v0, %s1, %s2 ; CHECK-NEXT: vld2d %v0, %s1, %s2
; CHECK-NEXT: vld2d %v0, %s1, %s0 ; CHECK-NEXT: vld2d %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld2d.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vld2d.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2d_vssl_imm(i8* %0) { define void @vld2d_vssl_imm(i8* %0) {
; CHECK-LABEL: vld2d_vssl_imm: ; CHECK-LABEL: vld2d_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld2d %v0, 8, %s0 ; CHECK-NEXT: vld2d %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2d_vssvl_imm(i8* %0, i8* %1) { define void @vld2d_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vld2d_vssvl_imm: ; CHECK-LABEL: vld2d_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld2d %v0, 8, %s1 ; CHECK-NEXT: vld2d %v0, 8, %s1
; CHECK-NEXT: vld2d %v0, 8, %s0 ; CHECK-NEXT: vld2d %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2dnc_vssl(i8* %0, i64 %1) { define void @vld2dnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vld2dnc_vssl: ; CHECK-LABEL: vld2dnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vld2d.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2dnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vld2dnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vld2dnc_vssvl: ; CHECK-LABEL: vld2dnc_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld2d.nc %v0, %s1, %s2 ; CHECK-NEXT: vld2d.nc %v0, %s1, %s2
; CHECK-NEXT: vld2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vld2d.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2dnc_vssl_imm(i8* %0) { define void @vld2dnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vld2dnc_vssl_imm: ; CHECK-LABEL: vld2dnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld2d.nc %v0, 8, %s0 ; CHECK-NEXT: vld2d.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vld2dnc_vssvl_imm(i8* %0, i8* %1) { define void @vld2dnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vld2dnc_vssvl_imm: ; CHECK-LABEL: vld2dnc_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld2d.nc %v0, 8, %s1 ; CHECK-NEXT: vld2d.nc %v0, 8, %s1
; CHECK-NEXT: vld2d.nc %v0, 8, %s0 ; CHECK-NEXT: vld2d.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vld2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2d_vssl(i8* %0, i64 %1) { define void @vldu2d_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldu2d_vssl: ; CHECK-LABEL: vldu2d_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu2d %v0, %s1, %s0 ; CHECK-NEXT: vldu2d %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu2d.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldu2d.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2d_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldu2d_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldu2d_vssvl: ; CHECK-LABEL: vldu2d_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldu2d %v0, %s1, %s2 ; CHECK-NEXT: vldu2d %v0, %s1, %s2
; CHECK-NEXT: vldu2d %v0, %s1, %s0 ; CHECK-NEXT: vldu2d %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2d_vssl_imm(i8* %0) { define void @vldu2d_vssl_imm(i8* %0) {
; CHECK-LABEL: vldu2d_vssl_imm: ; CHECK-LABEL: vldu2d_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldu2d %v0, 8, %s0 ; CHECK-NEXT: vldu2d %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2d_vssvl_imm(i8* %0, i8* %1) { define void @vldu2d_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldu2d_vssvl_imm: ; CHECK-LABEL: vldu2d_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu2d %v0, 8, %s1 ; CHECK-NEXT: vldu2d %v0, 8, %s1
; CHECK-NEXT: vldu2d %v0, 8, %s0 ; CHECK-NEXT: vldu2d %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2d.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2dnc_vssl(i8* %0, i64 %1) { define void @vldu2dnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldu2dnc_vssl: ; CHECK-LABEL: vldu2dnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2dnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldu2dnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldu2dnc_vssvl: ; CHECK-LABEL: vldu2dnc_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldu2d.nc %v0, %s1, %s2 ; CHECK-NEXT: vldu2d.nc %v0, %s1, %s2
; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vldu2d.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2dnc_vssl_imm(i8* %0) { define void @vldu2dnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldu2dnc_vssl_imm: ; CHECK-LABEL: vldu2dnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldu2d.nc %v0, 8, %s0 ; CHECK-NEXT: vldu2d.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldu2dnc_vssvl_imm(i8* %0, i8* %1) { define void @vldu2dnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldu2dnc_vssvl_imm: ; CHECK-LABEL: vldu2dnc_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldu2d.nc %v0, 8, %s1 ; CHECK-NEXT: vldu2d.nc %v0, 8, %s1
; CHECK-NEXT: vldu2d.nc %v0, 8, %s0 ; CHECK-NEXT: vldu2d.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldu2dnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsx_vssl(i8* %0, i64 %1) { define void @vldl2dsx_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldl2dsx_vssl: ; CHECK-LABEL: vldl2dsx_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsx_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldl2dsx_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldl2dsx_vssvl: ; CHECK-LABEL: vldl2dsx_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl2d.sx %v0, %s1, %s2 ; CHECK-NEXT: vldl2d.sx %v0, %s1, %s2
; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.sx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsx_vssl_imm(i8* %0) { define void @vldl2dsx_vssl_imm(i8* %0) {
; CHECK-LABEL: vldl2dsx_vssl_imm: ; CHECK-LABEL: vldl2dsx_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl2d.sx %v0, 8, %s0 ; CHECK-NEXT: vldl2d.sx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsx_vssvl_imm(i8* %0, i8* %1) { define void @vldl2dsx_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldl2dsx_vssvl_imm: ; CHECK-LABEL: vldl2dsx_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.sx %v0, 8, %s1 ; CHECK-NEXT: vldl2d.sx %v0, 8, %s1
; CHECK-NEXT: vldl2d.sx %v0, 8, %s0 ; CHECK-NEXT: vldl2d.sx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsxnc_vssl(i8* %0, i64 %1) { define void @vldl2dsxnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldl2dsxnc_vssl: ; CHECK-LABEL: vldl2dsxnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsxnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldl2dsxnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldl2dsxnc_vssvl: ; CHECK-LABEL: vldl2dsxnc_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s2 ; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s2
; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.sx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsxnc_vssl_imm(i8* %0) { define void @vldl2dsxnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldl2dsxnc_vssl_imm: ; CHECK-LABEL: vldl2dsxnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dsxnc_vssvl_imm(i8* %0, i8* %1) { define void @vldl2dsxnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldl2dsxnc_vssvl_imm: ; CHECK-LABEL: vldl2dsxnc_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s1 ; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s1
; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl2d.sx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dsxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzx_vssl(i8* %0, i64 %1) { define void @vldl2dzx_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldl2dzx_vssl: ; CHECK-LABEL: vldl2dzx_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.zx %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.zx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzx_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldl2dzx_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldl2dzx_vssvl: ; CHECK-LABEL: vldl2dzx_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl2d.zx %v0, %s1, %s2 ; CHECK-NEXT: vldl2d.zx %v0, %s1, %s2
; CHECK-NEXT: vldl2d.zx %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.zx %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzx_vssl_imm(i8* %0) { define void @vldl2dzx_vssl_imm(i8* %0) {
; CHECK-LABEL: vldl2dzx_vssl_imm: ; CHECK-LABEL: vldl2dzx_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl2d.zx %v0, 8, %s0 ; CHECK-NEXT: vldl2d.zx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzx_vssvl_imm(i8* %0, i8* %1) { define void @vldl2dzx_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldl2dzx_vssvl_imm: ; CHECK-LABEL: vldl2dzx_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.zx %v0, 8, %s1 ; CHECK-NEXT: vldl2d.zx %v0, 8, %s1
; CHECK-NEXT: vldl2d.zx %v0, 8, %s0 ; CHECK-NEXT: vldl2d.zx %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzx.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzxnc_vssl(i8* %0, i64 %1) { define void @vldl2dzxnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vldl2dzxnc_vssl: ; CHECK-LABEL: vldl2dzxnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %3, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzxnc_vssvl(i8* %0, i64 %1, i8* %2) { define void @vldl2dzxnc_vssvl(i8* %0, i64 %1, i8* %2) {
; CHECK-LABEL: vldl2dzxnc_vssvl: ; CHECK-LABEL: vldl2dzxnc_vssvl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256 ; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3 ; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s2 ; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s2
; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s0 ; CHECK-NEXT: vldl2d.zx.nc %v0, %s1, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %2, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 %1, i8* %2, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256) %5 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 %1, i8* %0, <256 x double> %4, i32 256)
tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0) tail call void asm sideeffect "vst $0, $1, $2", "v,r,r"(<256 x double> %5, i64 %1, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64, i8*, <256 x double>, i32) declare <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64, i8*, <256 x double>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzxnc_vssl_imm(i8* %0) { define void @vldl2dzxnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vldl2dzxnc_vssl_imm: ; CHECK-LABEL: vldl2dzxnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %0, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %0)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vldl2dzxnc_vssvl_imm(i8* %0, i8* %1) { define void @vldl2dzxnc_vssvl_imm(i8* %0, i8* %1) {
; CHECK-LABEL: vldl2dzxnc_vssvl_imm: ; CHECK-LABEL: vldl2dzxnc_vssvl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s1 ; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s1
; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s0 ; CHECK-NEXT: vldl2d.zx.nc %v0, 8, %s0
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %1, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssl(i64 8, i8* %1, i32 256)
%4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256) %4 = tail call fast <256 x double> @llvm.ve.vl.vldl2dzxnc.vssvl(i64 8, i8* %0, <256 x double> %3, i32 256)
tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0) tail call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %4, i8* %0)
ret void ret void
} }

llvm/test/CodeGen/VE/VELIntrinsics/vst.ll

; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
;;; Test vector store intrinsic instructions ;;; Test vector store intrinsic instructions
;;; ;;;
;;; Note: ;;; Note:
;;; We test VST*rrvl, VST*rrvml, VST*irvl, and VST*irvml instructions. ;;; We test VST*rrvl, VST*rrvml, VST*irvl, and VST*irvml instructions.
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst_vssl(i8* %0, i64 %1) { define void @vst_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vst_vssl: ; CHECK-LABEL: vst_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst %v0, %s1, %s0 ; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32) declare <256 x double> @llvm.ve.vl.vld.vssl(i64, i8*, i32)
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst_vssml(i8* %0, i64 %1) { define void @vst_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vst_vssml: ; CHECK-LABEL: vst_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vst %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vst.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst_vssl_imm(i8* %0) { define void @vst_vssl_imm(i8* %0) {
; CHECK-LABEL: vst_vssl_imm: ; CHECK-LABEL: vst_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst %v0, 8, %s0 ; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst_vssml_imm(i8* %0) { define void @vst_vssml_imm(i8* %0) {
; CHECK-LABEL: vst_vssml_imm: ; CHECK-LABEL: vst_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst %v0, 8, %s0, %vm0 ; CHECK-NEXT: vst %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstnc_vssl(i8* %0, i64 %1) { define void @vstnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstnc_vssl: ; CHECK-LABEL: vstnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst.nc %v0, %s1, %s0 ; CHECK-NEXT: vst.nc %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstnc.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstnc.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstnc_vssml(i8* %0, i64 %1) { define void @vstnc_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstnc_vssml: ; CHECK-LABEL: vstnc_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst.nc %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vst.nc %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstnc_vssl_imm(i8* %0) { define void @vstnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vstnc_vssl_imm: ; CHECK-LABEL: vstnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst.nc %v0, 8, %s0 ; CHECK-NEXT: vst.nc %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstnc_vssml_imm(i8* %0) { define void @vstnc_vssml_imm(i8* %0) {
; CHECK-LABEL: vstnc_vssml_imm: ; CHECK-LABEL: vstnc_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst.nc %v0, 8, %s0, %vm0 ; CHECK-NEXT: vst.nc %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstot_vssl(i8* %0, i64 %1) { define void @vstot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstot_vssl: ; CHECK-LABEL: vstot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst.ot %v0, %s1, %s0 ; CHECK-NEXT: vst.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstot_vssml(i8* %0, i64 %1) { define void @vstot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstot_vssml: ; CHECK-LABEL: vstot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vst.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstot_vssl_imm(i8* %0) { define void @vstot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstot_vssl_imm: ; CHECK-LABEL: vstot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst.ot %v0, 8, %s0 ; CHECK-NEXT: vst.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstot_vssml_imm(i8* %0) { define void @vstot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstot_vssml_imm: ; CHECK-LABEL: vstot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vst.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstncot_vssl(i8* %0, i64 %1) { define void @vstncot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstncot_vssl: ; CHECK-LABEL: vstncot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst.nc.ot %v0, %s1, %s0 ; CHECK-NEXT: vst.nc.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstncot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstncot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstncot_vssml(i8* %0, i64 %1) { define void @vstncot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstncot_vssml: ; CHECK-LABEL: vstncot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst.nc.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vst.nc.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstncot_vssl_imm(i8* %0) { define void @vstncot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstncot_vssl_imm: ; CHECK-LABEL: vstncot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst.nc.ot %v0, 8, %s0 ; CHECK-NEXT: vst.nc.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstncot_vssml_imm(i8* %0) { define void @vstncot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstncot_vssml_imm: ; CHECK-LABEL: vstncot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst.nc.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vst.nc.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu_vssl(i8* %0, i64 %1) { define void @vstu_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstu_vssl: ; CHECK-LABEL: vstu_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu %v0, %s1, %s0 ; CHECK-NEXT: vstu %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstu.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu_vssml(i8* %0, i64 %1) { define void @vstu_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstu_vssml: ; CHECK-LABEL: vstu_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstu %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstu.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu_vssl_imm(i8* %0) { define void @vstu_vssl_imm(i8* %0) {
; CHECK-LABEL: vstu_vssl_imm: ; CHECK-LABEL: vstu_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu %v0, 8, %s0 ; CHECK-NEXT: vstu %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu_vssml_imm(i8* %0) { define void @vstu_vssml_imm(i8* %0) {
; CHECK-LABEL: vstu_vssml_imm: ; CHECK-LABEL: vstu_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstu %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstunc_vssl(i8* %0, i64 %1) { define void @vstunc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstunc_vssl: ; CHECK-LABEL: vstunc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu.nc %v0, %s1, %s0 ; CHECK-NEXT: vstu.nc %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstunc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstunc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstunc.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstunc.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstunc_vssml(i8* %0, i64 %1) { define void @vstunc_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstunc_vssml: ; CHECK-LABEL: vstunc_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu.nc %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstu.nc %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstunc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstunc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstunc_vssl_imm(i8* %0) { define void @vstunc_vssl_imm(i8* %0) {
; CHECK-LABEL: vstunc_vssl_imm: ; CHECK-LABEL: vstunc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu.nc %v0, 8, %s0 ; CHECK-NEXT: vstu.nc %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstunc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstunc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstunc_vssml_imm(i8* %0) { define void @vstunc_vssml_imm(i8* %0) {
; CHECK-LABEL: vstunc_vssml_imm: ; CHECK-LABEL: vstunc_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu.nc %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstu.nc %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstuot_vssl(i8* %0, i64 %1) { define void @vstuot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstuot_vssl: ; CHECK-LABEL: vstuot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu.ot %v0, %s1, %s0 ; CHECK-NEXT: vstu.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstuot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstuot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstuot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstuot_vssml(i8* %0, i64 %1) { define void @vstuot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstuot_vssml: ; CHECK-LABEL: vstuot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstu.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstuot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstuot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstuot_vssl_imm(i8* %0) { define void @vstuot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstuot_vssl_imm: ; CHECK-LABEL: vstuot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu.ot %v0, 8, %s0 ; CHECK-NEXT: vstu.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstuot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstuot_vssml_imm(i8* %0) { define void @vstuot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstuot_vssml_imm: ; CHECK-LABEL: vstuot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstu.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstuncot_vssl(i8* %0, i64 %1) { define void @vstuncot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstuncot_vssl: ; CHECK-LABEL: vstuncot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu.nc.ot %v0, %s1, %s0 ; CHECK-NEXT: vstu.nc.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstuncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstuncot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstuncot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstuncot_vssml(i8* %0, i64 %1) { define void @vstuncot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstuncot_vssml: ; CHECK-LABEL: vstuncot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu.nc.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstu.nc.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstuncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstuncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstuncot_vssl_imm(i8* %0) { define void @vstuncot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstuncot_vssl_imm: ; CHECK-LABEL: vstuncot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu.nc.ot %v0, 8, %s0 ; CHECK-NEXT: vstu.nc.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstuncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstuncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstuncot_vssml_imm(i8* %0) { define void @vstuncot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstuncot_vssml_imm: ; CHECK-LABEL: vstuncot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu.nc.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstu.nc.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl_vssl(i8* %0, i64 %1) { define void @vstl_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstl_vssl: ; CHECK-LABEL: vstl_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl %v0, %s1, %s0 ; CHECK-NEXT: vstl %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstl.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl_vssml(i8* %0, i64 %1) { define void @vstl_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstl_vssml: ; CHECK-LABEL: vstl_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstl %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstl.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl_vssl_imm(i8* %0) { define void @vstl_vssl_imm(i8* %0) {
; CHECK-LABEL: vstl_vssl_imm: ; CHECK-LABEL: vstl_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl %v0, 8, %s0 ; CHECK-NEXT: vstl %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl_vssml_imm(i8* %0) { define void @vstl_vssml_imm(i8* %0) {
; CHECK-LABEL: vstl_vssml_imm: ; CHECK-LABEL: vstl_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstl %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlnc_vssl(i8* %0, i64 %1) { define void @vstlnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstlnc_vssl: ; CHECK-LABEL: vstlnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl.nc %v0, %s1, %s0 ; CHECK-NEXT: vstl.nc %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstlnc.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstlnc.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlnc_vssml(i8* %0, i64 %1) { define void @vstlnc_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstlnc_vssml: ; CHECK-LABEL: vstlnc_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl.nc %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstl.nc %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstlnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstlnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlnc_vssl_imm(i8* %0) { define void @vstlnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vstlnc_vssl_imm: ; CHECK-LABEL: vstlnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl.nc %v0, 8, %s0 ; CHECK-NEXT: vstl.nc %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlnc_vssml_imm(i8* %0) { define void @vstlnc_vssml_imm(i8* %0) {
; CHECK-LABEL: vstlnc_vssml_imm: ; CHECK-LABEL: vstlnc_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl.nc %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstl.nc %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlot_vssl(i8* %0, i64 %1) { define void @vstlot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstlot_vssl: ; CHECK-LABEL: vstlot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl.ot %v0, %s1, %s0 ; CHECK-NEXT: vstl.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstlot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstlot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlot_vssml(i8* %0, i64 %1) { define void @vstlot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstlot_vssml: ; CHECK-LABEL: vstlot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstl.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstlot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstlot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlot_vssl_imm(i8* %0) { define void @vstlot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstlot_vssl_imm: ; CHECK-LABEL: vstlot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl.ot %v0, 8, %s0 ; CHECK-NEXT: vstl.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlot_vssml_imm(i8* %0) { define void @vstlot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstlot_vssml_imm: ; CHECK-LABEL: vstlot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstl.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlncot_vssl(i8* %0, i64 %1) { define void @vstlncot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstlncot_vssl: ; CHECK-LABEL: vstlncot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl.nc.ot %v0, %s1, %s0 ; CHECK-NEXT: vstl.nc.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstlncot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstlncot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlncot_vssml(i8* %0, i64 %1) { define void @vstlncot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstlncot_vssml: ; CHECK-LABEL: vstlncot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl.nc.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstl.nc.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstlncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstlncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlncot_vssl_imm(i8* %0) { define void @vstlncot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstlncot_vssl_imm: ; CHECK-LABEL: vstlncot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl.nc.ot %v0, 8, %s0 ; CHECK-NEXT: vstl.nc.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstlncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstlncot_vssml_imm(i8* %0) { define void @vstlncot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstlncot_vssml_imm: ; CHECK-LABEL: vstlncot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl.nc.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstl.nc.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2d_vssl(i8* %0, i64 %1) { define void @vst2d_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vst2d_vssl: ; CHECK-LABEL: vst2d_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst2d %v0, %s1, %s0 ; CHECK-NEXT: vst2d %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst2d.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vst2d.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2d_vssml(i8* %0, i64 %1) { define void @vst2d_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vst2d_vssml: ; CHECK-LABEL: vst2d_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst2d %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vst2d %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst2d.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vst2d.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2d_vssl_imm(i8* %0) { define void @vst2d_vssl_imm(i8* %0) {
; CHECK-LABEL: vst2d_vssl_imm: ; CHECK-LABEL: vst2d_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst2d %v0, 8, %s0 ; CHECK-NEXT: vst2d %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2d_vssml_imm(i8* %0) { define void @vst2d_vssml_imm(i8* %0) {
; CHECK-LABEL: vst2d_vssml_imm: ; CHECK-LABEL: vst2d_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst2d %v0, 8, %s0, %vm0 ; CHECK-NEXT: vst2d %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dnc_vssl(i8* %0, i64 %1) { define void @vst2dnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vst2dnc_vssl: ; CHECK-LABEL: vst2dnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vst2d.nc %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst2dnc.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vst2dnc.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dnc_vssml(i8* %0, i64 %1) { define void @vst2dnc_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vst2dnc_vssml: ; CHECK-LABEL: vst2dnc_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst2d.nc %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vst2d.nc %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst2dnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vst2dnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dnc_vssl_imm(i8* %0) { define void @vst2dnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vst2dnc_vssl_imm: ; CHECK-LABEL: vst2dnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst2d.nc %v0, 8, %s0 ; CHECK-NEXT: vst2d.nc %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dnc_vssml_imm(i8* %0) { define void @vst2dnc_vssml_imm(i8* %0) {
; CHECK-LABEL: vst2dnc_vssml_imm: ; CHECK-LABEL: vst2dnc_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst2d.nc %v0, 8, %s0, %vm0 ; CHECK-NEXT: vst2d.nc %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dot_vssl(i8* %0, i64 %1) { define void @vst2dot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vst2dot_vssl: ; CHECK-LABEL: vst2dot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst2d.ot %v0, %s1, %s0 ; CHECK-NEXT: vst2d.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst2dot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vst2dot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dot_vssml(i8* %0, i64 %1) { define void @vst2dot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vst2dot_vssml: ; CHECK-LABEL: vst2dot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst2d.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vst2d.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst2dot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vst2dot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dot_vssl_imm(i8* %0) { define void @vst2dot_vssl_imm(i8* %0) {
; CHECK-LABEL: vst2dot_vssl_imm: ; CHECK-LABEL: vst2dot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst2d.ot %v0, 8, %s0 ; CHECK-NEXT: vst2d.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dot_vssml_imm(i8* %0) { define void @vst2dot_vssml_imm(i8* %0) {
; CHECK-LABEL: vst2dot_vssml_imm: ; CHECK-LABEL: vst2dot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst2d.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vst2d.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dncot_vssl(i8* %0, i64 %1) { define void @vst2dncot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vst2dncot_vssl: ; CHECK-LABEL: vst2dncot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst2d.nc.ot %v0, %s1, %s0 ; CHECK-NEXT: vst2d.nc.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst2dncot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vst2dncot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dncot_vssml(i8* %0, i64 %1) { define void @vst2dncot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vst2dncot_vssml: ; CHECK-LABEL: vst2dncot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vst2d.nc.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vst2d.nc.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vst2dncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vst2dncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dncot_vssl_imm(i8* %0) { define void @vst2dncot_vssl_imm(i8* %0) {
; CHECK-LABEL: vst2dncot_vssl_imm: ; CHECK-LABEL: vst2dncot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst2d.nc.ot %v0, 8, %s0 ; CHECK-NEXT: vst2d.nc.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vst2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vst2dncot_vssml_imm(i8* %0) { define void @vst2dncot_vssml_imm(i8* %0) {
; CHECK-LABEL: vst2dncot_vssml_imm: ; CHECK-LABEL: vst2dncot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vst2d.nc.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vst2d.nc.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2d_vssl(i8* %0, i64 %1) { define void @vstu2d_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstu2d_vssl: ; CHECK-LABEL: vstu2d_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu2d %v0, %s1, %s0 ; CHECK-NEXT: vstu2d %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu2d.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstu2d.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2d_vssml(i8* %0, i64 %1) { define void @vstu2d_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstu2d_vssml: ; CHECK-LABEL: vstu2d_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu2d %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstu2d %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu2d.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstu2d.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2d_vssl_imm(i8* %0) { define void @vstu2d_vssl_imm(i8* %0) {
; CHECK-LABEL: vstu2d_vssl_imm: ; CHECK-LABEL: vstu2d_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu2d %v0, 8, %s0 ; CHECK-NEXT: vstu2d %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2d_vssml_imm(i8* %0) { define void @vstu2d_vssml_imm(i8* %0) {
; CHECK-LABEL: vstu2d_vssml_imm: ; CHECK-LABEL: vstu2d_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu2d %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstu2d %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dnc_vssl(i8* %0, i64 %1) { define void @vstu2dnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstu2dnc_vssl: ; CHECK-LABEL: vstu2dnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vstu2d.nc %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu2dnc.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstu2dnc.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dnc_vssml(i8* %0, i64 %1) { define void @vstu2dnc_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstu2dnc_vssml: ; CHECK-LABEL: vstu2dnc_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu2d.nc %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstu2d.nc %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu2dnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstu2dnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dnc_vssl_imm(i8* %0) { define void @vstu2dnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vstu2dnc_vssl_imm: ; CHECK-LABEL: vstu2dnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu2d.nc %v0, 8, %s0 ; CHECK-NEXT: vstu2d.nc %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dnc_vssml_imm(i8* %0) { define void @vstu2dnc_vssml_imm(i8* %0) {
; CHECK-LABEL: vstu2dnc_vssml_imm: ; CHECK-LABEL: vstu2dnc_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu2d.nc %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstu2d.nc %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dot_vssl(i8* %0, i64 %1) { define void @vstu2dot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstu2dot_vssl: ; CHECK-LABEL: vstu2dot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu2d.ot %v0, %s1, %s0 ; CHECK-NEXT: vstu2d.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu2dot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstu2dot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dot_vssml(i8* %0, i64 %1) { define void @vstu2dot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstu2dot_vssml: ; CHECK-LABEL: vstu2dot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu2d.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstu2d.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu2dot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstu2dot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dot_vssl_imm(i8* %0) { define void @vstu2dot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstu2dot_vssl_imm: ; CHECK-LABEL: vstu2dot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu2d.ot %v0, 8, %s0 ; CHECK-NEXT: vstu2d.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dot_vssml_imm(i8* %0) { define void @vstu2dot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstu2dot_vssml_imm: ; CHECK-LABEL: vstu2dot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu2d.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstu2d.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dncot_vssl(i8* %0, i64 %1) { define void @vstu2dncot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstu2dncot_vssl: ; CHECK-LABEL: vstu2dncot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu2d.nc.ot %v0, %s1, %s0 ; CHECK-NEXT: vstu2d.nc.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu2dncot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstu2dncot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dncot_vssml(i8* %0, i64 %1) { define void @vstu2dncot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstu2dncot_vssml: ; CHECK-LABEL: vstu2dncot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstu2d.nc.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstu2d.nc.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstu2dncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstu2dncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dncot_vssl_imm(i8* %0) { define void @vstu2dncot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstu2dncot_vssl_imm: ; CHECK-LABEL: vstu2dncot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu2d.nc.ot %v0, 8, %s0 ; CHECK-NEXT: vstu2d.nc.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstu2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstu2dncot_vssml_imm(i8* %0) { define void @vstu2dncot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstu2dncot_vssml_imm: ; CHECK-LABEL: vstu2dncot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstu2d.nc.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstu2d.nc.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2d_vssl(i8* %0, i64 %1) { define void @vstl2d_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstl2d_vssl: ; CHECK-LABEL: vstl2d_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl2d %v0, %s1, %s0 ; CHECK-NEXT: vstl2d %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2d.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl2d.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstl2d.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2d_vssml(i8* %0, i64 %1) { define void @vstl2d_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstl2d_vssml: ; CHECK-LABEL: vstl2d_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl2d %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstl2d %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl2d.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstl2d.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2d_vssl_imm(i8* %0) { define void @vstl2d_vssl_imm(i8* %0) {
; CHECK-LABEL: vstl2d_vssl_imm: ; CHECK-LABEL: vstl2d_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl2d %v0, 8, %s0 ; CHECK-NEXT: vstl2d %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2d.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2d_vssml_imm(i8* %0) { define void @vstl2d_vssml_imm(i8* %0) {
; CHECK-LABEL: vstl2d_vssml_imm: ; CHECK-LABEL: vstl2d_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl2d %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstl2d %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dnc_vssl(i8* %0, i64 %1) { define void @vstl2dnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstl2dnc_vssl: ; CHECK-LABEL: vstl2dnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl2d.nc %v0, %s1, %s0 ; CHECK-NEXT: vstl2d.nc %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dnc.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl2dnc.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstl2dnc.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dnc_vssml(i8* %0, i64 %1) { define void @vstl2dnc_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstl2dnc_vssml: ; CHECK-LABEL: vstl2dnc_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl2d.nc %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstl2d.nc %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl2dnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstl2dnc.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dnc_vssl_imm(i8* %0) { define void @vstl2dnc_vssl_imm(i8* %0) {
; CHECK-LABEL: vstl2dnc_vssl_imm: ; CHECK-LABEL: vstl2dnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl2d.nc %v0, 8, %s0 ; CHECK-NEXT: vstl2d.nc %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dnc.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dnc_vssml_imm(i8* %0) { define void @vstl2dnc_vssml_imm(i8* %0) {
; CHECK-LABEL: vstl2dnc_vssml_imm: ; CHECK-LABEL: vstl2dnc_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl2d.nc %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstl2d.nc %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dot_vssl(i8* %0, i64 %1) { define void @vstl2dot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstl2dot_vssl: ; CHECK-LABEL: vstl2dot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl2d.ot %v0, %s1, %s0 ; CHECK-NEXT: vstl2d.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl2dot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstl2dot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dot_vssml(i8* %0, i64 %1) { define void @vstl2dot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstl2dot_vssml: ; CHECK-LABEL: vstl2dot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl2d.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstl2d.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl2dot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstl2dot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dot_vssl_imm(i8* %0) { define void @vstl2dot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstl2dot_vssl_imm: ; CHECK-LABEL: vstl2dot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl2d.ot %v0, 8, %s0 ; CHECK-NEXT: vstl2d.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dot_vssml_imm(i8* %0) { define void @vstl2dot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstl2dot_vssml_imm: ; CHECK-LABEL: vstl2dot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl2d.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstl2d.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dncot_vssl(i8* %0, i64 %1) { define void @vstl2dncot_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: vstl2dncot_vssl: ; CHECK-LABEL: vstl2dncot_vssl:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl2d.nc.ot %v0, %s1, %s0 ; CHECK-NEXT: vstl2d.nc.ot %v0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dncot.vssl(<256 x double> %3, i64 %1, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl2dncot.vssl(<256 x double>, i64, i8*, i32) declare void @llvm.ve.vl.vstl2dncot.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dncot_vssml(i8* %0, i64 %1) { define void @vstl2dncot_vssml(i8* %0, i64 %1) {
; CHECK-LABEL: vstl2dncot_vssml: ; CHECK-LABEL: vstl2dncot_vssml:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256 ; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2 ; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, %s1, %s0 ; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: vstl2d.nc.ot %v0, %s1, %s0, %vm0 ; CHECK-NEXT: vstl2d.nc.ot %v0, %s1, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256) %3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.ve.vl.vstl2dncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32) declare void @llvm.ve.vl.vstl2dncot.vssml(<256 x double>, i64, i8*, <256 x i1>, i32)
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dncot_vssl_imm(i8* %0) { define void @vstl2dncot_vssl_imm(i8* %0) {
; CHECK-LABEL: vstl2dncot_vssl_imm: ; CHECK-LABEL: vstl2dncot_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl2d.nc.ot %v0, 8, %s0 ; CHECK-NEXT: vstl2d.nc.ot %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256) tail call void @llvm.ve.vl.vstl2dncot.vssl(<256 x double> %2, i64 8, i8* %0, i32 256)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @vstl2dncot_vssml_imm(i8* %0) { define void @vstl2dncot_vssml_imm(i8* %0) {
; CHECK-LABEL: vstl2dncot_vssml_imm: ; CHECK-LABEL: vstl2dncot_vssml_imm:
; CHECK: .LBB{{[0-9]+}}_2: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256 ; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1 ; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vld %v0, 8, %s0 ; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: vstl2d.nc.ot %v0, 8, %s0, %vm0 ; CHECK-NEXT: vstl2d.nc.ot %v0, 8, %s0, %vm0
; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256) %2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256) tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
ret void ret void
} }
llvm/test/CodeGen/VE/Scalar/shr.ll