[ARM][SchedModels] Add support for branch forms of ALU instructions to Cortex-A57 model

[evgeny777]

Summary

Patch also fixes computation of mutually exclusive predicates for sequences of variants to be properly expanded

[evgeny777]

Fixed issue with accessing wrong element in vector

[dmgreen]

llvm/utils/TableGen/CodeGenSchedule.cpp

1373

Looks like it's worth clang-formatting the change.

1390–1392

"A to C and from A to B"?

Wonderful comment by the way, now that (I think) I understand it.

llvm/utils/TableGen/SubtargetEmitter.cpp

1452

Extra ;

1629

This can probably move below the if

[evgeny777]

Addressed

[dmgreen]

Thanks. LGTM.

llvm/utils/TableGen/SubtargetEmitter.cpp

1623–1628

Some extra whitespace, which can be removed.

llvm/lib/Target/ARM/ARM.td

 // Aliases
 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 
-
-//===----------------------------------------------------------------------===//
-// ARM schedules.
-//===----------------------------------------------------------------------===//
-//
-include "ARMPredicates.td"
-include "ARMSchedule.td"
-
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "ARMRegisterInfo.td"
 include "ARMRegisterBanks.td"
 include "ARMCallingConv.td"
 
 //===----------------------------------------------------------------------===//
+// ARM schedules.
+//===----------------------------------------------------------------------===//
+//
+include "ARMPredicates.td"
+include "ARMSchedule.td"
+
+//===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "ARMInstrInfo.td"
 def ARMInstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // ARM schedules

llvm/lib/Target/ARM/ARMSchedule.td

 
 let FunctionMapper = "ARM_AM::getAM3Op" in {
   class CheckAM3OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {}
 }
 
 // LDM, base reg in list
 def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
 
+class IsRegPCPred<int n> : MCSchedPredicate<CheckRegOperand<n, PC>>;
+
+class BranchWriteRes<int lat, int uops, list<ProcResourceKind> resl,
+                     list<int> rcl, SchedWriteRes wr> :
+  SchedWriteRes<!listconcat(wr.ProcResources, resl)> {
+  let Latency = !add(wr.Latency, lat);
+  let ResourceCycles = !listconcat(wr.ResourceCycles, rcl);
+  let NumMicroOps = !add(wr.NumMicroOps, uops);
+  SchedWriteRes BaseWr = wr;
+}
+
+class CheckBranchForm<int n, BranchWriteRes br> :
+  SchedWriteVariant<[
+    SchedVar<IsRegPCPred<n>, [br]>,
+    SchedVar<NoSchedPred,    [br.BaseWr]>
+  ]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //
 def IIC_iALUx      : InstrItinClass;
 def IIC_iALUi      : InstrItinClass;
 def IIC_iALUr      : InstrItinClass;
 def IIC_iALUsi     : InstrItinClass;
 def IIC_iALUsir    : InstrItinClass;

llvm/lib/Target/ARM/ARMScheduleA57.td

 def : InstRW<[A57Write_6cyc_1B_1L], (instregex "BR_JTm")>;
 
 // --- 3.3 Arithmetic and Logical Instructions ---
 // ADD{S}, ADC{S}, ADR, AND{S}, BIC{S}, CMN, CMP, EOR{S}, ORN{S}, ORR{S},
 // RSB{S}, RSC{S}, SUB{S}, SBC{S}, TEQ, TST
 
 def : InstRW<[A57Write_1cyc_1I], (instregex "tADDframe")>;
 
+// Check branch forms of ALU ops:
+// check reg 0 for ARM_AM::PC
+// if so adds 2 cyc to latency, 1 uop, 1 res cycle for A57UnitB
+class A57BranchForm<SchedWriteRes non_br> :
+  BranchWriteRes<2, 1, [A57UnitB], [1], non_br>;
+
 // shift by register, conditional or unconditional
 // TODO: according to the doc, conditional uses I0/I1, unconditional uses M
 // Why more complex instruction uses more simple pipeline?
 // May be an error in doc.
 def A57WriteALUsi : SchedWriteVariant<[
   // lsl #2, lsl #1, or lsr #1.
-  SchedVar<IsPredicatedPred, [A57Write_2cyc_1M]>,
-  SchedVar<NoSchedPred,      [A57Write_2cyc_1M]>
+  SchedVar<IsPredicatedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>,
+  SchedVar<NoSchedPred,      [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>
 ]>;
 def A57WriteALUsr : SchedWriteVariant<[
-  SchedVar<IsPredicatedPred, [A57Write_2cyc_1I]>,
-  SchedVar<NoSchedPred,      [A57Write_2cyc_1M]>
+  SchedVar<IsPredicatedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1I>>]>,
+  SchedVar<NoSchedPred,      [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>
 ]>;
 def A57WriteALUSsr : SchedWriteVariant<[
-  SchedVar<IsPredicatedPred, [A57Write_2cyc_1I]>,
-  SchedVar<NoSchedPred,      [A57Write_2cyc_1M]>
+  SchedVar<IsPredicatedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1I>>]>,
+  SchedVar<NoSchedPred,      [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>
 ]>;
 def A57ReadALUsr : SchedReadVariant<[
   SchedVar<IsPredicatedPred, [ReadDefault]>,
   SchedVar<NoSchedPred,      [ReadDefault]>
 ]>;
 def : SchedAlias<WriteALUsi,  A57WriteALUsi>;
 def : SchedAlias<WriteALUsr,  A57WriteALUsr>;
 def : SchedAlias<WriteALUSsr, A57WriteALUSsr>;

 def A57WriteVLDMuncond : SchedWriteVariant<[
   SchedVar<A57LMAddrPred1,  A57VLDMOpsListUncond.Writes[0-1]>,
   SchedVar<A57LMAddrPred2,  A57VLDMOpsListUncond.Writes[0-3]>,
   SchedVar<A57LMAddrPred3,  A57VLDMOpsListUncond.Writes[0-5]>,
   SchedVar<A57LMAddrPred4,  A57VLDMOpsListUncond.Writes[0-7]>,
   SchedVar<A57LMAddrPred5,  A57VLDMOpsListUncond.Writes[0-9]>,
   SchedVar<A57LMAddrPred6,  A57VLDMOpsListUncond.Writes[0-11]>,
   SchedVar<A57LMAddrPred7,  A57VLDMOpsListUncond.Writes[0-13]>,
-  SchedVar<A57LMAddrPred8,  A57VLDMOpsListUncond.Writes[0-15]>,
   SchedVar<NoSchedPred,     A57VLDMOpsListUncond.Writes[0-15]>
 ]> { let Variadic=1; }
 
 def A57VLDMOpsListCond : A57WriteLMOpsListType<
                [A57Write_5cyc_1L, A57Write_6cyc_1L,
                 A57Write_7cyc_1L, A57Write_8cyc_1L,
                 A57Write_9cyc_1L, A57Write_10cyc_1L,
                 A57Write_11cyc_1L, A57Write_12cyc_1L,
                 A57Write_13cyc_1L, A57Write_14cyc_1L,
                 A57Write_15cyc_1L, A57Write_16cyc_1L,
                 A57Write_17cyc_1L, A57Write_18cyc_1L,
                 A57Write_19cyc_1L, A57Write_20cyc_1L]>;
 def A57WriteVLDMcond : SchedWriteVariant<[
   SchedVar<A57LMAddrPred1,  A57VLDMOpsListCond.Writes[0-1]>,
   SchedVar<A57LMAddrPred2,  A57VLDMOpsListCond.Writes[0-3]>,
   SchedVar<A57LMAddrPred3,  A57VLDMOpsListCond.Writes[0-5]>,
   SchedVar<A57LMAddrPred4,  A57VLDMOpsListCond.Writes[0-7]>,
   SchedVar<A57LMAddrPred5,  A57VLDMOpsListCond.Writes[0-9]>,
   SchedVar<A57LMAddrPred6,  A57VLDMOpsListCond.Writes[0-11]>,
   SchedVar<A57LMAddrPred7,  A57VLDMOpsListCond.Writes[0-13]>,
-  SchedVar<A57LMAddrPred8,  A57VLDMOpsListCond.Writes[0-15]>,
   SchedVar<NoSchedPred,     A57VLDMOpsListCond.Writes[0-15]>
 ]> { let Variadic=1; }
 
 def A57WriteVLDM : SchedWriteVariant<[
   SchedVar<IsPredicatedPred, [A57WriteVLDMcond]>,
   SchedVar<NoSchedPred,      [A57WriteVLDMuncond]>
 ]> { let Variadic=1; }
 

 def A57WriteVLDMuncond_UPD : SchedWriteVariant<[
   SchedVar<A57LMAddrPred1,  A57VLDMOpsListUncond_Upd.Writes[0-1]>,
   SchedVar<A57LMAddrPred2,  A57VLDMOpsListUncond_Upd.Writes[0-3]>,
   SchedVar<A57LMAddrPred3,  A57VLDMOpsListUncond_Upd.Writes[0-5]>,
   SchedVar<A57LMAddrPred4,  A57VLDMOpsListUncond_Upd.Writes[0-7]>,
   SchedVar<A57LMAddrPred5,  A57VLDMOpsListUncond_Upd.Writes[0-9]>,
   SchedVar<A57LMAddrPred6,  A57VLDMOpsListUncond_Upd.Writes[0-11]>,
   SchedVar<A57LMAddrPred7,  A57VLDMOpsListUncond_Upd.Writes[0-13]>,
-  SchedVar<A57LMAddrPred8,  A57VLDMOpsListUncond_Upd.Writes[0-15]>,
   SchedVar<NoSchedPred,     A57VLDMOpsListUncond_Upd.Writes[0-15]>
 ]> { let Variadic=1; }
 
 def A57VLDMOpsListCond_Upd : A57WriteLMOpsListType<
                [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I,
                 A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I,
                 A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I,
                 A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I,
                 A57Write_13cyc_1L_1I, A57Write_14cyc_1L_1I,
                 A57Write_15cyc_1L_1I, A57Write_16cyc_1L_1I,
                 A57Write_17cyc_1L_1I, A57Write_18cyc_1L_1I,
                 A57Write_19cyc_1L_1I, A57Write_20cyc_1L_1I]>;
 def A57WriteVLDMcond_UPD : SchedWriteVariant<[
   SchedVar<A57LMAddrPred1,  A57VLDMOpsListCond_Upd.Writes[0-1]>,
   SchedVar<A57LMAddrPred2,  A57VLDMOpsListCond_Upd.Writes[0-3]>,
   SchedVar<A57LMAddrPred3,  A57VLDMOpsListCond_Upd.Writes[0-5]>,
   SchedVar<A57LMAddrPred4,  A57VLDMOpsListCond_Upd.Writes[0-7]>,
   SchedVar<A57LMAddrPred5,  A57VLDMOpsListCond_Upd.Writes[0-9]>,
   SchedVar<A57LMAddrPred6,  A57VLDMOpsListCond_Upd.Writes[0-11]>,
   SchedVar<A57LMAddrPred7,  A57VLDMOpsListCond_Upd.Writes[0-13]>,
-  SchedVar<A57LMAddrPred8,  A57VLDMOpsListCond_Upd.Writes[0-15]>,
   SchedVar<NoSchedPred,     A57VLDMOpsListCond_Upd.Writes[0-15]>
 ]> { let Variadic=1; }
 
 def A57WriteVLDM_UPD : SchedWriteVariant<[
   SchedVar<IsPredicatedPred, [A57WriteVLDMcond_UPD]>,
   SchedVar<NoSchedPred,      [A57WriteVLDMuncond_UPD]>
 ]> { let Variadic=1; }
 

 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>;
 
 // --- 3.20 CRC ---
 def : InstRW<[A57Write_3cyc_1W], (instregex "^(t2)?CRC32")>;
 
 // -----------------------------------------------------------------------------
 // Common definitions
 def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
-def : SchedAlias<WriteALU, A57Write_1cyc_1I>;
+def : SchedAlias<WriteALU, CheckBranchForm<0, A57BranchForm<A57Write_1cyc_1I>>>;
 
 def : SchedAlias<WriteBr, A57Write_1cyc_1B>;
 def : SchedAlias<WriteBrL, A57Write_1cyc_1B_1I>;
 def : SchedAlias<WriteBrTbl, A57Write_1cyc_1B_1I>;
 def : SchedAlias<WritePreLd, A57Write_4cyc_1L>;
 
 def : SchedAlias<WriteLd, A57Write_4cyc_1L>;
 def : SchedAlias<WriteST, A57Write_1cyc_1S>;
 def : ReadAdvance<ReadALU, 0>;
 
 } // SchedModel = CortexA57Model
 

llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td

def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
                                                     let ResourceCycles = [17]; }
 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
                                                     let ResourceCycles = [18]; }
 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
                                                     let ResourceCycles = [19]; }
 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
                                                     let ResourceCycles = [20]; }
 def A57Write_1cyc_1B  : SchedWriteRes<[A57UnitB]> { let Latency = 1;  }
-def A57Write_1cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 1;  }
-def A57Write_2cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 2;  }
+def A57Write_1cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 1;
+                                                    let ResourceCycles = [1]; }
+def A57Write_2cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 2;
+                                                    let ResourceCycles = [1]; }
 def A57Write_3cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 3;  }
 def A57Write_1cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 1;  }
 def A57Write_2cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 2;  }
 def A57Write_3cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 3;  }
-def A57Write_2cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 2;  }
+def A57Write_2cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 2;
+                                                    let ResourceCycles = [1]; }
 def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
                                                     let ResourceCycles = [32]; }
 def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
                                                     let ResourceCycles = [32]; }
 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
                                                     let ResourceCycles = [35]; }
 def A57Write_3cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 3;  }
 def A57Write_3cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 3;  }

llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s

 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     0.50                        adc r1, r2, #15
-# CHECK-NEXT:  1      1     0.50                        adc pc, r2, #16
+# CHECK-NEXT:  2      3     1.00                        adc pc, r2, #16
 # CHECK-NEXT:  1      1     0.50                        adc r1, r2, #240
 # CHECK-NEXT:  1      1     0.50                        adc r1, r2, #3840
 # CHECK-NEXT:  1      1     0.50                        adc r1, r2, #61440
 # CHECK-NEXT:  1      1     0.50                        adc r1, r2, #983040
 # CHECK-NEXT:  1      1     0.50                        adc r1, r2, #15728640
 # CHECK-NEXT:  1      1     0.50                        adc r1, r2, #251658240
 # CHECK-NEXT:  1      1     0.50                        adc r1, r2, #-268435456
 # CHECK-NEXT:  1      1     0.50                        adc r1, r2, #-268435441
 # CHECK-NEXT:  1      1     0.50                        adc r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        adc r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        adcs  r1, r2, #3840
 # CHECK-NEXT:  1      1     0.50                        adcs  r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        adcseq  r1, r2, #3840
 # CHECK-NEXT:  1      1     0.50                        adceq r1, r2, #3840
 # CHECK-NEXT:  1      1     0.50                        adc r4, r5, r6
-# CHECK-NEXT:  1      1     0.50                        adc pc, r5, r6
+# CHECK-NEXT:  2      3     1.00                        adc pc, r5, r6
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, lsl #1
-# CHECK-NEXT:  1      2     1.00                        adc pc, r5, r6, lsl #4
+# CHECK-NEXT:  2      4     1.00                        adc pc, r5, r6, lsl #4
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, lsl #31
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, lsr #1
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, lsr #31
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, lsr #32
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, asr #1
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, asr #31
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, asr #32
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, ror #1
-# CHECK-NEXT:  1      2     1.00                        adc pc, r5, r6, ror #2
+# CHECK-NEXT:  2      4     1.00                        adc pc, r5, r6, ror #2
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, ror #31
 # CHECK-NEXT:  1      2     1.00                        adc r6, r7, r8, lsl r9
 # CHECK-NEXT:  1      2     1.00                        adc r6, r7, r8, lsr r9
 # CHECK-NEXT:  1      2     1.00                        adc r6, r7, r8, asr r9
 # CHECK-NEXT:  1      2     1.00                        adc r6, r7, r8, ror r9
 # CHECK-NEXT:  1      2     1.00                        adc r4, r5, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        adc r5, r5, r6
 # CHECK-NEXT:  1      2     1.00                        adc r4, r4, r5, lsl #1

 # CHECK-NEXT:  1      2     1.00                        add r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        add r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        add r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        add r6, r6, r7, ror r9
 # CHECK-NEXT:  1      2     1.00                        add r4, r4, r5, rrx
 # CHECK-NEXT:  1      1     0.50                        adds  r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        adds  r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        adr r2, #3
-# CHECK-NEXT:  1      1     0.50                        and pc, pc, #8
+# CHECK-NEXT:  2      3     1.00                        and pc, pc, #8
 # CHECK-NEXT:  1      1     0.50                        sub r2, pc, #3
 # CHECK-NEXT:  1      1     0.50                        sub r1, pc, #0
-# CHECK-NEXT:  1      1     0.50                        sub pc, r2, #8
+# CHECK-NEXT:  2      3     1.00                        sub pc, r2, #8
 # CHECK-NEXT:  1      1     0.50                        sub r1, pc, #301989888
 # CHECK-NEXT:  1      1     0.50                        adr r1, #301989888
 # CHECK-NEXT:  1      1     0.50                        and r10, r1, #15
 # CHECK-NEXT:  1      1     0.50                        and r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        and r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        and r10, r1, r6
 # CHECK-NEXT:  1      2     1.00                        and r10, r1, r6, lsl #10
 # CHECK-NEXT:  1      2     1.00                        and r10, r1, r6, lsr #10

 # CHECK-NEXT:  1      2     1.00                        bic r10, r1, r6, asr #10
 # CHECK-NEXT:  1      2     1.00                        bic r10, r1, r6, ror #10
 # CHECK-NEXT:  1      2     1.00                        bic r6, r7, r8, lsl r2
 # CHECK-NEXT:  1      2     1.00                        bic r6, r7, r8, lsr r2
 # CHECK-NEXT:  1      2     1.00                        bic r6, r7, r8, asr r2
 # CHECK-NEXT:  1      2     1.00                        bic r6, r7, r8, ror r2
 # CHECK-NEXT:  1      2     1.00                        bic r10, r1, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        bic r1, r1, #15
-# CHECK-NEXT:  1      1     0.50                        bic pc, r1, #15
+# CHECK-NEXT:  2      3     1.00                        bic pc, r1, #15
 # CHECK-NEXT:  1      1     0.50                        bic r10, r10, r1
 # CHECK-NEXT:  1      2     1.00                        bic r10, r10, r1, lsl #10
 # CHECK-NEXT:  1      2     1.00                        bic r10, r10, r1, lsr #10
 # CHECK-NEXT:  1      2     1.00                        bic r10, r10, r1, lsr #10
 # CHECK-NEXT:  1      2     1.00                        bic r10, r10, r1, asr #10
 # CHECK-NEXT:  1      2     1.00                        bic r10, r10, r1, ror #10
 # CHECK-NEXT:  1      2     1.00                        bic r6, r6, r7, lsl r2
 # CHECK-NEXT:  1      2     1.00                        bic r6, r6, r7, lsr r2

 # CHECK-NEXT:  0      0     0.00    *      *      U     dsb #0xc
 # CHECK-NEXT:  0      0     0.00    *      *      U     dsb ld
 # CHECK-NEXT:  0      0     0.00    *      *      U     dsb st
 # CHECK-NEXT:  0      0     0.00    *      *      U     dsb sy
 # CHECK-NEXT:  1      1     0.50                        eor r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        eor r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        eor r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        eor r4, r5, r6
-# CHECK-NEXT:  1      1     0.50                        eor pc, r5, r6
+# CHECK-NEXT:  2      3     1.00                        eor pc, r5, r6
 # CHECK-NEXT:  1      2     1.00                        eor r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        eor r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        eor r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        eor r4, r5, r6, asr #5
 # CHECK-NEXT:  1      2     1.00                        eor r4, r5, r6, ror #5
 # CHECK-NEXT:  1      2     1.00                        eor r6, r7, r8, lsl r9
 # CHECK-NEXT:  1      2     1.00                        eor r6, r7, r8, lsr r9
 # CHECK-NEXT:  1      2     1.00                        eor r6, r7, r8, asr r9

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT: 8.00   144.50 144.50 53.00  524.00 12.00   -      -
+# CHECK-NEXT: 16.00  144.50 144.50 53.00  524.00 12.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #15
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc pc, r2, #16
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     adc pc, r2, #16
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #240
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #3840
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #983040
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #15728640
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #251658240
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #-268435456
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #-268435441
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r7, r8, #-2147483638
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adcs  r1, r2, #3840
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adcs  r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adcseq  r1, r2, #3840
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adceq r1, r2, #3840
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r4, r5, r6
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc pc, r5, r6
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     adc pc, r5, r6
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, lsl #1
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc pc, r5, r6, lsl #4
+# CHECK-NEXT: 1.00    -      -      -     1.00    -      -      -     adc pc, r5, r6, lsl #4
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, lsl #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, lsr #1
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, lsr #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, lsr #32
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, asr #1
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, asr #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, asr #32
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, ror #1
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc pc, r5, r6, ror #2
+# CHECK-NEXT: 1.00    -      -      -     1.00    -      -      -     adc pc, r5, r6, ror #2
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, ror #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r6, r7, r8, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r6, r7, r8, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r6, r7, r8, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r6, r7, r8, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r5, r6, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r5, r5, r6
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     adc r4, r4, r5, lsl #1

 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add r6, r6, r7, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add r6, r6, r7, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add r6, r6, r7, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add r6, r6, r7, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     add r4, r4, r5, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adds  r7, r8, #-2147483638
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adds  r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adr r2, #3
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and pc, pc, #8
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     and pc, pc, #8
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub r2, pc, #3
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub r1, pc, #0
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub pc, r2, #8
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     sub pc, r2, #8
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sub r1, pc, #301989888
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adr r1, #301989888
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and r10, r1, #15
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and r7, r8, #-2147483638
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     and r10, r1, r6
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and r10, r1, r6, lsl #10
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     and r10, r1, r6, lsr #10

 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r10, r1, r6, asr #10
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r10, r1, r6, ror #10
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r6, r7, r8, lsl r2
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r6, r7, r8, lsr r2
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r6, r7, r8, asr r2
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r6, r7, r8, ror r2
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r10, r1, r6, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     bic r1, r1, #15
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     bic pc, r1, #15
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     bic pc, r1, #15
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     bic r10, r10, r1
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r10, r10, r1, lsl #10
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r10, r10, r1, lsr #10
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r10, r10, r1, lsr #10
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r10, r10, r1, asr #10
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r10, r10, r1, ror #10
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r6, r6, r7, lsl r2
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     bic r6, r6, r7, lsr r2

 # CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb #0xc
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb ld
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb st
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     dsb sy
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor r4, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor r7, r8, #-2147483638
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor r4, r5, r6
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     eor pc, r5, r6
+# CHECK-NEXT: 1.00   0.50   0.50    -      -      -      -      -     eor pc, r5, r6
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r4, r5, r6, lsl #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r4, r5, r6, asr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r4, r5, r6, ror #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r6, r7, r8, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r6, r7, r8, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     eor r6, r7, r8, asr r9

llvm/utils/TableGen/CodeGenSchedule.cpp

public:
 
   void substituteVariants(const PredTransition &Trans);
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 
 private:
-  bool mutuallyExclusive(Record *PredDef, ArrayRef<PredCheck> Term);
+  bool mutuallyExclusive(Record *PredDef, ArrayRef<Record *> Preds,
+                         ArrayRef<PredCheck> Term);
   void getIntersectingVariants(
     const CodeGenSchedRW &SchedRW, unsigned TransIdx,
     std::vector<TransVariant> &IntersectingVariants);
   void pushVariant(const TransVariant &VInfo, bool IsRead);
 };
 
 } // end anonymous namespace
 
 // Return true if this predicate is mutually exclusive with a PredTerm. This
 // degenerates into checking if the predicate is mutually exclusive with any
 // predicate in the Term's conjunction.
 //
 // All predicates associated with a given SchedRW are considered mutually
 // exclusive. This should work even if the conditions expressed by the
 // predicates are not exclusive because the predicates for a given SchedWrite
 // are always checked in the order they are defined in the .td file. Later
 // conditions implicitly negate any prior condition.
 bool PredTransitions::mutuallyExclusive(Record *PredDef,
+                                        ArrayRef<Record *> Preds,
                                         ArrayRef<PredCheck> Term) {
   for (const PredCheck &PC: Term) {
     if (PC.Predicate == PredDef)
       return false;
 
     const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(PC.RWIdx, PC.IsRead);
     assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant");
     RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");
     if (any_of(Variants, [PredDef](const Record *R) {
           return R->getValueAsDef("Predicate") == PredDef;
-        }))
+        })) {
+      // To check if PredDef is mutually exclusive with PC we also need to
+      // check that PC.Predicate is exclusive with all predicates from variant
+      // we're expanding. Consider following RW sequence with two variants
+      // (1 & 2), where A, B and C are predicates from corresponding SchedVars:
+      //
+      // 1:A/B - 2:C/B
+      //
+      // Here C is not mutually exclusive with variant (1), because A doesn't
+      // exist in variant (2). This means we have possible transitions from A
+      // to C and from A to B, and fully expanded sequence would look like:
+      //
+      // if (A & C) return ...;
+      // if (A & B) return ...;
+      // if (B) return ...;
+      //
+      // Now let's consider another sequence:
+      //
+      // 1:A/B - 2:A/B
+      //
+      // Here A in variant (2) is mutually exclusive with variant (1), because
+      // A also exists in (2). This means A->B transition is impossible and
+      // expanded sequence would look like:
+      //
+      // if (A) return ...;
+      // if (B) return ...;
+      if (!count(Preds, PC.Predicate))
+        continue;
       return true;
     }
+  }
   return false;
 }
 
 static bool hasAliasedVariants(const CodeGenSchedRW &RW,
                                CodeGenSchedModels &SchedModels) {
   if (RW.HasVariants)
     return true;
 
for (const PredTransition &PTI : Transitions) {
     for (const SmallVectorImpl<unsigned> &RSI : PTI.ReadSequences)
       for (unsigned RI : RSI)
         if (hasAliasedVariants(SchedModels.getSchedRead(RI), SchedModels))
           return true;
   }
   return false;
 }
 
+static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants) {
+  std::vector<Record *> Preds;
+  for (auto &Variant : Variants) {
+    assert(Variant.VarOrSeqDef->isSubClassOf("SchedVar"));
+    Preds.push_back(Variant.VarOrSeqDef->getValueAsDef("Predicate"));
+  }
+  return Preds;
+}
+
 // Populate IntersectingVariants with any variants or aliased sequences of the
 // given SchedRW whose processor indices and predicates are not mutually
 // exclusive with the given transition.
 void PredTransitions::getIntersectingVariants(
   const CodeGenSchedRW &SchedRW, unsigned TransIdx,
   std::vector<TransVariant> &IntersectingVariants) {
 
   bool GenericRW = false;
if (AliasRW.HasVariants) {
       for (Record *VD : VarDefs)
         Variants.emplace_back(VD, AliasRW.Index, AliasProcIdx, 0);
     }
     if (AliasRW.IsSequence)
       Variants.emplace_back(AliasRW.TheDef, SchedRW.Index, AliasProcIdx, 0);
     if (AliasProcIdx == 0)
       GenericRW = true;
   }
+  std::vector<Record *> AllPreds = getAllPredicates(Variants);
   for (TransVariant &Variant : Variants) {
     // Don't expand variants if the processor models don't intersect.
     // A zero processor index means any processor.
     SmallVectorImpl<unsigned> &ProcIndices = TransVec[TransIdx].ProcIndices;
     if (ProcIndices[0] && Variant.ProcIdx) {
       unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(),
                                 Variant.ProcIdx);
       if (!Cnt)
         continue;
       if (Cnt > 1) {
         const CodeGenProcModel &PM =
           *(SchedModels.procModelBegin() + Variant.ProcIdx);
         PrintFatalError(Variant.VarOrSeqDef->getLoc(),
                         "Multiple variants defined for processor " +
                         PM.ModelName +
                         " Ensure only one SchedAlias exists per RW.");
       }
     }
-    if (Variant.VarOrSeqDef->isSubClassOf("SchedVar")) {
-      Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate");
-      if (mutuallyExclusive(PredDef, TransVec[TransIdx].PredTerm))
-        continue;
-    }
+    if (mutuallyExclusive(PredDef, AllPreds, TransVec[TransIdx].PredTerm))
+
     if (IntersectingVariants.empty()) {
       // The first variant builds on the existing transition.
       Variant.TransVecIdx = TransIdx;
       IntersectingVariants.push_back(Variant);
     }
     else {
       // Push another copy of the current transition for more variants.
       Variant.TransVecIdx = TransVec.size();

llvm/utils/TableGen/SubtargetEmitter.cpp

static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
   llvm::sort(Prologs, LessRecord());
   for (Record *P : Prologs)
     Stream << P->getValueAsString("Code") << '\n';
 
   Stream.flush();
   OS << Buffer;
 }
 
+static bool isTruePredicate(const Record *Rec) {
+  return Rec->isSubClassOf("MCSchedPredicate") &&
+         Rec->getValueAsDef("Pred")->isSubClassOf("MCTrue");
+}
+
 static void emitPredicates(const CodeGenSchedTransition &T,
                            const CodeGenSchedClass &SC, PredicateExpander &PE,
                            raw_ostream &OS) {
   std::string Buffer;
   raw_string_ostream SS(Buffer);
 
-  auto IsTruePredicate = [](const Record *Rec) {
-    return Rec->isSubClassOf("MCSchedPredicate") &&
-           Rec->getValueAsDef("Pred")->isSubClassOf("MCTrue");
-  };
-
   // If not all predicates are MCTrue, then we need an if-stmt.
   unsigned NumNonTruePreds =
-      T.PredTerm.size() - count_if(T.PredTerm, IsTruePredicate);
+      T.PredTerm.size() - count_if(T.PredTerm, isTruePredicate);
 
   SS.indent(PE.getIndentLevel() * 2);
 
   if (NumNonTruePreds) {
     bool FirstNonTruePredicate = true;
     SS << "if (";
 
     PE.setIndentLevel(PE.getIndentLevel() + 2);
 
     for (const Record *Rec : T.PredTerm) {
       // Skip predicates that evaluate to "true".
-      if (IsTruePredicate(Rec))
+      if (isTruePredicate(Rec))
         continue;
 
       if (FirstNonTruePredicate) {
         FirstNonTruePredicate = false;
       } else {
         SS << "\n";
         SS.indent(PE.getIndentLevel() * 2);
         SS << "&& ";
for (const CodeGenSchedTransition &T : SC.Transitions) {
     IdxVec PI;
     std::set_union(T.ProcIndices.begin(), T.ProcIndices.end(),
                    ProcIndices.begin(), ProcIndices.end(),
                    std::back_inserter(PI));
     ProcIndices.swap(PI);
   }
 }
 
+static bool isAlwaysTrue(const CodeGenSchedTransition &T) {
+  return llvm::all_of(T.PredTerm,
+                      [](const Record *R) { return isTruePredicate(R); });
+}
+
 void SubtargetEmitter::emitSchedModelHelpersImpl(
     raw_ostream &OS, bool OnlyExpandMCInstPredicates) {
   IdxVec VariantClasses;
   collectVariantClasses(SchedModels, VariantClasses,
                         OnlyExpandMCInstPredicates);
 
   if (VariantClasses.empty()) {
     emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates);
for (unsigned PI : ProcIndices) {
         OS << (OnlyExpandMCInstPredicates
                    ? "if (CPUID == "
                    : "if (SchedModel->getProcessorID() == ");
         OS << PI << ") ";
         OS << "{ // " << (SchedModels.procModelBegin() + PI)->ModelName << '\n';
       }
 
       // Now emit transitions associated with processor PI.
+      const CodeGenSchedTransition *FinalT = nullptr;
       for (const CodeGenSchedTransition &T : SC.Transitions) {
         if (PI != 0 && !count(T.ProcIndices, PI))
           continue;
 
         // Emit only transitions based on MCSchedPredicate, if it's the case.
         // At least the transition specified by NoSchedPred is emitted,
         // which becomes the default transition for those variants otherwise
         // not based on MCSchedPredicate.
         // FIXME: preferably, llvm-mca should instead assume a reasonable
         // default when a variant transition is not based on MCSchedPredicate
         // for a given processor.
         if (OnlyExpandMCInstPredicates && !hasMCSchedPredicates(T))
           continue;
 
+        // If transition is folded to 'return X' it should be the last one.
+        if (isAlwaysTrue(T)) {
+          FinalT = &T;
+          continue;
+        }
         PE.setIndentLevel(3);
         emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS);
       }
+      if (FinalT)
+        emitPredicates(*FinalT, SchedModels.getSchedClass(FinalT->ToClassIdx),
+                       PE, OS);
 
       OS << "    }\n";
 
       if (PI == 0)
         break;
     }
 
     if (SC.isInferred())