[NFC] Use [MC]Register for Hexagon target

[mtrofin]

Maybe the popular RegisterRef can be moved to Register.h? Would that complicate this patch?

llvm/lib/Target/Hexagon/BitTracker.h

134

are Reg and Pos const?

147

Are Reg and Sub const? marking them so would help readability, and also ensure we don't accidentally yank the initializer in the ctor.

llvm/lib/Target/Hexagon/HexagonBlockRanges.h

35

weird... there was one of these earlier. Not sure if hoisting it in a common .h may make sense, but otherwise the comments are the same (const-ing Reg and Sub)

llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp

86–87

seems like a popular design

llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp

191–192

4th RegisterRef.

Sub is probably unsigned?

llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp

51–52

5th RegisterRef :)

[gjain]

I'd definitely prefer not cleaning up RegisterRef as part of this patch. The register/sub tuple pattern is present throughout the code and needs an independant clean-up. Otherwise we risk this not being a NFC.

Regarding const usage, this will delete the implicit copy constructor. Given the earlier statement that those classes need an independant clean-up, are you okay punting on this?

llvm/lib/Target/Hexagon/BitTracker.h

134

See comments.

llvm/lib/Target/Hexagon/HexagonBlockRanges.h

35

Yeah this was very odd and requires clean-up

llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp

86–87

See comments.

[gjain]

Fix Sub to be unsigned

[mtrofin]

In D91160#2387274, @gjain wrote:

I'd definitely prefer not cleaning up RegisterRef as part of this patch. The register/sub tuple pattern is present throughout the code and needs an independant clean-up. Otherwise we risk this not being a NFC.

Regarding const usage, this will delete the implicit copy constructor. Given the earlier statement that those classes need an independant clean-up, are you okay punting on this?

Yes, but could you add a FIXME above each, with the same text - so we can fish them out easily afterwards.

[mtrofin]

lgtm

llvm/lib/Target/Hexagon/BitTracker.h

struct BitTracker {
   void visit(const MachineInstr &MI);
 
   void print_cells(raw_ostream &OS) const;
 
 private:
   void visitPHI(const MachineInstr &PI);
   void visitNonBranch(const MachineInstr &MI);
   void visitBranchesFrom(const MachineInstr &BI);
-  void visitUsesOf(unsigned Reg);
+  void visitUsesOf(Register Reg);
 
   using CFGEdge = std::pair<int, int>;
   using EdgeSetType = std::set<CFGEdge>;
   using InstrSetType = std::set<const MachineInstr *>;
   using EdgeQueueType = std::queue<CFGEdge>;
 
   // Priority queue of instructions using modified registers, ordered by
   // their relative position in a basic block.

 struct BitTracker::BitRef {
   BitRef(unsigned R = 0, uint16_t P = 0) : Reg(R), Pos(P) {}
 
   bool operator== (const BitRef &BR) const {
     // If Reg is 0, disregard Pos.
     return Reg == BR.Reg && (Reg == 0 || Pos == BR.Pos);
   }
 
-  unsigned Reg;
+  Register Reg;
   uint16_t Pos;
 };
 
 // Abstraction of a register reference in MachineOperand.  It contains the
 // register number and the subregister index.
+// FIXME: Consolidate duplicate definitions of RegisterRef
 struct BitTracker::RegisterRef {
-  RegisterRef(unsigned R = 0, unsigned S = 0)
-    : Reg(R), Sub(S) {}
+  RegisterRef(Register R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
   RegisterRef(const MachineOperand &MO)
       : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
 
-  unsigned Reg, Sub;
+  Register Reg;
+  unsigned Sub;
 };
 
 // Value that a single bit can take.  This is outside of the context of
 // any register, it is more of an abstraction of the two-element set of
 // possible bit values.  One extension here is the "Ref" type, which
 // indicates that this bit takes the same value as the bit described by
 // RefInfo.
 struct BitTracker::BitValue {
const BitValue &operator[](uint16_t BitN) const {
     assert(BitN < Bits.size());
     return Bits[BitN];
   }
   BitValue &operator[](uint16_t BitN) {
     assert(BitN < Bits.size());
     return Bits[BitN];
   }
 
-  bool meet(const RegisterCell &RC, unsigned SelfR);
+  bool meet(const RegisterCell &RC, Register SelfR);
   RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
   RegisterCell extract(const BitMask &M) const;  // Returns a new cell.
   RegisterCell &rol(uint16_t Sh);    // Rotate left.
   RegisterCell &fill(uint16_t B, uint16_t E, const BitValue &V);
   RegisterCell &cat(const RegisterCell &RC);  // Concatenate.
   uint16_t cl(bool B) const;
   uint16_t ct(bool B) const;
 
struct BitTracker::MachineEvaluator {
 
   // Return a sub-register mask that indicates which bits in Reg belong
   // to the subregister Sub. These bits are assumed to be contiguous in
   // the super-register, and have the same ordering in the sub-register
   // as in the super-register. It is valid to call this function with
   // Sub == 0, in this case, the function should return a mask that spans
   // the entire register Reg (which is what the default implementation
   // does).
-  virtual BitMask mask(unsigned Reg, unsigned Sub) const;
+  virtual BitMask mask(Register Reg, unsigned Sub) const;
   // Indicate whether a given register class should be tracked.
   virtual bool track(const TargetRegisterClass *RC) const { return true; }
   // Evaluate a non-branching machine instruction, given the cell map with
   // the input values. Place the results in the Outputs map. Return "true"
   // if evaluation succeeded, "false" otherwise.
   virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
                         CellMapType &Outputs) const;
   // Evaluate a branch, given the cell map with the input values. Fill out
   // a list of all possible branch targets and indicate (through a flag)
   // whether the branch could fall-through. Return "true" if this information
   // has been successfully computed, "false" otherwise.
   virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
                         BranchTargetList &Targets, bool &FallsThru) const = 0;
   // Given a register class RC, return a register class that should be assumed
   // when a register from class RC is used with a subregister of index Idx.
   virtual const TargetRegisterClass&
   composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const {
     if (Idx == 0)
       return RC;
     llvm_unreachable("Unimplemented composeWithSubRegIndex");
   }
   // Return the size in bits of the physical register Reg.
-  virtual uint16_t getPhysRegBitWidth(unsigned Reg) const;
+  virtual uint16_t getPhysRegBitWidth(Register Reg) const;
 
   const TargetRegisterInfo &TRI;
   MachineRegisterInfo &MRI;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H

llvm/lib/Target/Hexagon/BitTracker.cpp

 }
 
 // If we were allowed to update a cell for a part of a register, the meet
 // operation would need to be parametrized by the register number and the
 // exact part of the register, so that the computer BitRefs correspond to
 // the actual bits of the "self" register.
 // While this cannot happen in the current implementation, I'm not sure
 // if this should be ruled out in the future.
-bool BT::RegisterCell::meet(const RegisterCell &RC, unsigned SelfR) {
+bool BT::RegisterCell::meet(const RegisterCell &RC, Register SelfR) {
   // An example when "meet" can be invoked with SelfR == 0 is a phi node
   // with a physical register as an operand.
-  assert(SelfR == 0 || Register::isVirtualRegister(SelfR));
+  assert(SelfR == 0 || SelfR.isVirtual());
   bool Changed = false;
   for (uint16_t i = 0, n = Bits.size(); i < n; ++i) {
     const BitValue &RCV = RC[i];
     Changed |= Bits[i].meet(RCV, BitRef(SelfR, i));
   }
   return Changed;
 }
 
uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {
   // The general problem is with finding a register class that corresponds
   // to a given reference reg:sub. There can be several such classes, and
   // since we only care about the register size, it does not matter which
   // such class we would find.
   // The easiest way to accomplish what we want is to
   // 1. find a physical register PhysR from the same class as RR.Reg,
   // 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
   // 3. find a register class that contains PhysS.
-  if (Register::isVirtualRegister(RR.Reg)) {
+  if (RR.Reg.isVirtual()) {
     const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
     return TRI.getRegSizeInBits(VC);
   }
-  assert(Register::isPhysicalRegister(RR.Reg));
+  assert(RR.Reg.isPhysical());
   Register PhysR =
       (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub);
   return getPhysRegBitWidth(PhysR);
 }
 
 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR,
       const CellMapType &M) const {
   uint16_t BW = getRegBitWidth(RR);
 
   // Physical registers are assumed to be present in the map with an unknown
   // value. Don't actually insert anything in the map, just return the cell.
-  if (Register::isPhysicalRegister(RR.Reg))
+  if (RR.Reg.isPhysical())
     return RegisterCell::self(0, BW);
 
-  assert(Register::isVirtualRegister(RR.Reg));
+  assert(RR.Reg.isVirtual());
   // For virtual registers that belong to a class that is not tracked,
   // generate an "unknown" value as well.
   const TargetRegisterClass *C = MRI.getRegClass(RR.Reg);
   if (!track(C))
     return RegisterCell::self(0, BW);
 
   CellMapType::const_iterator F = M.find(RR.Reg);
   if (F != M.end()) {
     if (!RR.Sub)
       return F->second;
     BitMask M = mask(RR.Reg, RR.Sub);
     return F->second.extract(M);
   }
   // If not found, create a "top" entry, but do not insert it in the map.
   return RegisterCell::top(BW);
 }
 
 void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC,
       CellMapType &M) const {
   // While updating the cell map can be done in a meaningful way for
   // a part of a register, it makes little sense to implement it as the
   // SSA representation would never contain such "partial definitions".
-  if (!Register::isVirtualRegister(RR.Reg))
+  if (!RR.Reg.isVirtual())
     return;
   assert(RR.Sub == 0 && "Unexpected sub-register in definition");
   // Eliminate all ref-to-reg-0 bit values: replace them with "self".
   M[RR.Reg] = RC.regify(RR.Reg);
 }
 
 // Check if the cell represents a compile-time integer value.
 bool BT::MachineEvaluator::isInt(const RegisterCell &A) const {
BT::RegisterCell BT::MachineEvaluator::eINS(const RegisterCell &A1,
   assert(AtN < W1 && AtN+W2 <= W1);
   // Copy bits from A1, insert A2 at position AtN.
   RegisterCell Res = RegisterCell::ref(A1);
   if (W2 > 0)
     Res.insert(RegisterCell::ref(A2), BT::BitMask(AtN, AtN+W2-1));
   return Res;
 }
 
-BT::BitMask BT::MachineEvaluator::mask(unsigned Reg, unsigned Sub) const {
+BT::BitMask BT::MachineEvaluator::mask(Register Reg, unsigned Sub) const {
   assert(Sub == 0 && "Generic BitTracker::mask called for Sub != 0");
   uint16_t W = getRegBitWidth(Reg);
   assert(W > 0 && "Cannot generate mask for empty register");
   return BitMask(0, W-1);
 }
 
-uint16_t BT::MachineEvaluator::getPhysRegBitWidth(unsigned Reg) const {
-  assert(Register::isPhysicalRegister(Reg));
+uint16_t BT::MachineEvaluator::getPhysRegBitWidth(Register Reg) const {
+  assert(Reg.isPhysical());
   const TargetRegisterClass &PC = *TRI.getMinimalPhysRegClass(Reg);
   return TRI.getRegSizeInBits(PC);
 }
 
 bool BT::MachineEvaluator::evaluate(const MachineInstr &MI,
                                     const CellMapType &Inputs,
                                     CellMapType &Outputs) const {
   unsigned Opc = MI.getOpcode();
void BT::visitNonBranch(const MachineInstr &MI) {
   // Iterate over all definitions of the instruction, and update the
   // cells accordingly.
   for (const MachineOperand &MO : MI.operands()) {
     // Visit register defs only.
     if (!MO.isReg() || !MO.isDef())
       continue;
     RegisterRef RD(MO);
     assert(RD.Sub == 0 && "Unexpected sub-register in definition");
-    if (!Register::isVirtualRegister(RD.Reg))
+    if (!RD.Reg.isVirtual())
       continue;
 
     bool Changed = false;
     if (!Eval || ResMap.count(RD.Reg) == 0) {
       // Set to "ref" (aka "bottom").
       uint16_t DefBW = ME.getRegBitWidth(RD);
       RegisterCell RefC = RegisterCell::self(RD.Reg, DefBW);
       if (RefC != ME.getCell(RD, Map)) {
if (!DefaultToAll) {
     for (const MachineBasicBlock *SB : B.successors())
       Targets.insert(SB);
   }
 
   for (const MachineBasicBlock *TB : Targets)
     FlowQ.push(CFGEdge(ThisN, TB->getNumber()));
 }
 
-void BT::visitUsesOf(unsigned Reg) {
+void BT::visitUsesOf(Register Reg) {
   if (Trace)
     dbgs() << "queuing uses of modified reg " << printReg(Reg, &ME.TRI)
            << " cell: " << ME.getCell(Reg, Map) << '\n';
 
   for (MachineInstr &UseI : MRI.use_nodbg_instructions(Reg))
     UseQ.push(&UseI);
 }
 

llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp

public:
     static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs);
     static void getInstrUses(const MachineInstr &MI, RegisterSet &Uses);
     static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1,
         const BitTracker::RegisterCell &RC2, uint16_t B2, uint16_t W);
     static bool isZero(const BitTracker::RegisterCell &RC, uint16_t B,
         uint16_t W);
     static bool getConst(const BitTracker::RegisterCell &RC, uint16_t B,
         uint16_t W, uint64_t &U);
-    static bool replaceReg(unsigned OldR, unsigned NewR,
+    static bool replaceReg(Register OldR, Register NewR,
                            MachineRegisterInfo &MRI);
     static bool getSubregMask(const BitTracker::RegisterRef &RR,
         unsigned &Begin, unsigned &Width, MachineRegisterInfo &MRI);
-    static bool replaceRegWithSub(unsigned OldR, unsigned NewR,
+    static bool replaceRegWithSub(Register OldR, Register NewR, unsigned NewSR,
+                                  MachineRegisterInfo &MRI);
+    static bool replaceSubWithSub(Register OldR, unsigned OldSR, Register NewR,
                                   unsigned NewSR, MachineRegisterInfo &MRI);
-    static bool replaceSubWithSub(unsigned OldR, unsigned OldSR,
-        unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI);
     static bool parseRegSequence(const MachineInstr &I,
         BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH,
         const MachineRegisterInfo &MRI);
 
     static bool getUsedBitsInStore(unsigned Opc, BitVector &Bits,
         uint16_t Begin);
     static bool getUsedBits(unsigned Opc, unsigned OpN, BitVector &Bits,
         uint16_t Begin, const HexagonInstrInfo &HII);

 // Utility functions:
 //
 void HexagonBitSimplify::getInstrDefs(const MachineInstr &MI,
       RegisterSet &Defs) {
   for (auto &Op : MI.operands()) {
     if (!Op.isReg() || !Op.isDef())
       continue;
     Register R = Op.getReg();
-    if (!Register::isVirtualRegister(R))
+    if (!R.isVirtual())
       continue;
     Defs.insert(R);
   }
 }
 
 void HexagonBitSimplify::getInstrUses(const MachineInstr &MI,
       RegisterSet &Uses) {
   for (auto &Op : MI.operands()) {
     if (!Op.isReg() || !Op.isUse())
       continue;
     Register R = Op.getReg();
-    if (!Register::isVirtualRegister(R))
+    if (!R.isVirtual())
       continue;
     Uses.insert(R);
   }
 }
 
 // Check if all the bits in range [B, E) in both cells are equal.
 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1,
       uint16_t B1, const BitTracker::RegisterCell &RC2, uint16_t B2,
if (BV.is(1))
       T |= 1;
     else if (!BV.is(0))
       return false;
   }
   U = T;
   return true;
 }
 
-bool HexagonBitSimplify::replaceReg(unsigned OldR, unsigned NewR,
+bool HexagonBitSimplify::replaceReg(Register OldR, Register NewR,
                                     MachineRegisterInfo &MRI) {
-  if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
+  if (!OldR.isVirtual() || !NewR.isVirtual())
     return false;
   auto Begin = MRI.use_begin(OldR), End = MRI.use_end();
   decltype(End) NextI;
   for (auto I = Begin; I != End; I = NextI) {
     NextI = std::next(I);
     I->setReg(NewR);
   }
   return Begin != End;
 }
 
-bool HexagonBitSimplify::replaceRegWithSub(unsigned OldR, unsigned NewR,
-      unsigned NewSR, MachineRegisterInfo &MRI) {
-  if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
+bool HexagonBitSimplify::replaceRegWithSub(Register OldR, Register NewR,
+                                           unsigned NewSR,
+                                           MachineRegisterInfo &MRI) {
+  if (!OldR.isVirtual() || !NewR.isVirtual())
     return false;
   if (hasTiedUse(OldR, MRI, NewSR))
     return false;
   auto Begin = MRI.use_begin(OldR), End = MRI.use_end();
   decltype(End) NextI;
   for (auto I = Begin; I != End; I = NextI) {
     NextI = std::next(I);
     I->setReg(NewR);
     I->setSubReg(NewSR);
   }
   return Begin != End;
 }
 
-bool HexagonBitSimplify::replaceSubWithSub(unsigned OldR, unsigned OldSR,
-      unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI) {
-  if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
+bool HexagonBitSimplify::replaceSubWithSub(Register OldR, unsigned OldSR,
+                                           Register NewR, unsigned NewSR,
+                                           MachineRegisterInfo &MRI) {
+  if (!OldR.isVirtual() || !NewR.isVirtual())
     return false;
   if (OldSR != NewSR && hasTiedUse(OldR, MRI, NewSR))
     return false;
   auto Begin = MRI.use_begin(OldR), End = MRI.use_end();
   decltype(End) NextI;
   for (auto I = Begin; I != End; I = NextI) {
     NextI = std::next(I);
     if (I->getSubReg() != OldSR)
bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN,
   return false;
 }
 
 // Calculate the register class that matches Reg:Sub. For example, if
 // %1 is a double register, then %1:isub_hi would match the "int"
 // register class.
 const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
       const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
-  if (!Register::isVirtualRegister(RR.Reg))
+  if (!RR.Reg.isVirtual())
     return nullptr;
   auto *RC = MRI.getRegClass(RR.Reg);
   if (RR.Sub == 0)
     return RC;
   auto &HRI = static_cast<const HexagonRegisterInfo&>(
                   *MRI.getTargetRegisterInfo());
 
   auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {

 }
 
 // Check if RD could be replaced with RS at any possible use of RD.
 // For example a predicate register cannot be replaced with a integer
 // register, but a 64-bit register with a subregister can be replaced
 // with a 32-bit register.
 bool HexagonBitSimplify::isTransparentCopy(const BitTracker::RegisterRef &RD,
       const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) {
-  if (!Register::isVirtualRegister(RD.Reg) ||
-      !Register::isVirtualRegister(RS.Reg))
+  if (!RD.Reg.isVirtual() || !RS.Reg.isVirtual())
     return false;
   // Return false if one (or both) classes are nullptr.
   auto *DRC = getFinalVRegClass(RD, MRI);
   if (!DRC)
     return false;
 
   return DRC == getFinalVRegClass(RS, MRI);
 }
if (!MI->isPHI() && !MI->isSafeToMove(nullptr, Store))
       continue;
 
     bool AllDead = true;
     SmallVector<unsigned,2> Regs;
     for (auto &Op : MI->operands()) {
       if (!Op.isReg() || !Op.isDef())
         continue;
       Register R = Op.getReg();
-      if (!Register::isVirtualRegister(R) || !isDead(R)) {
+      if (!R.isVirtual() || !isDead(R)) {
         AllDead = false;
         break;
       }
       Regs.push_back(R);
     }
     if (!AllDead)
       continue;
 
for (unsigned i = 0; i < Pending.size(); ++i) {
     for (auto I = MRI.use_begin(R), E = MRI.use_end(); I != E; ++I) {
       BitTracker::RegisterRef UR = *I;
       unsigned B, W;
       if (!HBS::getSubregMask(UR, B, W, MRI))
         return false;
       MachineInstr &UseI = *I->getParent();
       if (UseI.isPHI() || UseI.isCopy()) {
         Register DefR = UseI.getOperand(0).getReg();
-        if (!Register::isVirtualRegister(DefR))
+        if (!DefR.isVirtual())
           return false;
         Pending.push_back(DefR);
       } else {
         if (!computeUsedBits(UseI, I.getOperandNo(), Used, B))
           return false;
       }
     }
   }
public:
     ConstGeneration(BitTracker &bt, const HexagonInstrInfo &hii,
         MachineRegisterInfo &mri)
       : Transformation(true), HII(hii), MRI(mri), BT(bt) {}
 
     bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override;
     static bool isTfrConst(const MachineInstr &MI);
 
   private:
-    unsigned genTfrConst(const TargetRegisterClass *RC, int64_t C,
-        MachineBasicBlock &B, MachineBasicBlock::iterator At, DebugLoc &DL);
+    Register genTfrConst(const TargetRegisterClass *RC, int64_t C,
+                         MachineBasicBlock &B, MachineBasicBlock::iterator At,
+                         DebugLoc &DL);
 
     const HexagonInstrInfo &HII;
     MachineRegisterInfo &MRI;
     BitTracker &BT;
   };
 
 } // end anonymous namespace
 
switch (Opc) {
     case Hexagon::CONST64:
       return true;
   }
   return false;
 }
 
 // Generate a transfer-immediate instruction that is appropriate for the
 // register class and the actual value being transferred.
-unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C,
-      MachineBasicBlock &B, MachineBasicBlock::iterator At, DebugLoc &DL) {
+Register ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C,
+                                      MachineBasicBlock &B,
+                                      MachineBasicBlock::iterator At,
+                                      DebugLoc &DL) {
   Register Reg = MRI.createVirtualRegister(RC);
   if (RC == &Hexagon::IntRegsRegClass) {
     BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), Reg)
         .addImm(int32_t(C));
     return Reg;
   }
 
   if (RC == &Hexagon::DoubleRegsRegClass) {
bool ConstGeneration::processBlock(MachineBasicBlock &B, const RegisterSet&) {
 
   for (auto I = B.begin(), E = B.end(); I != E; ++I) {
     if (isTfrConst(*I))
       continue;
     Defs.clear();
     HBS::getInstrDefs(*I, Defs);
     if (Defs.count() != 1)
       continue;
-    unsigned DR = Defs.find_first();
-    if (!Register::isVirtualRegister(DR))
+    Register DR = Defs.find_first();
+    if (!DR.isVirtual())
       continue;
     uint64_t U;
     const BitTracker::RegisterCell &DRC = BT.lookup(DR);
     if (HBS::getConst(DRC, 0, DRC.width(), U)) {
       int64_t C = U;
       DebugLoc DL = I->getDebugLoc();
       auto At = I->isPHI() ? B.getFirstNonPHI() : I;
-      unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL);
+      Register ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL);
       if (ImmReg) {
         HBS::replaceReg(DR, ImmReg, MRI);
         BT.put(ImmReg, DRC);
         Changed = true;
       }
     }
   }
   return Changed;
bool CopyGeneration::findMatch(const BitTracker::RegisterRef &Inp,
   if (!BT.has(Inp.Reg))
     return false;
   const BitTracker::RegisterCell &InpRC = BT.lookup(Inp.Reg);
   auto *FRC = HBS::getFinalVRegClass(Inp, MRI);
   unsigned B, W;
   if (!HBS::getSubregMask(Inp, B, W, MRI))
     return false;
 
-  for (unsigned R = AVs.find_first(); R; R = AVs.find_next(R)) {
+  for (Register R = AVs.find_first(); R; R = AVs.find_next(R)) {
     if (!BT.has(R) || Forbidden[R])
       continue;
     const BitTracker::RegisterCell &RC = BT.lookup(R);
     unsigned RW = RC.width();
     if (W == RW) {
       if (FRC != MRI.getRegClass(R))
         continue;
       if (!HBS::isTransparentCopy(R, Inp, MRI))
for (auto I = B.begin(), E = B.end(), NextI = I; I != E;
     unsigned Opc = I->getOpcode();
     if (CopyPropagation::isCopyReg(Opc, false) ||
         ConstGeneration::isTfrConst(*I))
       continue;
 
     DebugLoc DL = I->getDebugLoc();
     auto At = I->isPHI() ? B.getFirstNonPHI() : I;
 
-    for (unsigned R = Defs.find_first(); R; R = Defs.find_next(R)) {
+    for (Register R = Defs.find_first(); R; R = Defs.find_next(R)) {
       BitTracker::RegisterRef MR;
       auto *FRC = HBS::getFinalVRegClass(R, MRI);
 
       if (findMatch(R, MR, AVB)) {
         Register NewR = MRI.createVirtualRegister(FRC);
         BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
           .addReg(MR.Reg, 0, MR.Sub);
         BT.put(BitTracker::RegisterRef(NewR), BT.get(MR));
bool BitSimplification::matchHalf(unsigned SelfR,
   // and RC = { [0]:0 [1-15]:v1[1-15]... }.
   bool Low = false;
   unsigned I = B;
   while (I < B+16 && RC[I].num())
     I++;
   if (I == B+16)
     return false;
 
-  unsigned Reg = RC[I].RefI.Reg;
+  Register Reg = RC[I].RefI.Reg;
   unsigned P = RC[I].RefI.Pos;    // The RefI.Pos will be advanced by I-B.
   if (P < I-B)
     return false;
   unsigned Pos = P - (I-B);
 
   if (Reg == 0 || Reg == SelfR)    // Don't match "self".
     return false;
-  if (!Register::isVirtualRegister(Reg))
+  if (!Reg.isVirtual())
     return false;
   if (!BT.has(Reg))
     return false;
 
   const BitTracker::RegisterCell &SC = BT.lookup(Reg);
   if (Pos+16 > SC.width())
     return false;
 
if (TC == &Hexagon::DoubleRegsRegClass) {
       if (P >= 32) {
         P -= 32;
         RR.Sub = Hexagon::isub_hi;
       }
     } else if (TC == &Hexagon::IntRegsRegClass) {
       P = V.RefI.Pos;
     }
     if (P != std::numeric_limits<unsigned>::max()) {
-      unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
+      Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
       BuildMI(B, At, DL, HII.get(Hexagon::S2_tstbit_i), NewR)
           .addReg(RR.Reg, 0, RR.Sub)
           .addImm(P);
       HBS::replaceReg(RD.Reg, NewR, MRI);
       BT.put(NewR, RC);
       return true;
     }
   } else if (V.is(0) || V.is(1)) {
if (I->isTerminator())
       continue;
     if (I->isPHI())
       break;
 
     RegisterSet Defs;
     HBS::getInstrDefs(*I, Defs);
     if (Defs.count() != 1)
       continue;
-    unsigned DefR = Defs.find_first();
-    if (!Register::isVirtualRegister(DefR))
+    Register DefR = Defs.find_first();
+    if (!DefR.isVirtual())
       continue;
     if (!isBitShuffle(&*I, DefR))
       continue;
 
     bool BadUse = false;
     for (auto UI = MRI->use_begin(DefR), UE = MRI->use_end(); UI != UE; ++UI) {
       MachineInstr *UseI = UI->getParent();
       if (UseI->getParent() == C.LB) {

llvm/lib/Target/Hexagon/HexagonBitTracker.h

struct HexagonEvaluator : public BitTracker::MachineEvaluator {
   HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
                    const HexagonInstrInfo &tii, MachineFunction &mf);
 
   bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
                 CellMapType &Outputs) const override;
   bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
                 BranchTargetList &Targets, bool &FallsThru) const override;
 
-  BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override;
+  BitTracker::BitMask mask(Register Reg, unsigned Sub) const override;
 
-  uint16_t getPhysRegBitWidth(unsigned Reg) const override;
+  uint16_t getPhysRegBitWidth(Register Reg) const override;
 
   const TargetRegisterClass &composeWithSubRegIndex(
         const TargetRegisterClass &RC, unsigned Idx) const override;
 
   MachineFunction &MF;
   MachineFrameInfo &MFI;
   const HexagonInstrInfo &TII;
 

llvm/lib/Target/Hexagon/HexagonBitTracker.cpp

if (!InVirtReg)
       continue;
     if (Arg.hasAttribute(Attribute::SExt))
       VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
     else if (Arg.hasAttribute(Attribute::ZExt))
       VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
   }
 }
 
-BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
+BT::BitMask HexagonEvaluator::mask(Register Reg, unsigned Sub) const {
   if (Sub == 0)
     return MachineEvaluator::mask(Reg, 0);
   const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
   unsigned ID = RC.getID();
   uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
   const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
   bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
   switch (ID) {
     case Hexagon::DoubleRegsRegClassID:
     case Hexagon::HvxWRRegClassID:
     case Hexagon::HvxVQRRegClassID:
       return IsSubLo ? BT::BitMask(0, RW-1)
                      : BT::BitMask(RW, 2*RW-1);
     default:
       break;
   }
 #ifndef NDEBUG
   dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
          << TRI.getRegClassName(&RC) << '\n';
 #endif
   llvm_unreachable("Unexpected register/subregister");
 }
 
-uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
-  assert(Register::isPhysicalRegister(Reg));
+uint16_t HexagonEvaluator::getPhysRegBitWidth(Register Reg) const {
+  assert(Reg.isPhysical());
 
   using namespace Hexagon;
   const auto &HST = MF.getSubtarget<HexagonSubtarget>();
   if (HST.useHVXOps()) {
     for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
                      HvxVQRRegClass})
       if (RC.contains(Reg))
         return TRI.getRegSizeInBits(RC);

 }
 
 unsigned HexagonEvaluator::getUniqueDefVReg(const MachineInstr &MI) const {
   unsigned DefReg = 0;
   for (const MachineOperand &Op : MI.operands()) {
     if (!Op.isReg() || !Op.isDef())
       continue;
     Register R = Op.getReg();
-    if (!Register::isVirtualRegister(R))
+    if (!R.isVirtual())
       continue;
     if (DefReg != 0)
       return 0;
     DefReg = R;
   }
   return DefReg;
 }
 

llvm/lib/Target/Hexagon/HexagonBlockRanges.h

 //===- HexagonBlockRanges.h -------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H
 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H
 
 #include "llvm/ADT/BitVector.h"
+#include "llvm/CodeGen/Register.h"
 #include <cassert>
 #include <map>
 #include <set>
 #include <utility>
 #include <vector>
 
 namespace llvm {
 
 class HexagonSubtarget;
 class MachineBasicBlock;
 class MachineFunction;
 class MachineInstr;
 class MachineRegisterInfo;
 class raw_ostream;
 class TargetInstrInfo;
 class TargetRegisterInfo;
 
 struct HexagonBlockRanges {
   HexagonBlockRanges(MachineFunction &MF);
 
+  // FIXME: Consolidate duplicate definitions of RegisterRef
   struct RegisterRef {
-    unsigned Reg, Sub;
+    llvm::Register Reg;
+    unsigned Sub;
 
     bool operator<(RegisterRef R) const {
       return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
     }
   };
   using RegisterSet = std::set<RegisterRef>;
 
   // This is to represent an "index", which is an abstraction of a position

llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp

HexagonBlockRanges::RegisterSet HexagonBlockRanges::expandToSubRegs(
 
   if (Register::isPhysicalRegister(R.Reg)) {
     MCSubRegIterator I(R.Reg, &TRI);
     if (!I.isValid())
       SRs.insert({R.Reg, 0});
     for (; I.isValid(); ++I)
       SRs.insert({*I, 0});
   } else {
-    assert(Register::isVirtualRegister(R.Reg));
+    assert(R.Reg.isVirtual());
     auto &RC = *MRI.getRegClass(R.Reg);
     unsigned PReg = *RC.begin();
     MCSubRegIndexIterator I(PReg, &TRI);
     if (!I.isValid())
       SRs.insert({R.Reg, 0});
     for (; I.isValid(); ++I)
       SRs.insert({R.Reg, I.getSubRegIndex()});
   }
for (unsigned R = 1; R < NumRegs; ++R) {
     for (auto S : expandToSubRegs({R,0}, MRI, TRI)) {
       if (Reserved[S.Reg] || Visited[S.Reg])
         continue;
       addDeadRanges(S);
       Visited[S.Reg] = true;
     }
   }
   for (auto &P : LiveMap)
-    if (Register::isVirtualRegister(P.first.Reg))
+    if (P.first.Reg.isVirtual())
       addDeadRanges(P.first);
 
   LLVM_DEBUG(dbgs() << __func__ << ": dead map\n"
                     << PrintRangeMap(DeadMap, TRI) << '\n');
   return DeadMap;
 }
 
 raw_ostream &llvm::operator<<(raw_ostream &OS,

llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp

struct Register {
           Reg = Op.getReg();
           Sub = Op.getSubReg();
         } else if (Op.isFI()) {
           Reg = llvm::Register::index2StackSlot(Op.getIndex());
         }
         return *this;
       }
       bool isVReg() const {
-        return Reg != 0 && !llvm::Register::isStackSlot(Reg) &&
-               llvm::Register::isVirtualRegister(Reg);
-      }
-      bool isSlot() const {
-        return Reg != 0 && llvm::Register::isStackSlot(Reg);
+        return Reg != 0 && !Reg.isStack() && Reg.isVirtual();
       }
+      bool isSlot() const { return Reg != 0 && Reg.isStack(); }
       operator MachineOperand() const {
         if (isVReg())
           return MachineOperand::CreateReg(Reg, /*Def*/false, /*Imp*/false,
                           /*Kill*/false, /*Dead*/false, /*Undef*/false,
                           /*EarlyClobber*/false, Sub);
-        if (llvm::Register::isStackSlot(Reg)) {
+        if (Reg.isStack()) {
           int FI = llvm::Register::stackSlot2Index(Reg);
           return MachineOperand::CreateFI(FI);
         }
         llvm_unreachable("Cannot create MachineOperand");
       }
       bool operator==(Register R) const { return Reg == R.Reg && Sub == R.Sub; }
       bool operator!=(Register R) const { return !operator==(R); }
       bool operator<(Register R) const {
         // For std::map.
         return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
       }
-      unsigned Reg = 0, Sub = 0;
+      llvm::Register Reg;
+      unsigned Sub = 0;
     };
 
     struct ExtExpr {
       // A subexpression in which the extender is used. In general, this
       // represents an expression where adding D to the extender will be
       // equivalent to adding D to the expression as a whole. In other
       // words, expr(add(##V,D) = add(expr(##V),D).
 

llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp

namespace {
   };
 
   // A representation of a register as it can appear in a MachineOperand,
   // i.e. a pair register:subregister.
 
   // FIXME: Use TargetInstrInfo::RegSubRegPair. Also duplicated in
   // HexagonGenPredicate
   struct RegisterSubReg {
-    unsigned Reg, SubReg;
+    Register Reg;
+    unsigned SubReg;
 
     explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {}
     explicit RegisterSubReg(const MachineOperand &MO)
       : Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
 
     void print(const TargetRegisterInfo *TRI = nullptr) const {
       dbgs() << printReg(Reg, TRI, SubReg);
     }
public:
     public:
       CellMap() {
         assert(Top.isTop());
         Bottom.setBottom();
       }
 
       void clear() { Map.clear(); }
 
-      bool has(unsigned R) const {
+      bool has(Register R) const {
         // All non-virtual registers are considered "bottom".
-        if (!Register::isVirtualRegister(R))
+        if (!R.isVirtual())
           return true;
         MapType::const_iterator F = Map.find(R);
         return F != Map.end();
       }
 
-      const LatticeCell &get(unsigned R) const {
-        if (!Register::isVirtualRegister(R))
+      const LatticeCell &get(Register R) const {
+        if (!R.isVirtual())
           return Bottom;
         MapType::const_iterator F = Map.find(R);
         if (F != Map.end())
           return F->second;
         return Top;
       }
 
       // Invalidates any const references.
-      void update(unsigned R, const LatticeCell &L) {
-        Map[R] = L;
-      }
+      void update(Register R, const LatticeCell &L) { Map[R] = L; }
 
       void print(raw_ostream &os, const TargetRegisterInfo &TRI) const;
 
     private:
-      using MapType = std::map<unsigned, LatticeCell>;
+      using MapType = std::map<Register, LatticeCell>;
 
       MapType Map;
       // To avoid creating "top" entries, return a const reference to
       // this cell in "get". Also, have a "Bottom" cell to return from
       // get when a value of a physical register is requested.
       LatticeCell Top, Bottom;
 
     public:

 
 void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
   const MachineBasicBlock *MB = PN.getParent();
   unsigned MBN = MB->getNumber();
   LLVM_DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN);
 
   const MachineOperand &MD = PN.getOperand(0);
   RegisterSubReg DefR(MD);
-  assert(Register::isVirtualRegister(DefR.Reg));
+  assert(DefR.Reg.isVirtual());
 
   bool Changed = false;
 
   // If the def has a sub-register, set the corresponding cell to "bottom".
   if (DefR.SubReg) {
 Bottomize:
     const LatticeCell &T = Cells.get(DefR.Reg);
     Changed = !T.isBottom();
if (!EdgeExec.count(CFGEdge(PBN, MBN))) {
       LLVM_DEBUG(dbgs() << "  edge " << printMBBReference(*PB) << "->"
                         << printMBBReference(*MB) << " not executable\n");
       continue;
     }
     const MachineOperand &SO = PN.getOperand(i);
     RegisterSubReg UseR(SO);
     // If the input is not a virtual register, we don't really know what
     // value it holds.
-    if (!Register::isVirtualRegister(UseR.Reg))
+    if (!UseR.Reg.isVirtual())
       goto Bottomize;
     // If there is no cell for an input register, it means top.
     if (!Cells.has(UseR.Reg))
       continue;
 
     LatticeCell SrcC;
     bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC);
     LLVM_DEBUG(dbgs() << "  edge from " << printMBBReference(*PB) << ": "
void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
 
   // Update outputs. If the value was not computed, set all the
   // def cells to bottom.
   for (const MachineOperand &MO : MI.operands()) {
     if (!MO.isReg() || !MO.isDef())
       continue;
     RegisterSubReg DefR(MO);
     // Only track virtual registers.
-    if (!Register::isVirtualRegister(DefR.Reg))
+    if (!DefR.Reg.isVirtual())
       continue;
     bool Changed = false;
     // If the evaluation failed, set cells for all output registers to bottom.
     if (!Eval) {
       const LatticeCell &T = Cells.get(DefR.Reg);
       Changed = !T.isBottom();
       Cells.update(DefR.Reg, Bottom);
     } else {
bool MachineConstPropagator::run(MachineFunction &MF) {
   return Changed;
 }
 
 // --------------------------------------------------------------------
 // Machine const evaluator.
 
 bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs,
       LatticeCell &RC) {
-  if (!Register::isVirtualRegister(R.Reg))
+  if (!R.Reg.isVirtual())
     return false;
   const LatticeCell &L = Inputs.get(R.Reg);
   if (!R.SubReg) {
     RC = L;
     return !RC.isBottom();
   }
   bool Eval = evaluate(R, L, RC);
   return Eval && !RC.isBottom();
bool evaluateHexCondMove(const MachineInstr &MI, const CellMap &Inputs,
           CellMap &Outputs);
     bool evaluateHexExt(const MachineInstr &MI, const CellMap &Inputs,
           CellMap &Outputs);
     bool evaluateHexVector1(const MachineInstr &MI, const CellMap &Inputs,
           CellMap &Outputs);
     bool evaluateHexVector2(const MachineInstr &MI, const CellMap &Inputs,
           CellMap &Outputs);
 
-    void replaceAllRegUsesWith(unsigned FromReg, unsigned ToReg);
+    void replaceAllRegUsesWith(Register FromReg, Register ToReg);
     bool rewriteHexBranch(MachineInstr &BrI, const CellMap &Inputs);
     bool rewriteHexConstDefs(MachineInstr &MI, const CellMap &Inputs,
           bool &AllDefs);
     bool rewriteHexConstUses(MachineInstr &MI, const CellMap &Inputs);
 
     MachineRegisterInfo *MRI;
     const HexagonInstrInfo &HII;
     const HexagonRegisterInfo &HRI;
if (MI.getNumOperands() == 0 || !MI.getOperand(0).isReg())
     return false;
   const MachineOperand &MD = MI.getOperand(0);
   if (!MD.isDef())
     return false;
 
   unsigned Opc = MI.getOpcode();
   RegisterSubReg DefR(MD);
   assert(!DefR.SubReg);
-  if (!Register::isVirtualRegister(DefR.Reg))
+  if (!DefR.Reg.isVirtual())
     return false;
 
   if (MI.isCopy()) {
     LatticeCell RC;
     RegisterSubReg SrcR(MI.getOperand(1));
     bool Eval = evaluateCOPY(SrcR, Inputs, RC);
     if (!Eval)
       return false;

 #ifndef NDEBUG
   bool Debugging = DebugFlag && isCurrentDebugType(DEBUG_TYPE);
   if (Debugging) {
     bool Const = true, HasUse = false;
     for (const MachineOperand &MO : MI.operands()) {
       if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
         continue;
       RegisterSubReg R(MO);
-      if (!Register::isVirtualRegister(R.Reg))
+      if (!R.Reg.isVirtual())
         continue;
       HasUse = true;
       // PHIs can legitimately have "top" cells after propagation.
       if (!MI.isPHI() && !Inputs.has(R.Reg)) {
         dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg)
                << " in MI: " << MI;
         continue;
       }
#endif
   auto &HST = MF->getSubtarget<HexagonSubtarget>();
 
   // Collect all virtual register-def operands.
   SmallVector<unsigned,2> DefRegs;
   for (const MachineOperand &MO : MI.operands()) {
     if (!MO.isReg() || !MO.isDef())
       continue;
     Register R = MO.getReg();
-    if (!Register::isVirtualRegister(R))
+    if (!R.isVirtual())
       continue;
     assert(!MO.getSubReg());
     assert(Inputs.has(R));
     DefRegs.push_back(R);
   }
 
   MachineBasicBlock &B = *MI.getParent();
   const DebugLoc &DL = MI.getDebugLoc();
if (NewMI) {
       else
         dbgs() << "  modified the instruction itself and created:" << *NewMI;
     }
   });
 
   return Changed;
 }
 
-void HexagonConstEvaluator::replaceAllRegUsesWith(unsigned FromReg,
-      unsigned ToReg) {
-  assert(Register::isVirtualRegister(FromReg));
-  assert(Register::isVirtualRegister(ToReg));
+void HexagonConstEvaluator::replaceAllRegUsesWith(Register FromReg,
+                                                  Register ToReg) {
+  assert(FromReg.isVirtual());
+  assert(ToReg.isVirtual());
   for (auto I = MRI->use_begin(FromReg), E = MRI->use_end(); I != E;) {
     MachineOperand &O = *I;
     ++I;
     O.setReg(ToReg);
   }
 }
 
 bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI,

llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp

for (auto &MI : *B) {
     // be used outside of this block (or else it won't be possible to
     // update the use of it after predication). PHI uses will be updated
     // to use a result of a MUX, and a MUX cannot be created for predicate
     // registers.
     for (const MachineOperand &MO : MI.operands()) {
       if (!MO.isReg() || !MO.isDef())
         continue;
       Register R = MO.getReg();
-      if (!Register::isVirtualRegister(R))
+      if (!R.isVirtual())
         continue;
       if (!isPredicate(R))
         continue;
       for (auto U = MRI->use_begin(R); U != MRI->use_end(); ++U)
         if (U->getParent()->isPHI())
           return false;
     }
   }
   return true;
 }
 
 bool HexagonEarlyIfConversion::usesUndefVReg(const MachineInstr *MI) const {
   for (const MachineOperand &MO : MI->operands()) {
     if (!MO.isReg() || !MO.isUse())
       continue;
     Register R = MO.getReg();
-    if (!Register::isVirtualRegister(R))
+    if (!R.isVirtual())
       continue;
     const MachineInstr *DefI = MRI->getVRegDef(R);
     // "Undefined" virtual registers are actually defined via IMPLICIT_DEF.
     assert(DefI && "Expecting a reaching def in MRI");
     if (DefI->isImplicitDef())
       return true;
   }
   return false;

 unsigned HexagonEarlyIfConversion::countPredicateDefs(
       const MachineBasicBlock *B) const {
   unsigned PredDefs = 0;
   for (auto &MI : *B) {
     for (const MachineOperand &MO : MI.operands()) {
       if (!MO.isReg() || !MO.isDef())
         continue;
       Register R = MO.getReg();
-      if (!Register::isVirtualRegister(R))
+      if (!R.isVirtual())
         continue;
       if (isPredicate(R))
         PredDefs++;
     }
   }
   return PredDefs;
 }
 

llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp

private:
     LiveIntervals *LIS = nullptr;
     bool CoaLimitActive = false;
     bool TfrLimitActive = false;
     unsigned CoaLimit;
     unsigned TfrLimit;
     unsigned CoaCounter = 0;
     unsigned TfrCounter = 0;
 
+    // FIXME: Consolidate duplicate definitions of RegisterRef
     struct RegisterRef {
       RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
           Sub(Op.getSubReg()) {}
       RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
 
       bool operator== (RegisterRef RR) const {
         return Reg == RR.Reg && Sub == RR.Sub;
       }
       bool operator!= (RegisterRef RR) const { return !operator==(RR); }
       bool operator< (RegisterRef RR) const {
         return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
       }
 
-      unsigned Reg, Sub;
+      Register Reg;
+      unsigned Sub;
     };
 
     using ReferenceMap = DenseMap<unsigned, unsigned>;
     enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
     enum { Exec_Then = 0x10, Exec_Else = 0x20 };
 
     unsigned getMaskForSub(unsigned Sub);
     bool isCondset(const MachineInstr &MI);
-    LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
+    LaneBitmask getLaneMask(Register Reg, unsigned Sub);
 
     void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
     bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
 
-    void updateDeadsInRange(unsigned Reg, LaneBitmask LM, LiveRange &Range);
-    void updateKillFlags(unsigned Reg);
-    void updateDeadFlags(unsigned Reg);
-    void recalculateLiveInterval(unsigned Reg);
+    void updateDeadsInRange(Register Reg, LaneBitmask LM, LiveRange &Range);
+    void updateKillFlags(Register Reg);
+    void updateDeadFlags(Register Reg);
+    void recalculateLiveInterval(Register Reg);
     void removeInstr(MachineInstr &MI);
-    void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
+    void updateLiveness(std::set<Register> &RegSet, bool Recalc,
                         bool UpdateKills, bool UpdateDeads);
 
     unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
     MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
         MachineBasicBlock::iterator At, unsigned DstR,
         unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
         bool ReadUndef, bool ImpUse);
-    bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs);
+    bool split(MachineInstr &MI, std::set<Register> &UpdRegs);
 
     bool isPredicable(MachineInstr *MI);
     MachineInstr *getReachingDefForPred(RegisterRef RD,
         MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
     bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
     bool canMoveMemTo(MachineInstr &MI, MachineInstr &ToI, bool IsDown);
     void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
                      MachineBasicBlock::iterator Where,
                      const MachineOperand &PredOp, bool Cond,
-                     std::set<unsigned> &UpdRegs);
+                     std::set<Register> &UpdRegs);
     void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
         bool Cond, MachineBasicBlock::iterator First,
         MachineBasicBlock::iterator Last);
-    bool predicate(MachineInstr &TfrI, bool Cond, std::set<unsigned> &UpdRegs);
-    bool predicateInBlock(MachineBasicBlock &B,
-        std::set<unsigned> &UpdRegs);
+    bool predicate(MachineInstr &TfrI, bool Cond, std::set<Register> &UpdRegs);
+    bool predicateInBlock(MachineBasicBlock &B, std::set<Register> &UpdRegs);
 
     bool isIntReg(RegisterRef RR, unsigned &BW);
     bool isIntraBlocks(LiveInterval &LI);
     bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
-    bool coalesceSegments(const SmallVectorImpl<MachineInstr*> &Condsets,
-                          std::set<unsigned> &UpdRegs);
+    bool coalesceSegments(const SmallVectorImpl<MachineInstr *> &Condsets,
+                          std::set<Register> &UpdRegs);
   };
 
 } // end anonymous namespace
 
 char HexagonExpandCondsets::ID = 0;
 
 namespace llvm {
 
switch (Opc) {
     case Hexagon::C2_muxri:
     case Hexagon::PS_pselect:
         return true;
       break;
   }
   return false;
 }
 
-LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
-  assert(Register::isVirtualRegister(Reg));
+LaneBitmask HexagonExpandCondsets::getLaneMask(Register Reg, unsigned Sub) {
+  assert(Reg.isVirtual());
   return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
                   : MRI->getMaxLaneMaskForVReg(Reg);
 }
 
 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
       unsigned Exec) {
   unsigned Mask = getMaskForSub(RR.Sub) | Exec;
   ReferenceMap::iterator F = Map.find(RR.Reg);
bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
   if (F == Map.end())
     return false;
   unsigned Mask = getMaskForSub(RR.Sub) | Exec;
   if (Mask & F->second)
     return true;
   return false;
 }
 
-void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
+void HexagonExpandCondsets::updateKillFlags(Register Reg) {
   auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void {
     // Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
     MachineInstr *MI = LIS->getInstructionFromIndex(K);
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand &Op = MI->getOperand(i);
       if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg ||
           MI->isRegTiedToDefOperand(i))
         continue;
if (LI.hasSubRanges()) {
           WholeReg = false;
       }
     }
     if (WholeReg)
       KillAt(I->end, MRI->getMaxLaneMaskForVReg(Reg));
   }
 }
 
-void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
+void HexagonExpandCondsets::updateDeadsInRange(Register Reg, LaneBitmask LM,
                                                LiveRange &Range) {
-  assert(Register::isVirtualRegister(Reg));
+  assert(Reg.isVirtual());
   if (Range.empty())
     return;
 
   // Return two booleans: { def-modifes-reg, def-covers-reg }.
   auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> {
     if (!Op.isReg() || !Op.isDef())
       return { false, false };
     Register DR = Op.getReg(), DSR = Op.getSubReg();
-    if (!Register::isVirtualRegister(DR) || DR != Reg)
+    if (!DR.isVirtual() || DR != Reg)
       return { false, false };
     LaneBitmask SLM = getLaneMask(DR, DSR);
     LaneBitmask A = SLM & LM;
     return { A.any(), A == SLM };
   };
 
   // The splitting step will create pairs of predicated definitions without
   // any implicit uses (since implicit uses would interfere with predication).
for (auto &Seg : Range) {
     for (std::pair<RegisterRef, unsigned> P : ImpUses) {
       RegisterRef R = P.first;
       MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
       DefI->tieOperands(P.second, DefI->getNumOperands()-1);
     }
   }
 }
 
-void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
+void HexagonExpandCondsets::updateDeadFlags(Register Reg) {
   LiveInterval &LI = LIS->getInterval(Reg);
   if (LI.hasSubRanges()) {
     for (LiveInterval::SubRange &S : LI.subranges()) {
       updateDeadsInRange(Reg, S.LaneMask, S);
       LIS->shrinkToUses(S, Reg);
     }
     LI.clear();
     LIS->constructMainRangeFromSubranges(LI);
   } else {
     updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI);
   }
 }
 
-void HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) {
+void HexagonExpandCondsets::recalculateLiveInterval(Register Reg) {
   LIS->removeInterval(Reg);
   LIS->createAndComputeVirtRegInterval(Reg);
 }
 
 void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
   LIS->RemoveMachineInstrFromMaps(MI);
   MI.eraseFromParent();
 }
 
-void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
-      bool Recalc, bool UpdateKills, bool UpdateDeads) {
+void HexagonExpandCondsets::updateLiveness(std::set<Register> &RegSet,
+                                           bool Recalc, bool UpdateKills,
+                                           bool UpdateDeads) {
   UpdateKills |= UpdateDeads;
-  for (unsigned R : RegSet) {
-    if (!Register::isVirtualRegister(R)) {
-      assert(Register::isPhysicalRegister(R));
+  for (Register R : RegSet) {
+    if (!R.isVirtual()) {
+      assert(R.isPhysical());
       // There shouldn't be any physical registers as operands, except
       // possibly reserved registers.
       assert(MRI->isReserved(R));
       continue;
     }
     if (Recalc)
       recalculateLiveInterval(R);
     if (UpdateKills)

 /// operand). The condition (true/false) is given in Cond.
 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
       bool IfTrue) {
   using namespace Hexagon;
 
   if (SO.isReg()) {
     Register PhysR;
     RegisterRef RS = SO;
-    if (Register::isVirtualRegister(RS.Reg)) {
+    if (RS.Reg.isVirtual()) {
       const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
       assert(VC->begin() != VC->end() && "Empty register class");
       PhysR = *VC->begin();
     } else {
       assert(Register::isPhysicalRegister(RS.Reg));
       PhysR = RS.Reg;
     }
     Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
 
   LLVM_DEBUG(dbgs() << "created an initial copy: " << *MIB);
   return &*MIB;
 }
 
 /// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
 /// performs all necessary changes to complete the replacement.
 bool HexagonExpandCondsets::split(MachineInstr &MI,
-                                  std::set<unsigned> &UpdRegs) {
+                                  std::set<Register> &UpdRegs) {
   if (TfrLimitActive) {
     if (TfrCounter >= TfrLimit)
       return false;
     TfrCounter++;
   }
   LLVM_DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent())
                     << ": " << MI);
   MachineOperand &MD = MI.getOperand(0);  // Definition
bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs,
   // and no use operand can be defined.
   for (auto &Op : MI.operands()) {
     if (!Op.isReg())
       continue;
     RegisterRef RR = Op;
     // For physical register we would need to check register aliases, etc.
     // and we don't want to bother with that. It would be of little value
     // before the actual register rewriting (from virtual to physical).
-    if (!Register::isVirtualRegister(RR.Reg))
+    if (!RR.Reg.isVirtual())
       return false;
     // No redefs for any operand.
     if (isRefInMap(RR, Defs, Exec_Then))
       return false;
     // For defs, there cannot be uses.
     if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
       return false;
   }

 }
 
 /// Generate a predicated version of MI (where the condition is given via
 /// PredR and Cond) at the point indicated by Where.
 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
                                         MachineInstr &MI,
                                         MachineBasicBlock::iterator Where,
                                         const MachineOperand &PredOp, bool Cond,
-                                        std::set<unsigned> &UpdRegs) {
+                                        std::set<Register> &UpdRegs) {
   // The problem with updating live intervals is that we can move one def
   // past another def. In particular, this can happen when moving an A2_tfrt
   // over an A2_tfrf defining the same register. From the point of view of
   // live intervals, these two instructions are two separate definitions,
   // and each one starts another live segment. LiveIntervals's "handleMove"
   // does not allow such moves, so we need to handle it ourselves. To avoid
   // invalidating liveness data while we are using it, the move will be
   // implemented in 4 steps: (1) add a clone of the instruction MI at the
for (MachineBasicBlock::iterator I = First; I != End; ++I) {
     }
   }
 }
 
 /// For a given conditional copy, predicate the definition of the source of
 /// the copy under the given condition (using the same predicate register as
 /// the copy).
 bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
-                                      std::set<unsigned> &UpdRegs) {
+                                      std::set<Register> &UpdRegs) {
   // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
   unsigned Opc = TfrI.getOpcode();
   (void)Opc;
   assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
   LLVM_DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
                     << ": " << TfrI);
 
   MachineOperand &MD = TfrI.getOperand(0);
for (auto &Op : MI->operands()) {
       // We don't want to deal with physical registers. The reason is that
       // they can be aliased with other physical registers. Aliased virtual
       // registers must share the same register number, and can only differ
       // in the subregisters, which we are keeping track of. Physical
       // registers ters no longer have subregisters---their super- and
       // subregisters are other physical registers, and we are not checking
       // that.
       RegisterRef RR = Op;
-      if (!Register::isVirtualRegister(RR.Reg))
+      if (!RR.Reg.isVirtual())
         return false;
 
       ReferenceMap &Map = Op.isDef() ? Defs : Uses;
       if (Op.isDef() && Op.isUndef()) {
         assert(RR.Sub && "Expecting a subregister on <def,read-undef>");
         // If this is a <def,read-undef>, then it invalidates the non-written
         // part of the register. For the purpose of checking the validity of
         // the move, assume that it modifies the whole register.
bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
 
   removeInstr(TfrI);
   removeInstr(*DefI);
   return true;
 }
 
 /// Predicate all cases of conditional copies in the specified block.
 bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
-      std::set<unsigned> &UpdRegs) {
+                                             std::set<Register> &UpdRegs) {
   bool Changed = false;
   MachineBasicBlock::iterator I, E, NextI;
   for (I = B.begin(), E = B.end(); I != E; I = NextI) {
     NextI = std::next(I);
     unsigned Opc = I->getOpcode();
     if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
       bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs);
       if (!Done) {
         // If we didn't predicate I, we may need to remove it in case it is
         // an "identity" copy, e.g.  %1 = A2_tfrt %2, %1.
         if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
           for (auto &Op : I->operands())
             if (Op.isReg())
               UpdRegs.insert(Op.getReg());
           removeInstr(*I);
         }
       }
       Changed |= Done;
     }
   }
   return Changed;
 }
 
 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
-  if (!Register::isVirtualRegister(RR.Reg))
+  if (!RR.Reg.isVirtual())
     return false;
   const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
   if (RC == &Hexagon::IntRegsRegClass) {
     BW = 32;
     return true;
   }
   if (RC == &Hexagon::DoubleRegsRegClass) {
     BW = (RR.Sub != 0) ? 32 : 64;
bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
 
   return true;
 }
 
 /// Attempt to coalesce one of the source registers to a MUX instruction with
 /// the destination register. This could lead to having only one predicated
 /// instruction in the end instead of two.
 bool HexagonExpandCondsets::coalesceSegments(
-      const SmallVectorImpl<MachineInstr*> &Condsets,
-      std::set<unsigned> &UpdRegs) {
+    const SmallVectorImpl<MachineInstr *> &Condsets,
+    std::set<Register> &UpdRegs) {
   SmallVector<MachineInstr*,16> TwoRegs;
   for (MachineInstr *MI : Condsets) {
     MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
     if (!S1.isReg() && !S2.isReg())
       continue;
     TwoRegs.push_back(MI);
   }
 
bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
   MDT = &getAnalysis<MachineDominatorTree>();
   LIS = &getAnalysis<LiveIntervals>();
   MRI = &MF.getRegInfo();
 
   LLVM_DEBUG(LIS->print(dbgs() << "Before expand-condsets\n",
                         MF.getFunction().getParent()));
 
   bool Changed = false;
-  std::set<unsigned> CoalUpd, PredUpd;
+  std::set<Register> CoalUpd, PredUpd;
 
   SmallVector<MachineInstr*,16> Condsets;
   for (auto &B : MF)
     for (auto &I : B)
       if (isCondset(I))
         Condsets.push_back(&I);
 
   // Try to coalesce the target of a mux with one of its sources.
   // This could eliminate a register copy in some circumstances.
   Changed |= coalesceSegments(Condsets, CoalUpd);
 
   // Update kill flags on all source operands. This is done here because
   // at this moment (when expand-condsets runs), there are no kill flags
   // in the IR (they have been removed by live range analysis).
   // Updating them right before we split is the easiest, because splitting
   // adds definitions which would interfere with updating kills afterwards.
-  std::set<unsigned> KillUpd;
+  std::set<Register> KillUpd;
   for (MachineInstr *MI : Condsets)
     for (MachineOperand &Op : MI->operands())
       if (Op.isReg() && Op.isUse())
         if (!CoalUpd.count(Op.getReg()))
           KillUpd.insert(Op.getReg());
   updateLiveness(KillUpd, false, true, false);
   LLVM_DEBUG(
       LIS->print(dbgs() << "After coalescing\n", MF.getFunction().getParent()));

llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

for (auto &I : MBB) {
         // index into an offset would have to be aware of the placement of
         // the frame creation/destruction instructions.
         if (MO.isFI())
           return true;
         if (MO.isReg()) {
           Register R = MO.getReg();
           // Virtual registers will need scavenging, which then may require
           // a stack slot.
-          if (Register::isVirtualRegister(R))
+          if (R.isVirtual())
             return true;
           for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
             if (CSR[*S])
               return true;
           continue;
         }
         if (MO.isRegMask()) {
           // A regmask would normally have all callee-saved registers marked

llvm/lib/Target/Hexagon/HexagonGenInsert.cpp

for (mf_iterator A = MFN->begin(), Z = MFN->end(); A != Z; ++A) {
 
     for (mb_iterator I = B.begin(), E = B.end(); I != E; ++I) {
       const MachineInstr *MI = &*I;
       for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
         const MachineOperand &MO = MI->getOperand(i);
         if (MO.isReg() && MO.isDef()) {
           Register R = MO.getReg();
           assert(MO.getSubReg() == 0 && "Unexpected subregister in definition");
-          if (Register::isVirtualRegister(R))
+          if (R.isVirtual())
             RO.insert(std::make_pair(R, Index++));
         }
       }
     }
   }
   // Since some virtual registers may have had their def and uses eliminated,
   // they are no longer referenced in the code, and so they will not appear
   // in the map.

 
 void HexagonGenInsert::getInstrDefs(const MachineInstr *MI,
       RegisterSet &Defs) const {
   for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg() || !MO.isDef())
       continue;
     Register R = MO.getReg();
-    if (!Register::isVirtualRegister(R))
+    if (!R.isVirtual())
       continue;
     Defs.insert(R);
   }
 }
 
 void HexagonGenInsert::getInstrUses(const MachineInstr *MI,
       RegisterSet &Uses) const {
   for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg() || !MO.isUse())
       continue;
     Register R = MO.getReg();
-    if (!Register::isVirtualRegister(R))
+    if (!R.isVirtual())
       continue;
     Uses.insert(R);
   }
 }
 
 unsigned HexagonGenInsert::distance(const MachineBasicBlock *FromB,
       const MachineBasicBlock *ToB, const UnsignedMap &RPO,
       PairMapType &M) const {
if (MI->isInlineAsm() || !MI->isSafeToMove(nullptr, Store))
       continue;
 
     bool AllDead = true;
     SmallVector<unsigned,2> Regs;
     for (const MachineOperand &MO : MI->operands()) {
       if (!MO.isReg() || !MO.isDef())
         continue;
       Register R = MO.getReg();
-      if (!Register::isVirtualRegister(R) || !MRI->use_nodbg_empty(R)) {
+      if (!R.isVirtual() || !MRI->use_nodbg_empty(R)) {
         AllDead = false;
         break;
       }
       Regs.push_back(R);
     }
     if (!AllDead)
       continue;
 

llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp

namespace llvm {
   FunctionPass *createHexagonGenPredicate();
 
 } // end namespace llvm
 
 namespace {
 
   // FIXME: Use TargetInstrInfo::RegSubRegPair
   struct RegisterSubReg {
-    unsigned R, S;
+    Register R;
+    unsigned S;
 
     RegisterSubReg(unsigned r = 0, unsigned s = 0) : R(r), S(s) {}
     RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
     RegisterSubReg(const Register &Reg) : R(Reg), S(0) {}
 
     bool operator== (const RegisterSubReg &Reg) const {
       return R == Reg.R && S == Reg.S;
     }
private:
 
     const HexagonInstrInfo *TII = nullptr;
     const HexagonRegisterInfo *TRI = nullptr;
     MachineRegisterInfo *MRI = nullptr;
     SetOfReg PredGPRs;
     VectOfInst PUsers;
     RegToRegMap G2P;
 
-    bool isPredReg(unsigned R);
+    bool isPredReg(Register R);
     void collectPredicateGPR(MachineFunction &MF);
     void processPredicateGPR(const RegisterSubReg &Reg);
     unsigned getPredForm(unsigned Opc);
     bool isConvertibleToPredForm(const MachineInstr *MI);
     bool isScalarCmp(unsigned Opc);
     bool isScalarPred(RegisterSubReg PredReg);
     RegisterSubReg getPredRegFor(const RegisterSubReg &Reg);
     bool convertToPredForm(MachineInstr *MI);
     bool eliminatePredCopies(MachineFunction &MF);
   };
 
 } // end anonymous namespace
 
 char HexagonGenPredicate::ID = 0;
 
 INITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred",
   "Hexagon generate predicate operations", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
 INITIALIZE_PASS_END(HexagonGenPredicate, "hexagon-gen-pred",
   "Hexagon generate predicate operations", false, false)
 
-bool HexagonGenPredicate::isPredReg(unsigned R) {
-  if (!Register::isVirtualRegister(R))
+bool HexagonGenPredicate::isPredReg(Register R) {
+  if (!R.isVirtual())
     return false;
   const TargetRegisterClass *RC = MRI->getRegClass(R);
   return RC == &Hexagon::PredRegsRegClass;
 }
 
 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) {
   using namespace Hexagon;
 
for (MachineFunction::iterator A = MF.begin(), Z = MF.end(); A != Z; ++A) {
     for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
       MachineInstr *MI = &*I;
       unsigned Opc = MI->getOpcode();
       switch (Opc) {
         case Hexagon::C2_tfrpr:
         case TargetOpcode::COPY:
           if (isPredReg(MI->getOperand(1).getReg())) {
             RegisterSubReg RD = MI->getOperand(0);
-            if (Register::isVirtualRegister(RD.R))
+            if (RD.R.isVirtual())
               PredGPRs.insert(RD);
           }
           break;
       }
     }
   }
 }
 
if (isConvertibleToPredForm(UseI))
       PUsers.insert(UseI);
   }
 }
 
 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) {
   // Create a predicate register for a given Reg. The newly created register
   // will have its value copied from Reg, so that it can be later used as
   // an operand in other instructions.
-  assert(Register::isVirtualRegister(Reg.R));
+  assert(Reg.R.isVirtual());
   RegToRegMap::iterator F = G2P.find(Reg);
   if (F != G2P.end())
     return F->second;
 
   LLVM_DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI));
   MachineInstr *DefI = MRI->getVRegDef(Reg.R);
   assert(DefI);
   unsigned Opc = DefI->getOpcode();
bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
   // copied back into the original gpr.
 
   for (MachineBasicBlock &MBB : MF) {
     for (MachineInstr &MI : MBB) {
       if (MI.getOpcode() != TargetOpcode::COPY)
         continue;
       RegisterSubReg DR = MI.getOperand(0);
       RegisterSubReg SR = MI.getOperand(1);
-      if (!Register::isVirtualRegister(DR.R))
+      if (!DR.R.isVirtual())
         continue;
-      if (!Register::isVirtualRegister(SR.R))
+      if (!SR.R.isVirtual())
         continue;
       if (MRI->getRegClass(DR.R) != PredRC)
         continue;
       if (MRI->getRegClass(SR.R) != PredRC)
         continue;
       assert(!DR.S && !SR.S && "Unexpected subregister");
       MRI->replaceRegWith(DR.R, SR.R);
       Erase.insert(&MI);

llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow(
   // won't underflow in the first iteration.
   int64_t Imm;
   if (checkForImmediate(*InitVal, Imm))
     return (EndVal->getImm() == Imm);
 
   Register Reg = InitVal->getReg();
 
   // We don't know the value of a physical register.
-  if (!Register::isVirtualRegister(Reg))
+  if (!Reg.isVirtual())
     return true;
 
   MachineInstr *Def = MRI->getVRegDef(Reg);
   if (!Def)
     return true;
 
   // If the initial value is a Phi or copy and the operands may not underflow,
   // then the definition cannot be underflow either.
if (!MO.isReg())
     return false;
 
   // MO is a register. Check whether it is defined as an immediate value,
   // and if so, get the value of it in TV. That value will then need to be
   // processed to handle potential subregisters in MO.
   int64_t TV;
 
   Register R = MO.getReg();
-  if (!Register::isVirtualRegister(R))
+  if (!R.isVirtual())
     return false;
   MachineInstr *DI = MRI->getVRegDef(R);
   unsigned DOpc = DI->getOpcode();
   switch (DOpc) {
     case TargetOpcode::COPY:
     case Hexagon::A2_tfrsi:
     case Hexagon::A2_tfrpi:
     case Hexagon::CONST32:

llvm/lib/Target/Hexagon/HexagonPeephole.cpp

for (auto I = MBB->begin(), E = MBB->end(), NextI = I; I != E; I = NextI) {
       // %170 = SXTW %166
       if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
         assert(MI.getNumOperands() == 2);
         MachineOperand &Dst = MI.getOperand(0);
         MachineOperand &Src = MI.getOperand(1);
         Register DstReg = Dst.getReg();
         Register SrcReg = Src.getReg();
         // Just handle virtual registers.
-        if (Register::isVirtualRegister(DstReg) &&
-            Register::isVirtualRegister(SrcReg)) {
+        if (DstReg.isVirtual() && SrcReg.isVirtual()) {
           // Map the following:
           // %170 = SXTW %166
           // PeepholeMap[170] = %166
           PeepholeMap[DstReg] = SrcReg;
         }
       }
 
       // Look for  %170 = COMBINE_ir_V4 (0, %169)
for (auto I = MBB->begin(), E = MBB->end(), NextI = I; I != E; I = NextI) {
       // Look for P=NOT(P).
       if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) {
         assert(MI.getNumOperands() == 2);
         MachineOperand &Dst = MI.getOperand(0);
         MachineOperand &Src = MI.getOperand(1);
         Register DstReg = Dst.getReg();
         Register SrcReg = Src.getReg();
         // Just handle virtual registers.
-        if (Register::isVirtualRegister(DstReg) &&
-            Register::isVirtualRegister(SrcReg)) {
+        if (DstReg.isVirtual() && SrcReg.isVirtual()) {
           // Map the following:
           // %170 = NOT_xx %166
           // PeepholeMap[170] = %166
           PeepholeMap[DstReg] = SrcReg;
         }
       }
 
       // Look for copy:
       // %176 = COPY %170:isub_lo
       if (!DisableOptSZExt && MI.isCopy()) {
         assert(MI.getNumOperands() == 2);
         MachineOperand &Dst = MI.getOperand(0);
         MachineOperand &Src = MI.getOperand(1);
 
         // Make sure we are copying the lower 32 bits.
         if (Src.getSubReg() != Hexagon::isub_lo)
           continue;
 
         Register DstReg = Dst.getReg();
         Register SrcReg = Src.getReg();
-        if (Register::isVirtualRegister(DstReg) &&
-            Register::isVirtualRegister(SrcReg)) {
+        if (DstReg.isVirtual() && SrcReg.isVirtual()) {
           // Try to find in the map.
           if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
             // Change the 1st operand.
             MI.RemoveOperand(1);
             MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
           } else  {
             DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
               PeepholeDoubleRegsMap.find(SrcReg);
for (auto I = MBB->begin(), E = MBB->end(), NextI = I; I != E; I = NextI) {
         bool Done = false;
         if (QII->isPredicated(MI)) {
           MachineOperand &Op0 = MI.getOperand(0);
           Register Reg0 = Op0.getReg();
           const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
           if (RC0->getID() == Hexagon::PredRegsRegClassID) {
             // Handle instructions that have a prediate register in op0
             // (most cases of predicable instructions).
-            if (Register::isVirtualRegister(Reg0)) {
+            if (Reg0.isVirtual()) {
               // Try to find in the map.
               if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
                 // Change the 1st operand and, flip the opcode.
                 MI.getOperand(0).setReg(PeepholeSrc);
                 MRI->clearKillFlags(PeepholeSrc);
                 int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());
                 MI.setDesc(QII->get(NewOp));
                 Done = true;

llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp

private:
     using UUPairMap = std::map<unsigned, UUPair>;
     using LoopRegMap = std::map<const MachineLoop *, USet>;
 
     bool isInduction(unsigned Reg, LoopRegMap &IRM) const;
     bool isVolatileInstr(const MachineInstr *MI) const;
     bool isFixedInstr(const MachineInstr *MI) const;
     void partitionRegisters(UUSetMap &P2Rs);
     int32_t profit(const MachineInstr *MI) const;
-    int32_t profit(unsigned Reg) const;
+    int32_t profit(Register Reg) const;
     bool isProfitable(const USet &Part, LoopRegMap &IRM) const;
 
     void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
     void collectIndRegs(LoopRegMap &IRM);
 
     void createHalfInstr(unsigned Opc, MachineInstr *MI,
         const UUPairMap &PairMap, unsigned SubR);
     void splitMemRef(MachineInstr *MI, const UUPairMap &PairMap);
switch (Opc) {
     case Hexagon::S2_lsr_i_p:
       break;
   }
 
   for (auto &Op : MI->operands()) {
     if (!Op.isReg())
       continue;
     Register R = Op.getReg();
-    if (!Register::isVirtualRegister(R))
+    if (!R.isVirtual())
       return true;
   }
   return false;
 }
 
 void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
   using UUMap = std::map<unsigned, unsigned>;
   using UVect = std::vector<unsigned>;
for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end();
       if (isFixedInstr(UseI))
         continue;
       for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) {
         MachineOperand &MO = UseI->getOperand(i);
         // Skip non-registers or registers with subregisters.
         if (&MO == &Op || !MO.isReg() || MO.getSubReg())
           continue;
         Register T = MO.getReg();
-        if (!Register::isVirtualRegister(T)) {
+        if (!T.isVirtual()) {
           FixedRegs.set(x);
           continue;
         }
         if (MRI->getRegClass(T) != DoubleRC)
           continue;
         unsigned u = Register::virtReg2Index(T);
         if (FixedRegs[u])
           continue;
case Hexagon::S2_lsr_i_p:
       if (S == 48)
         return 7;
       return -10;
   }
 
   return 0;
 }
 
-int32_t HexagonSplitDoubleRegs::profit(unsigned Reg) const {
-  assert(Register::isVirtualRegister(Reg));
+int32_t HexagonSplitDoubleRegs::profit(Register Reg) const {
+  assert(Reg.isVirtual());
 
   const MachineInstr *DefI = MRI->getVRegDef(Reg);
   switch (DefI->getOpcode()) {
     case Hexagon::A2_tfrpi:
     case Hexagon::CONST64:
     case Hexagon::A2_combineii:
     case Hexagon::A4_combineii:
     case Hexagon::A4_combineri:
void HexagonSplitDoubleRegs::createHalfInstr(unsigned Opc, MachineInstr *MI,
   for (auto &Op : MI->operands()) {
     if (!Op.isReg()) {
       NewI->addOperand(Op);
       continue;
     }
     // For register operands, set the subregister.
     Register R = Op.getReg();
     unsigned SR = Op.getSubReg();
-    bool isVirtReg = Register::isVirtualRegister(R);
+    bool isVirtReg = R.isVirtual();
     bool isKill = Op.isKill();
     if (isVirtReg && MRI->getRegClass(R) == DoubleRC) {
       isKill = false;
       UUPairMap::const_iterator F = PairMap.find(R);
       if (F == PairMap.end()) {
         SR = SubR;
       } else {
         const UUPair &P = F->second;
void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
       const UUPairMap &PairMap) {
   MachineBasicBlock &B = *MI->getParent();
   DebugLoc DL = MI->getDebugLoc();
 
   for (auto &Op : MI->operands()) {
     if (!Op.isReg() || !Op.isUse())
       continue;
     Register R = Op.getReg();
-    if (!Register::isVirtualRegister(R))
+    if (!R.isVirtual())
       continue;
     if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())
       continue;
     UUPairMap::const_iterator F = PairMap.find(R);
     if (F == PairMap.end())
       continue;
     const UUPair &Pr = F->second;
     Register NewDR = MRI->createVirtualRegister(DoubleRC);

llvm/lib/Target/Hexagon/HexagonSubtarget.cpp

if (QII.isHVXVec(SrcInst) || useBSBScheduling())
     Dep.setLatency((Dep.getLatency() + 1) >> 1);
 }
 
 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
   MachineInstr *SrcI = Src->getInstr();
   for (auto &I : Src->Succs) {
     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
       continue;
-    unsigned DepR = I.getReg();
+    Register DepR = I.getReg();
     int DefIdx = -1;
     for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
       const MachineOperand &MO = SrcI->getOperand(OpNum);
       bool IsSameOrSubReg = false;
       if (MO.isReg()) {
-        unsigned MOReg = MO.getReg();
-        if (Register::isVirtualRegister(DepR)) {
+        Register MOReg = MO.getReg();
+        if (DepR.isVirtual()) {
           IsSameOrSubReg = (MOReg == DepR);
         } else {
           IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg);
         }
         if (MO.isDef() && IsSameOrSubReg)
           DefIdx = OpNum;
       }
     }