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Differential D91146

[VE] Support inline assembly with vector regsiters
ClosedPublic

Authored by kaz7 on Nov 10 2020, 1:58 AM.

Details

Reviewers
simoll
k-ishizaka
Commits
rGc84b2c49be46: [VE] Support inline assembly with vector regsiters
Summary

Support inline assembly with vector registers. Add a regression test also.

Diff Detail

Unit TestsFailed

TimeTest
370 mslinux > HWAddressSanitizer-x86_64.TestCases::sizes.cpp

Event Timeline

kaz7 created this revision.Nov 10 2020, 1:58 AM
Herald added subscribers: llvm-commits, hiraditya. · View Herald TranscriptNov 10 2020, 1:58 AM
kaz7 requested review of this revision.Nov 10 2020, 1:58 AM
kaz7 updated this revision to Diff 304108.Nov 10 2020, 2:13 AM

Add lvl instructions to a regression test.

Harbormaster completed remote builds in B78264: Diff 304106.Nov 10 2020, 2:15 AM
Harbormaster completed remote builds in B78265: Diff 304108.Nov 10 2020, 2:37 AM
simoll accepted this revision.Nov 10 2020, 3:26 AM
This revision is now accepted and ready to land.Nov 10 2020, 3:26 AM
This revision was landed with ongoing or failed builds.Nov 10 2020, 3:55 AM
Closed by commit rGc84b2c49be46: [VE] Support inline assembly with vector regsiters (authored by kaz7). · Explain Why
This revision was automatically updated to reflect the committed changes.
kaz7 added a commit: rGc84b2c49be46: [VE] Support inline assembly with vector regsiters.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
1 line
1 line
16 lines
test/
CodeGen/
VE/
Scalar/
74 lines

Diff 304108

llvm/lib/Target/VE/VEAsmPrinter.cpp

Show First 20 Lines • Show All 371 Lines • ▼ Show 20 Lines if (ExtraCode && ExtraCode[0]) {
if (ExtraCode[1] != 0) if (ExtraCode[1] != 0)
return true; // Unknown modifier. return true; // Unknown modifier.
switch (ExtraCode[0]) { switch (ExtraCode[0]) {
default: default:
// See if this is a generic print operand // See if this is a generic print operand
return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O); return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
case 'r': case 'r':
case 'v':
break; break;
} }
} }
printOperand(MI, OpNo, O); printOperand(MI, OpNo, O);
return false; return false;
} }
// Force static initialization. // Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEAsmPrinter() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEAsmPrinter() {
RegisterAsmPrinter<VEAsmPrinter> X(getTheVETarget()); RegisterAsmPrinter<VEAsmPrinter> X(getTheVETarget());
} }

llvm/lib/Target/VE/VEISelLowering.h

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Linespublic:
/// Returns true if the target allows unaligned memory accesses of the /// Returns true if the target allows unaligned memory accesses of the
/// specified type. /// specified type.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
MachineMemOperand::Flags Flags, MachineMemOperand::Flags Flags,
bool *Fast) const override; bool *Fast) const override;
/// Inline Assembly { /// Inline Assembly {
ConstraintType getConstraintType(StringRef Constraint) const override;
std::pair<unsigned, const TargetRegisterClass *> std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override; StringRef Constraint, MVT VT) const override;
/// } Inline Assembly /// } Inline Assembly
/// Target Optimization { /// Target Optimization {
Show All 16 Lines

llvm/lib/Target/VE/VEISelLowering.cpp

Show First 20 Lines • Show All 1,545 Lines • ▼ Show 20 LinesSDValue VETargetLowering::PerformDAGCombine(SDNode *N,
return SDValue(); return SDValue();
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VE Inline Assembly Support // VE Inline Assembly Support
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
VETargetLowering::ConstraintType
VETargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default:
break;
case 'v': // vector registers
return C_RegisterClass;
}
}
return TargetLowering::getConstraintType(Constraint);
}
std::pair<unsigned, const TargetRegisterClass *> std::pair<unsigned, const TargetRegisterClass *>
VETargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, VETargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, StringRef Constraint,
MVT VT) const { MVT VT) const {
const TargetRegisterClass *RC = nullptr; const TargetRegisterClass *RC = nullptr;
if (Constraint.size() == 1) { if (Constraint.size() == 1) {
switch (Constraint[0]) { switch (Constraint[0]) {
default: default:
return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
case 'r': case 'r':
RC = &VE::I64RegClass; RC = &VE::I64RegClass;
break; break;
case 'v':
RC = &VE::V64RegClass;
break;
} }
return std::make_pair(0U, RC); return std::make_pair(0U, RC);
} }
return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
} }

llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
define void @vld(i8* %p, i64 %i) nounwind {
; CHECK-LABEL: vld:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
ret void
}
define void @vldvst(i8* %p, i64 %i) nounwind {
; CHECK-LABEL: vldvst:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
%1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %1, i8* %p, i64 %i) nounwind
ret void
}
define void @vld2vst2(i8* %p, i64 %i) nounwind {
; CHECK-LABEL: vld2vst2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: vld %v1, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v1, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
%1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
%2 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %1, i8* %p, i64 %i) nounwind
tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %2, i8* %p, i64 %i) nounwind
ret void
}