[VE] Support inline assembly

[kaz7]

Summary

Support inline assembly with scalar registers. Add a regression test also.

llvm/lib/Target/VE/VEAsmPrinter.cpp

public:
   void lowerGETTLSAddrAndEmitMCInsts(const MachineInstr *MI,
                                      const MCSubtargetInfo &STI);
 
   void emitInstruction(const MachineInstr *MI) override;
 
   static const char *getRegisterName(unsigned RegNo) {
     return VEInstPrinter::getRegisterName(RegNo);
   }
+  void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &OS);
+  bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+                       const char *ExtraCode, raw_ostream &O) override;
 };
 } // end of anonymous namespace
 
 static MCOperand createVEMCOperand(VEMCExpr::VariantKind Kind, MCSymbol *Sym,
                                    MCContext &OutContext) {
   const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Sym, OutContext);
   const VEMCExpr *expr = VEMCExpr::create(Kind, MCSym, OutContext);
   return MCOperand::createExpr(expr);
void VEAsmPrinter::emitInstruction(const MachineInstr *MI) {
   MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
   do {
     MCInst TmpInst;
     LowerVEMachineInstrToMCInst(&*I, TmpInst, *this);
     EmitToStreamer(*OutStreamer, TmpInst);
   } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
 }
 
+void VEAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
+                                raw_ostream &O) {
+  const MachineOperand &MO = MI->getOperand(OpNum);
+
+  switch (MO.getType()) {
+  case MachineOperand::MO_Register:
+    O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
+    break;
+  default:
+    llvm_unreachable("<unknown operand type>");
+  }
+}
+
+// PrintAsmOperand - Print out an operand for an inline asm expression.
+bool VEAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+                                   const char *ExtraCode, raw_ostream &O) {
+  if (ExtraCode && ExtraCode[0]) {
+    if (ExtraCode[1] != 0)
+      return true; // Unknown modifier.
+
+    switch (ExtraCode[0]) {
+    default:
+      // See if this is a generic print operand
+      return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
+    case 'r':
+      break;
+    }
+  }
+
+  printOperand(MI, OpNo, O);
+
+  return false;
+}
+
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEAsmPrinter() {
   RegisterAsmPrinter<VEAsmPrinter> X(getTheVETarget());
 }

llvm/lib/Target/VE/VEISelLowering.h

public:
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
   /// Returns true if the target allows unaligned memory accesses of the
   /// specified type.
   bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
                                       MachineMemOperand::Flags Flags,
                                       bool *Fast) const override;
 
+  /// Inline Assembly {
+
+  std::pair<unsigned, const TargetRegisterClass *>
+  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
+                               StringRef Constraint, MVT VT) const override;
+
+  /// } Inline Assembly
+
   /// Target Optimization {
 
   // SX-Aurora VE's s/udiv is 5-9 times slower than multiply.
   bool isIntDivCheap(EVT, AttributeList) const override { return false; }
   // VE doesn't have rem.
   bool hasStandaloneRem(EVT) const override { return false; }
   // VE LDZ instruction returns 64 if the input is zero.
   bool isCheapToSpeculateCtlz() const override { return true; }

llvm/lib/Target/VE/VEISelLowering.cpp

SDValue VETargetLowering::PerformDAGCombine(SDNode *N,
   default:
     break;
   case ISD::TRUNCATE:
     return combineTRUNCATE(N, DCI);
   }
 
   return SDValue();
 }
+
+//===----------------------------------------------------------------------===//
+//                         VE Inline Assembly Support
+//===----------------------------------------------------------------------===//
+
+std::pair<unsigned, const TargetRegisterClass *>
+VETargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
+                                               StringRef Constraint,
+                                               MVT VT) const {
+  const TargetRegisterClass *RC = nullptr;
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
+    default:
+      return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+    case 'r':
+      RC = &VE::I64RegClass;
+      break;
+    }
+    return std::make_pair(0U, RC);
+  }
+
+  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+}

llvm/test/CodeGen/VE/Scalar/inlineasm-lea.ll

+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+define i64 @lea1a(i64 %x) nounwind {
+; CHECK-LABEL: lea1a:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lea %s0, (%s0)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    or %s11, 0, %s9
+  %asmtmp = tail call i64 asm "lea $0, ($1)", "=r,r"(i64 %x) nounwind
+  ret i64 %asmtmp
+}
+
+define i64 @lea1b(i64 %x) nounwind {
+; CHECK-LABEL: lea1b:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lea %s0, (, %s0)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    or %s11, 0, %s9
+  %asmtmp = tail call i64 asm "lea $0, (, $1)", "=r,r"(i64 %x) nounwind
+  ret i64 %asmtmp
+}
+
+define i64 @lea2(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: lea2:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lea %s0, (%s0, %s1)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    or %s11, 0, %s9
+  %asmtmp = tail call i64 asm "lea $0, ($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind
+  ret i64 %asmtmp
+}
+
+define i64 @lea3(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: lea3:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lea %s0, 2048(%s0, %s1)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    or %s11, 0, %s9
+  %asmtmp = tail call i64 asm "lea $0, 2048($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind
+  ret i64 %asmtmp
+}
+
+define i64 @leasl3(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: leasl3:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lea.sl %s0, 2048(%s1, %s0)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    or %s11, 0, %s9
+  %asmtmp = tail call i64 asm "lea.sl $0, 2048($1, $2)", "=r,r,r"(i64 %y, i64 %x) nounwind
+  ret i64 %asmtmp
+}