[IR] [TableGen] Cleanup pass over the IR TableGen files, part 2

[Paul-C-Anagnostopoulos]

Summary

This is the final patch for the IR TableGen files cleanup.

It deals with the intrinsics for NVVM.

[tra]

LGTM overall, modulo one cosmetic nit.

llvm/include/llvm/IR/IntrinsicsNVVM.td

173–181

I'd keep the original version, including the formatting -- I think it's substantially more readable that way. Understanding the uniformly nested set of foldl() is mentally easier to grok than the mix of foldl and foreach with args wrapped differently at each level.

IMO, it's one of the cases where nominally better code is not necessarily an improvement overall.

[Paul-C-Anagnostopoulos]

llvm/include/llvm/IR/IntrinsicsNVVM.td

173–181

Yes, now that you bring up consistency, I think it would be better to keep !foldl.

Why do you like them not indented?

[tra]

llvm/include/llvm/IR/IntrinsicsNVVM.td

173–181

When nested foldl's indented identically, it's easier to see that all of them do roughly the same thing.

Considering that each next foldl is an argument for !listconcat, we'd need to indent way too far to the right to make it useful. Or we'd need to wrap foldl arguments so that each is on its own line. That would make it hard to see the whole class at once.
Indenting just a little makes it hard to tell where exactly the next indentation level belongs, so that's not very goo either.
Not indenting, is not perfect, but I find it the least confusing of the options I tried.

[Paul-C-Anagnostopoulos]

Restored the two !foldl operators discussed above.

llvm/include/llvm/IR/IntrinsicsNVVM.td

class MMA_SIGNATURE<WMMA_REGS A, WMMA_REGS B, WMMA_REGS C, WMMA_REGS D> {
   list<WMMA_REGS> id_frags = !cond(
      // int and sub-int ops are identified by input type.
      !eq(A.ptx_elt_type, "s8") : [A],
      !eq(A.ptx_elt_type, "u8") : [A],
      !eq(A.ptx_elt_type, "s4") : [A],
      !eq(A.ptx_elt_type, "u4") : [A],
      !eq(A.ptx_elt_type, "b1") : [A],
      // the rest are FP ops identified by accumulator & result type.
-     1: [D, C]
+     true: [D, C]
      );
    string ret = !foldl("", id_frags, a, b, !strconcat(a, ".", b.ptx_elt_type));
 }
 
 class WMMA_NAME_MMA<string ALayout, string BLayout, int Satfinite,
                     WMMA_REGS A, WMMA_REGS B, WMMA_REGS C, WMMA_REGS D> {
   string signature = MMA_SIGNATURE<A, B, C, D>.ret;
   string llvm = !if(
list<list<WMMA_REGS>> ret =
      !foldl([]<list<WMMA_REGS>>, TypeA, t2, type_a, !listconcat(t2,
      !foldl([]<list<WMMA_REGS>>, !if(!size(TypeB), TypeB, [type_a]), t3, type_b, !listconcat(t3,
      !foldl([]<list<WMMA_REGS>>, TypeC, t4, type_c, !listconcat(t4,
      !foldl([]<list<WMMA_REGS>>, !if(!size(TypeD), TypeD, [type_c]), t5, type_d, !listconcat(t5,
             [[WMMA_REGS<geom, "a", type_a>,
               WMMA_REGS<geom, "b", type_b>,
               WMMA_REGS<geom, "c", type_c>,
               WMMA_REGS<geom, "d", type_d>]]))))))))));
    // Debugging aid for readable representation of the list above.
    list<list<string>> ops = !foreach(x, ret, [x[0].gft, x[1].gft, x[2].gft, x[3].gft]);
 }
 
 class MMA_LDST_OPS<list<string> Geom, list<string> Frags, list<string> Types> {
   list<WMMA_REGS> ret =
      !foldl([]<WMMA_REGS>, Geom, t1, geom, !listconcat(t1,
      !foldl([]<WMMA_REGS>, Frags, t2, frag, !listconcat(t2,
      !foldl([]<WMMA_REGS>, Types, t3, type, !listconcat(t3,
             [WMMA_REGS<geom, frag, type>]))))));
    // Debugging aid for readable representation of the list above.
    list<string> ops = !foreach(x, ret, x.gft);
 }
 
 
 
 // Creates list of valid combinations of fragments. This is the master list that
!and(!eq(layout_b, "-"), // It's a Load or Store op
              !eq(ld, "u4:b:col"),
              !eq(ldf, "u4:c"),
              !eq(ldf, "u4:d"))) : [1],
     // All other sub-int ops are not supported.
     !eq(t, "b1") : [],
     !eq(t, "s4") : [],
     !eq(t, "u4") : [],
     // All other (non sub-int) are OK.
-    1: [1]
+    true: [1]
   );
 }
 
 class SHFL_INFO<bit sync, string mode, string type, bit return_pred> {
   string Suffix = !if(sync, "sync_", "")
                   # mode # "_"
                   # type
                   # !if(return_pred, "p", "");
 
   string Name = "int_nvvm_shfl_" # Suffix;
   string Builtin = "__nvvm_shfl_" # Suffix;
   string IntrName = "llvm.nvvm.shfl." # !subst("_",".", Suffix);
-  list<int> withGccBuiltin = !if(return_pred, [], [1]);
-  list<int> withoutGccBuiltin = !if(return_pred, [1], []);
+  bit withGccBuiltin = !not(return_pred);
+  bit withoutGccBuiltin = return_pred;
   LLVMType OpType = !cond(
     !eq(type,"i32"): llvm_i32_ty,
     !eq(type,"f32"): llvm_float_ty);
   list<LLVMType> RetTy = !if(return_pred, [OpType, llvm_i1_ty], [OpType]);
   list<LLVMType> ArgsTy = !if(sync,
     [llvm_i32_ty, OpType, llvm_i32_ty, llvm_i32_ty],
     [OpType, llvm_i32_ty, llvm_i32_ty]);
 }

 def int_nvvm_read_ptx_sreg_pm3 : PTXReadNCSRegIntrinsic_r32<"pm3">;
 
 def int_nvvm_read_ptx_sreg_warpsize : PTXReadSRegIntrinsic_r32<"warpsize">;
 
 //
 // SHUFFLE
 //
 // Generate intrinsics for all variants of shfl instruction.
-foreach sync = [0, 1] in {
+foreach sync = [false, true] in {
   foreach mode = ["up", "down", "bfly", "idx"] in {
     foreach type = ["i32", "f32"] in {
-      foreach return_pred = [0, 1] in {
+      foreach return_pred = [false, true] in {
         foreach i = [SHFL_INFO<sync, mode, type, return_pred>] in {
-          foreach _ = i.withGccBuiltin in {
+          if i.withGccBuiltin then {
             def i.Name : GCCBuiltin<i.Builtin>,
                          Intrinsic<i.RetTy, i.ArgsTy,
                                    [IntrInaccessibleMemOnly, IntrConvergent],
                                    i.IntrName>;
           }
-          foreach _ = i.withoutGccBuiltin in {
+          if i.withoutGccBuiltin then {
             def i.Name : Intrinsic<i.RetTy, i.ArgsTy,
                          [IntrInaccessibleMemOnly, IntrConvergent], i.IntrName>;
           }
         }
       }
     }
   }
 }