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Differential D90912

[VE] Add v(m)regs to preserve_all reg mask
ClosedPublic

Authored by simoll on Nov 6 2020, 1:26 AM.

Details

Reviewers
kaz7
k-ishizaka
Commits
rG7914e4f0fa60: [VE] Add v(m)regs to preserve_all reg mask
Summary

V(m)regs where defined before CSR_preserve_all was, add them now.

Diff Detail

Unit TestsFailed

TimeTest
400 mslinux > HWAddressSanitizer-x86_64.TestCases::sizes.cpp

Event Timeline

simoll created this revision.Nov 6 2020, 1:26 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 6 2020, 1:26 AM
Herald added subscribers: llvm-commits, hiraditya. · View Herald Transcript
simoll requested review of this revision.Nov 6 2020, 1:26 AM
Harbormaster completed remote builds in B77842: Diff 303368.Nov 6 2020, 2:16 AM
simoll mentioned this in D90842: [VE] fastcc and vreg-to-vreg copy.Nov 6 2020, 5:29 AM
kaz7 accepted this revision.Nov 6 2020, 6:06 AM
This revision is now accepted and ready to land.Nov 6 2020, 6:06 AM
This revision was landed with ongoing or failed builds.Nov 6 2020, 6:16 AM
Closed by commit rG7914e4f0fa60: [VE] Add v(m)regs to preserve_all reg mask (authored by simoll). · Explain Why
This revision was automatically updated to reflect the committed changes.
simoll added a commit: rG7914e4f0fa60: [VE] Add v(m)regs to preserve_all reg mask.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
4 lines

Diff 303368

llvm/lib/Target/VE/VECallingConv.td

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines CCIfType<[f128],
[SX0, SX1, SX3, SX5]>>, [SX0, SX1, SX3, SX5]>>,
]>; ]>;
// Callee-saved registers // Callee-saved registers
def CSR : CalleeSavedRegs<(add (sequence "SX%u", 18, 33))>; def CSR : CalleeSavedRegs<(add (sequence "SX%u", 18, 33))>;
def CSR_NoRegs : CalleeSavedRegs<(add)>; def CSR_NoRegs : CalleeSavedRegs<(add)>;
// PreserveAll (clobbers s62,s63) - used for ve_grow_stack // PreserveAll (clobbers s62,s63) - used for ve_grow_stack
def CSR_preserve_all : CalleeSavedRegs<(add (sequence "SX%u", 0, 61))>; def CSR_preserve_all : CalleeSavedRegs<(add (sequence "SX%u", 0, 61),
(sequence "V%u", 0, 63),
(sequence "VM%u", 1, 15))>;