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[VE] fastcc and vreg-to-vreg copy
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Authored by simoll on Nov 5 2020, 5:29 AM.

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Summary

This defines a 'fastcc' for the VE target and implements vreg-to-vreg copy for parameter passing. The 'fastcc' extends the standard CC for SX-Aurora with register passing of vector-typed parameters and return values.

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Event Timeline

simoll created this revision.Nov 5 2020, 5:29 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 5 2020, 5:29 AM
simoll requested review of this revision.Nov 5 2020, 5:29 AM
kaz7 added a comment.Nov 5 2020, 1:08 PM

It is better to make a different NFC patch for modifications on the mechanism to retrieve the calling convention. And need a regression test from caller side.

llvm/lib/Target/VE/VEISelLowering.cpp
43

These modifications are independent from passing vector registers on registers patch.

simoll updated this revision to Diff 303414.Nov 6 2020, 5:27 AM
  • Rebased onto commited CC switching patch D90911
  • added call tests
simoll added inline comments.Nov 6 2020, 5:29 AM
llvm/lib/Target/VE/VECallingConv.td
165

I'll commit the CSR_preserve_all change standalone with D90912

simoll updated this revision to Diff 303428.Nov 6 2020, 6:19 AM
simoll retitled this revision from [VE] fastcc with vector register passing to [VE] fastcc with vector register passing.
simoll edited the summary of this revision. (Show Details)
  • Rebased.
  • NFC.
simoll marked an inline comment as done.Nov 6 2020, 6:19 AM
simoll updated this revision to Diff 303473.Nov 6 2020, 8:55 AM
  • Rebasing onto landed D90833 and adapted tests.
kaz7 added a comment.Nov 8 2020, 3:50 PM

Thank you for adding caller side test. However, it is not possible to examine these tests whether fastcc is implemented correctly or not, unfortunately. How about upstream vector load and vector store first, then upstream this with caller side tests something like load and call, and return and store? After that, upstream vector copy with callee side tests.

Here is why the patches are structured this way relying on fastcc:
My actual goal is to put a patch on phabricator that demonstrates the hpce/develop isel mechanism for vector instructions. This should come with single vector instruction tests (one vector inst emitted per test function).

Using fastcc we can write single vector instruction tests that do not require any vld nor vst nor vor, if we order the vector operands in IR to match the vreg order of the CC.
However, to emit any valid vector instruction code in the first place, i need LVLGen upstream (D90850) and to upstream LVLGen we need a test for it. The VOR required for fastcc is such a test and it does not require any isel patterns.

This current patch (D90842) is just a stub for fastcc to make D90850 smaller.

simoll updated this revision to Diff 305146.Nov 13 2020, 7:57 AM
simoll retitled this revision from [VE] fastcc with vector register passing to [VE] fastcc and vreg-to-vreg copy.
simoll edited the summary of this revision. (Show Details)

Merged into one fastcc vreg-to-vreg patch

kaz7 added a comment.Nov 13 2020, 1:25 PM

Why is there no caller_varg_pass_v0 or caller_varg_pass_v0_and_v1 tests?

Why is there no caller_varg_pass_v0 or caller_varg_pass_v0_and_v1 tests?

fastcc does not support vargs. Citing the LLVM LangRef :

“fastcc” - The fast calling convention
[..]
This calling convention does not support varargs and requires the prototype of all callees to exactly match the prototype of the function definition.

kaz7 added a comment.Nov 16 2020, 2:46 AM

I don't say varargs. I meant vector arguments. This patch define fastcc and declare how to pass vector arguments and vector return values using vector registers. Why don't you make tests to check function calls using vector registers correctly? Your tests don't show %v0 or %v1 in checking assembly code, so it is not possible to check the correctness, IMO.

simoll updated this revision to Diff 305479.Nov 16 2020, 5:17 AM
simoll edited the summary of this revision. (Show Details)
  • added vector param tests that trigger explicit vreg copies.
kaz7 accepted this revision.Nov 16 2020, 6:19 AM

Thank you for adding acceptable tests. LGTM.

This revision is now accepted and ready to land.Nov 16 2020, 6:19 AM
This revision was landed with ongoing or failed builds.Nov 16 2020, 7:24 AM
This revision was automatically updated to reflect the committed changes.