[VE] Add isReMaterializable and isAsCheapAsAMove flags

[kaz7]

Summary

Add isReMaterializable and isCheapAsAMove flags to integer instructions
which cost cheap.

llvm/lib/Target/VE/VEInstrInfo.td

multiclass RMm<string opcStr, bits<8>opc, RegisterClass RC> {
   def zri : RM<opc, (outs RC:$dest), (ins MEMzri:$addr),
                !strconcat(opcStr, " $dest, $addr"), []>;
   let cy = 0, cz = 0 in
   def zii : RM<opc, (outs RC:$dest), (ins MEMzii:$addr),
                !strconcat(opcStr, " $dest, $addr"), []>;
 }
 
 // Section 8.2.1 - LEA
-let cx = 0, DecoderMethod = "DecodeLoadI64" in
-defm LEA : RMm<"lea", 0x06, I64>;
-let cx = 1, DecoderMethod = "DecodeLoadI64" in
-defm LEASL : RMm<"lea.sl", 0x06, I64>;
+let isReMaterializable = 1, isAsCheapAsAMove = 1,
+    DecoderMethod = "DecodeLoadI64" in {
+  let cx = 0 in defm LEA : RMm<"lea", 0x06, I64>;
+  let cx = 1 in defm LEASL : RMm<"lea.sl", 0x06, I64>;
+}
 
 def : Pat<(iPTR ADDRrri:$addr), (LEArri MEMrri:$addr)>;
 def : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>;
 def : Pat<(add I64:$base, simm32:$disp), (LEArii $base, 0, (LO32 $disp))>;
 def : Pat<(add I64:$base, lozero:$disp), (LEASLrii $base, 0, (HI32 $disp))>;
 
 def lea_add : PatFrags<(ops node:$base, node:$idx, node:$disp),
                        [(add (add node:$base, node:$idx), node:$disp),

 // Section 8.3.2 - SVOB (Set Vector Out-of-order memory access Boundary)
 let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1 in
 def SVOB : RR<0x30, (outs), (ins), "svob">;
 
 //-----------------------------------------------------------------------------
 // Section 8.4 - Fixed-point Operation Instructions
 //-----------------------------------------------------------------------------
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+
 // Section 8.4.1 - ADD (Add)
 defm ADDUL : RRm<"addu.l", 0x48, I64, i64>;
 let cx = 1 in defm ADDUW : RRm<"addu.w", 0x48, I32, i32>;
 
 // Section 8.4.2 - ADS (Add Single)
 defm ADDSWSX : RRm<"adds.w.sx", 0x4A, I32, i32, add>;
 let cx = 1 in defm ADDSWZX : RRm<"adds.w.zx", 0x4A, I32, i32>;
 
 // Section 8.4.3 - ADX (Add)
 defm ADDSL : RRm<"adds.l", 0x59, I64, i64, add>;
 
 // Section 8.4.4 - SUB (Subtract)
 defm SUBUL : RRNCm<"subu.l", 0x58, I64, i64>;
 let cx = 1 in defm SUBUW : RRNCm<"subu.w", 0x58, I32, i32>;
 
 // Section 8.4.5 - SBS (Subtract Single)
 defm SUBSWSX : RRNCm<"subs.w.sx", 0x5A, I32, i32, sub>;
 let cx = 1 in defm SUBSWZX : RRNCm<"subs.w.zx", 0x5A, I32, i32>;
 
 // Section 8.4.6 - SBX (Subtract)
 defm SUBSL : RRNCm<"subs.l", 0x5B, I64, i64, sub>;
 
+} // isReMaterializable, isAsCheapAsAMove
+
 // Section 8.4.7 - MPY (Multiply)
 defm MULUL : RRm<"mulu.l", 0x49, I64, i64>;
 let cx = 1 in defm MULUW : RRm<"mulu.w", 0x49, I32, i32>;
 
 // Section 8.4.8 - MPS (Multiply Single)
 defm MULSWSX : RRm<"muls.w.sx", 0x4B, I32, i32, mul>;
 let cx = 1 in defm MULSWZX : RRm<"muls.w.zx", 0x4B, I32, i32>;
 

 
 // Section 8.4.12 - DVS (Divide Single)
 defm DIVSWSX : RRNCm<"divs.w.sx", 0x7B, I32, i32, sdiv>;
 let cx = 1 in defm DIVSWZX : RRNCm<"divs.w.zx", 0x7B, I32, i32>;
 
 // Section 8.4.13 - DVX (Divide)
 defm DIVSL : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>;
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+
 // Section 8.4.14 - CMP (Compare)
 defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64>;
 let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32>;
 
 // Section 8.4.15 - CPS (Compare Single)
 defm CMPSWSX : RRNCm<"cmps.w.sx", 0x7A, I32, i32>;
 let cx = 1 in defm CMPSWZX : RRNCm<"cmps.w.zx", 0x7A, I32, i32>;
 
 // Section 8.4.16 - CPX (Compare)
 defm CMPSL : RRNCm<"cmps.l", 0x6A, I64, i64>;
 
 // Section 8.4.17 - CMS (Compare and Select Maximum/Minimum Single)
 // cx: sx/zx, cw: max/min
 defm MAXSWSX : RRm<"maxs.w.sx", 0x78, I32, i32>;
 let cx = 1 in defm MAXSWZX : RRm<"maxs.w.zx", 0x78, I32, i32>;
 let cw = 1 in defm MINSWSX : RRm<"mins.w.sx", 0x78, I32, i32>;
 let cx = 1, cw = 1 in defm MINSWZX : RRm<"mins.w.zx", 0x78, I32, i32>;
 
 // Section 8.4.18 - CMX (Compare and Select Maximum/Minimum)
 defm MAXSL : RRm<"maxs.l", 0x68, I64, i64>;
 let cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64>;
 
+} // isReMaterializable, isAsCheapAsAMove
+
 //-----------------------------------------------------------------------------
 // Section 8.5 - Logical Operation Instructions
 //-----------------------------------------------------------------------------
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+
 // Section 8.5.1 - AND (AND)
 defm AND : RRm<"and", 0x44, I64, i64, and>;
 
 // Section 8.5.2 - OR (OR)
 defm OR : RRm<"or", 0x45, I64, i64, or>;
 
 // Section 8.5.3 - XOR (Exclusive OR)
 defm XOR : RRm<"xor", 0x46, I64, i64, xor>;
 
 // Section 8.5.4 - EQV (Equivalence)
 defm EQV : RRm<"eqv", 0x47, I64, i64>;
 
+} // isReMaterializable, isAsCheapAsAMove
+
 // Section 8.5.5 - NND (Negate AND)
 def and_not : PatFrags<(ops node:$x, node:$y),
                        [(and (not node:$x), node:$y)]>;
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm NND : RRNCm<"nnd", 0x54, I64, i64, and_not>;
 
 // Section 8.5.6 - MRG (Merge)
 defm MRG : RRMRGm<"mrg", 0x56, I64, i64>;
 
 // Section 8.5.7 - LDZ (Leading Zero Count)
 def ctlz_pat : PatFrags<(ops node:$src),
                         [(ctlz node:$src),
                          (ctlz_zero_undef node:$src)]>;
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm LDZ : RRI1m<"ldz", 0x67, I64, i64, ctlz_pat>;
 
 // Section 8.5.8 - PCNT (Population Count)
 defm PCNT : RRI1m<"pcnt", 0x38, I64, i64, ctpop>;
 
 // Section 8.5.9 - BRV (Bit Reverse)
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm BRV : RRI1m<"brv", 0x39, I64, i64, bitreverse>;
 
 // Section 8.5.10 - BSWP (Byte Swap)
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm BSWP : RRSWPm<"bswp", 0x2B, I64, i64>;
+
 def : Pat<(i64 (bswap i64:$src)),
           (BSWPri $src, 0)>;
 def : Pat<(i64 (bswap (i64 mimm:$src))),
           (BSWPmi (MIMM $src), 0)>;
 def : Pat<(i32 (bswap i32:$src)),
           (EXTRACT_SUBREG
               (BSWPri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub_i32), 1),
               sub_i32)>;

 def : MnemonicAlias<"cmov.d", "cmov.d.at">;
 def : MnemonicAlias<"cmov.s", "cmov.s.at">;
 
 //-----------------------------------------------------------------------------
 // Section 8.6 - Shift Operation Instructions
 //-----------------------------------------------------------------------------
 
 // Section 8.6.1 - SLL (Shift Left Logical)
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;
 
 // Section 8.6.2 - SLD (Shift Left Double)
 defm SLD : RRILDm<"sld", 0x64, I64, i64>;
 
 // Section 8.6.3 - SRL (Shift Right Logical)
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;
 
 // Section 8.6.4 - SRD (Shift Right Double)
 defm SRD : RRIRDm<"srd", 0x74, I64, i64>;
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+
 // Section 8.6.5 - SLA (Shift Left Arithmetic)
 defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;
 let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>;
 
 // Section 8.6.6 - SLAX (Shift Left Arithmetic)
 defm SLAL : RRIm<"sla.l", 0x57, I64, i64>;
 
 // Section 8.6.7 - SRA (Shift Right Arithmetic)
 defm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>;
 let cx = 1 in defm SRAWZX : RRIm<"sra.w.zx", 0x76, I32, i32>;
 
 // Section 8.6.8 - SRAX (Shift Right Arithmetic)
 defm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>;
 
+} // isReMaterializable, isAsCheapAsAMove
+
 def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))),
           (EXTRACT_SUBREG (SRLri (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
             $src, sub_i32), !add(32, 64)), imm:$val), sub_i32)>;
 def : Pat<(i32 (srl i32:$src, i32:$val)),
           (EXTRACT_SUBREG (SRLrr (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
             $src, sub_i32), !add(32, 64)), $val), sub_i32)>;
 
 //-----------------------------------------------------------------------------

llvm/test/CodeGen/VE/Scalar/br_cc.ll

 }
 
 ; Function Attrs: nounwind
 define void @br_cc_i128_imm(i128 %0) {
 ; CHECK-LABEL: br_cc_i128_imm:
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s2
-; CHECK-NEXT:    or %s3, 0, %s2
+; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
 ; CHECK-NEXT:    or %s4, 63, (0)1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
 ; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
 ; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP

 }
 
 ; Function Attrs: nounwind
 define void @br_cc_u128_imm(i128 %0) {
 ; CHECK-LABEL: br_cc_u128_imm:
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s2
-; CHECK-NEXT:    or %s3, 0, %s2
+; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
 ; CHECK-NEXT:    or %s4, 63, (0)1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
 ; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
 ; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
4:                                                ; preds = %3, %1
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @br_cc_imm_i128(i128 %0) {
 ; CHECK-LABEL: br_cc_imm_i128:
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, -1, (0)1
-; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s2
-; CHECK-NEXT:    or %s2, 0, %s3
-; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s1
+; CHECK-NEXT:    or %s2, 0, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s1
 ; CHECK-NEXT:    or %s4, -64, (0)1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
-; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s2, %s3, %s1
-; CHECK-NEXT:    brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s0
+; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = icmp sgt i128 %0, -65
   br i1 %2, label %3, label %4
 
 3:                                                ; preds = %1
   tail call void asm sideeffect "nop", ""()
   br label %4
 
 4:                                                ; preds = %3, %1
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @br_cc_imm_u128(i128 %0) {
 ; CHECK-LABEL: br_cc_imm_u128:
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:    or %s2, -1, (0)1
-; CHECK-NEXT:    or %s3, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s2
-; CHECK-NEXT:    or %s2, 0, %s3
-; CHECK-NEXT:    cmov.l.ne %s2, (63)0, %s1
+; CHECK-NEXT:    or %s2, 0, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
 ; CHECK-NEXT:    or %s4, -64, (0)1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s4
-; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s2, %s3, %s1
-; CHECK-NEXT:    brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s0
+; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT:    brne.w 0, %s3, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = icmp ugt i128 %0, -65
   br i1 %2, label %3, label %4

llvm/test/CodeGen/VE/Scalar/call.ll

 }
 
 define i32 @stack_call_int_szext() {
 ; CHECK-LABEL: stack_call_int_szext:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s0, -1, (0)1
 ; CHECK-NEXT:    st %s0, 248(, %s11)
 ; CHECK-NEXT:    lea %s34, 65535
-; CHECK-NEXT:    lea %s1, stack_callee_int_szext@lo
-; CHECK-NEXT:    and %s1, %s1, (32)0
-; CHECK-NEXT:    lea.sl %s12, stack_callee_int_szext@hi(, %s1)
+; CHECK-NEXT:    lea %s0, stack_callee_int_szext@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, stack_callee_int_szext@hi(, %s0)
+; CHECK-NEXT:    or %s0, -1, (0)1
 ; CHECK-NEXT:    lea %s1, 255
 ; CHECK-NEXT:    or %s2, 3, (0)1
 ; CHECK-NEXT:    or %s3, 4, (0)1
 ; CHECK-NEXT:    or %s4, 5, (0)1
 ; CHECK-NEXT:    or %s5, 6, (0)1
 ; CHECK-NEXT:    or %s6, 7, (0)1
 ; CHECK-NEXT:    or %s7, 8, (0)1
 ; CHECK-NEXT:    st %s34, 240(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i32 @stack_callee_int_szext(i1 -1, i8 -1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i16 -1, i8 -1)
   ret i32 %r
 }
 
 define float @stack_call_float() {
 ; CHECK-LABEL: stack_call_float:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea.sl %s0, 1092616192
 ; CHECK-NEXT:    st %s0, 248(, %s11)
 ; CHECK-NEXT:    lea.sl %s34, 1091567616
+; CHECK-NEXT:    lea %s0, stack_callee_float@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, stack_callee_float@hi(, %s0)
 ; CHECK-NEXT:    lea.sl %s0, 1065353216
 ; CHECK-NEXT:    lea.sl %s1, 1073741824
 ; CHECK-NEXT:    lea.sl %s2, 1077936128
 ; CHECK-NEXT:    lea.sl %s3, 1082130432
 ; CHECK-NEXT:    lea.sl %s4, 1084227584
 ; CHECK-NEXT:    lea.sl %s5, 1086324736
 ; CHECK-NEXT:    lea.sl %s6, 1088421888
 ; CHECK-NEXT:    lea.sl %s7, 1090519040
-; CHECK-NEXT:    lea %s35, stack_callee_float@lo
-; CHECK-NEXT:    and %s35, %s35, (32)0
-; CHECK-NEXT:    lea.sl %s12, stack_callee_float@hi(, %s35)
 ; CHECK-NEXT:    st %s34, 240(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call float @stack_callee_float(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0)
   ret float %r
 }
 
 define float @stack_call_float2(float %p0) {

 ; CHECK-NEXT:    or %s5, 0, %s0
 ; CHECK-NEXT:    or %s6, 0, %s0
 ; CHECK-NEXT:    or %s7, 0, %s0
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call float @stack_callee_float(float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0)
   ret float %r
 }
-

llvm/test/CodeGen/VE/Scalar/ctlz.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 declare i128 @llvm.ctlz.i128(i128, i1)
 declare i64 @llvm.ctlz.i64(i64, i1)
 declare i32 @llvm.ctlz.i32(i32, i1)
 declare i16 @llvm.ctlz.i16(i16, i1)
 declare i8 @llvm.ctlz.i8(i8, i1)
 
 define i128 @func128(i128 %p){
 ; CHECK-LABEL: func128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s3, %s1, %s2
+; CHECK-NEXT:    cmps.l %s2, %s1, %s2
 ; CHECK-NEXT:    ldz %s1, %s1
 ; CHECK-NEXT:    ldz %s0, %s0
 ; CHECK-NEXT:    lea %s0, 64(, %s0)
-; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s3
-; CHECK-NEXT:    or %s1, 0, %s2
+; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s2
+; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true)
   ret i128 %r
 }
 
 define i64 @func64(i64 %p) {
 ; CHECK-LABEL: func64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true)
   ret i8 %r
 }
 
 define i128 @func128x(i128 %p){
 ; CHECK-LABEL: func128x:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s3, %s1, %s2
+; CHECK-NEXT:    cmps.l %s2, %s1, %s2
 ; CHECK-NEXT:    ldz %s1, %s1
 ; CHECK-NEXT:    ldz %s0, %s0
 ; CHECK-NEXT:    lea %s0, 64(, %s0)
-; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s3
-; CHECK-NEXT:    or %s1, 0, %s2
+; CHECK-NEXT:    cmov.l.ne %s0, %s1, %s2
+; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false)
   ret i128 %r
 }
 
 define i64 @func64x(i64 %p) {
 ; CHECK-LABEL: func64x:
 ; CHECK:       .LBB{{[0-9]+}}_2:

llvm/test/CodeGen/VE/Scalar/cttz.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 declare i128 @llvm.cttz.i128(i128, i1)
 declare i64 @llvm.cttz.i64(i64, i1)
 declare i32 @llvm.cttz.i32(i32, i1)
 declare i16 @llvm.cttz.i16(i16, i1)
 declare i8 @llvm.cttz.i8(i8, i1)
 
 define i128 @func128(i128 %p) {
 ; CHECK-LABEL: func128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s3, %s0, %s2
-; CHECK-NEXT:    lea %s4, -1(, %s0)
-; CHECK-NEXT:    nnd %s0, %s0, %s4
-; CHECK-NEXT:    pcnt %s4, %s0
+; CHECK-NEXT:    cmps.l %s2, %s0, %s2
+; CHECK-NEXT:    lea %s3, -1(, %s0)
+; CHECK-NEXT:    nnd %s0, %s0, %s3
+; CHECK-NEXT:    pcnt %s3, %s0
 ; CHECK-NEXT:    lea %s0, -1(, %s1)
 ; CHECK-NEXT:    nnd %s0, %s1, %s0
 ; CHECK-NEXT:    pcnt %s0, %s0
 ; CHECK-NEXT:    lea %s0, 64(, %s0)
-; CHECK-NEXT:    cmov.l.ne %s0, %s4, %s3
-; CHECK-NEXT:    or %s1, 0, %s2
+; CHECK-NEXT:    cmov.l.ne %s0, %s3, %s2
+; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true)
   ret i128 %r
 }
 
 define i64 @func64(i64 %p) {
 ; CHECK-LABEL: func64:
 ; CHECK:       .LBB{{[0-9]+}}_2:

llvm/test/CodeGen/VE/Scalar/fp_frem.ll

; CHECK-NEXT:    or %s11, 0, %s9
   ret fp128 %3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @frem_float_zero(float %0) {
 ; CHECK-LABEL: frem_float_zero:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
+; CHECK-NEXT:    lea %s0, fmodf@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s0)
 ; CHECK-NEXT:    lea.sl %s0, 0
-; CHECK-NEXT:    lea %s2, fmodf@lo
-; CHECK-NEXT:    and %s2, %s2, (32)0
-; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s2)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = frem float 0.000000e+00, %0
   ret float %2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @frem_double_zero(double %0) {
; CHECK-NEXT:    or %s11, 0, %s9
   ret fp128 %2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @frem_float_cont(float %0) {
 ; CHECK-LABEL: frem_float_cont:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s1, 0, %s0
+; CHECK-NEXT:    lea %s0, fmodf@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s0)
 ; CHECK-NEXT:    lea.sl %s0, -1073741824
-; CHECK-NEXT:    lea %s2, fmodf@lo
-; CHECK-NEXT:    and %s2, %s2, (32)0
-; CHECK-NEXT:    lea.sl %s12, fmodf@hi(, %s2)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = frem float -2.000000e+00, %0
   ret float %2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @frem_double_cont(double %0) {

llvm/test/CodeGen/VE/Scalar/selectccf32c.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i64 %0, %1
   %6 = select i1 %5, float %2, float %3
   ret float %6
 }
 
 define float @selectccsgti128(i128, i128, float, float) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
-; CHECK-NEXT:    or %s3, 0, %s6
-; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    or %s6, 0, (0)1
+; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
+; CHECK-NEXT:    cmov.l.eq %s6, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s6, %s3
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i128 %0, %1
   %6 = select i1 %5, float %2, float %3
   ret float %6
 }
 

 ; CHECK-NEXT:    fcmp.d %s0, %s0, %s1
 ; CHECK-NEXT:    cmov.d.gt %s3, %s2, %s0
 ; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = fcmp ogt double %0, %1
   %6 = select i1 %5, float %2, float %3
   ret float %6
 }
-

llvm/test/CodeGen/VE/Scalar/selectccf64c.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i64 %0, %1
   %6 = select i1 %5, double %2, double %3
   ret double %6
 }
 
 define double @selectccsgti128(i128, i128, double, double) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
-; CHECK-NEXT:    or %s3, 0, %s6
-; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    or %s6, 0, (0)1
+; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
+; CHECK-NEXT:    cmov.l.eq %s6, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s6, %s3
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i128 %0, %1
   %6 = select i1 %5, double %2, double %3
   ret double %6
 }
 

 ; CHECK-NEXT:    fcmp.d %s0, %s0, %s1
 ; CHECK-NEXT:    cmov.d.gt %s3, %s2, %s0
 ; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = fcmp ogt double %0, %1
   %6 = select i1 %5, double %2, double %3
   ret double %6
 }
-

llvm/test/CodeGen/VE/Scalar/selectcci32c.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i64 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsgti128(i128, i128, i32, i32) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
-; CHECK-NEXT:    or %s3, 0, %s6
-; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    or %s6, 0, (0)1
+; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
+; CHECK-NEXT:    cmov.l.eq %s6, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s6, %s3
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i128 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 

 ; CHECK-NEXT:    fcmp.d %s0, %s0, %s1
 ; CHECK-NEXT:    cmov.d.gt %s3, %s2, %s0
 ; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = fcmp ogt double %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
-

llvm/test/CodeGen/VE/Scalar/selectcci64c.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i64 %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
 
 define i64 @selectccsgti128(i128, i128, i64, i64) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
-; CHECK-NEXT:    or %s3, 0, %s6
-; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    or %s6, 0, (0)1
+; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    or %s2, 0, %s6
+; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s6
+; CHECK-NEXT:    cmov.l.eq %s6, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s6, %s3
 ; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
 ; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i128 %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
 

 ; CHECK-NEXT:    fcmp.d %s0, %s0, %s1
 ; CHECK-NEXT:    cmov.d.gt %s3, %s2, %s0
 ; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = fcmp ogt double %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
-

llvm/test/CodeGen/VE/Scalar/va_caller.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 declare i32 @func(i32, ...)
 
 define i32 @caller() {
 ; CHECK-LABEL: caller:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    st %s18, 48(, %s9) # 8-byte Folded Spill
-; CHECK-NEXT:    or %s18, 0, (0)1
-; CHECK-NEXT:    st %s18, 264(, %s11)
-; CHECK-NEXT:    or %s0, 10, (0)1
-; CHECK-NEXT:    st %s0, 256(, %s11)
-; CHECK-NEXT:    lea.sl %s0, 1075970048
-; CHECK-NEXT:    st %s0, 248(, %s11)
-; CHECK-NEXT:    or %s0, 8, (0)1
-; CHECK-NEXT:    st %s0, 240(, %s11)
-; CHECK-NEXT:    st %s18, 232(, %s11)
-; CHECK-NEXT:    or %s5, 5, (0)1
-; CHECK-NEXT:    st %s5, 216(, %s11)
-; CHECK-NEXT:    or %s4, 4, (0)1
-; CHECK-NEXT:    st %s4, 208(, %s11)
-; CHECK-NEXT:    or %s3, 3, (0)1
-; CHECK-NEXT:    st %s3, 200(, %s11)
-; CHECK-NEXT:    or %s2, 2, (0)1
-; CHECK-NEXT:    st %s2, 192(, %s11)
+; CHECK-NEXT:    or %s0, 0, (0)1
+; CHECK-NEXT:    st %s0, 264(, %s11)
+; CHECK-NEXT:    or %s1, 10, (0)1
+; CHECK-NEXT:    st %s1, 256(, %s11)
+; CHECK-NEXT:    lea.sl %s1, 1075970048
+; CHECK-NEXT:    st %s1, 248(, %s11)
+; CHECK-NEXT:    or %s1, 8, (0)1
+; CHECK-NEXT:    st %s1, 240(, %s11)
+; CHECK-NEXT:    st %s0, 232(, %s11)
+; CHECK-NEXT:    or %s1, 5, (0)1
+; CHECK-NEXT:    st %s1, 216(, %s11)
+; CHECK-NEXT:    or %s1, 4, (0)1
+; CHECK-NEXT:    st %s1, 208(, %s11)
+; CHECK-NEXT:    or %s1, 3, (0)1
+; CHECK-NEXT:    st %s1, 200(, %s11)
+; CHECK-NEXT:    or %s1, 2, (0)1
+; CHECK-NEXT:    st %s1, 192(, %s11)
 ; CHECK-NEXT:    or %s1, 1, (0)1
 ; CHECK-NEXT:    st %s1, 184(, %s11)
-; CHECK-NEXT:    lea %s0, .LCPI{{[0-9]+}}_0@lo
-; CHECK-NEXT:    and %s0, %s0, (32)0
-; CHECK-NEXT:    lea.sl %s0, .LCPI{{[0-9]+}}_0@hi(, %s0)
-; CHECK-NEXT:    ld %s34, 8(, %s0)
-; CHECK-NEXT:    ld %s35, (, %s0)
-; CHECK-NEXT:    st %s18, 176(, %s11)
-; CHECK-NEXT:    lea.sl %s6, 1086324736
-; CHECK-NEXT:    st %s6, 224(, %s11)
+; CHECK-NEXT:    lea %s1, .LCPI{{[0-9]+}}_0@lo
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
+; CHECK-NEXT:    ld %s34, 8(, %s1)
+; CHECK-NEXT:    ld %s35, (, %s1)
+; CHECK-NEXT:    st %s0, 176(, %s11)
+; CHECK-NEXT:    lea.sl %s0, 1086324736
+; CHECK-NEXT:    st %s0, 224(, %s11)
 ; CHECK-NEXT:    st %s34, 280(, %s11)
 ; CHECK-NEXT:    lea %s0, func@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, func@hi(, %s0)
+; CHECK-NEXT:    or %s0, 0, (0)1
+; CHECK-NEXT:    or %s1, 1, (0)1
+; CHECK-NEXT:    or %s2, 2, (0)1
+; CHECK-NEXT:    or %s3, 3, (0)1
+; CHECK-NEXT:    or %s4, 4, (0)1
+; CHECK-NEXT:    or %s5, 5, (0)1
+; CHECK-NEXT:    lea.sl %s6, 1086324736
+; CHECK-NEXT:    or %s7, 0, (0)1
 ; CHECK-NEXT:    st %s35, 272(, %s11)
-; CHECK-NEXT:    or %s0, 0, %s18
-; CHECK-NEXT:    or %s7, 0, %s18
 ; CHECK-NEXT:    bsic %s10, (, %s12)
-; CHECK-NEXT:    or %s0, 0, %s18
-; CHECK-NEXT:    ld %s18, 48(, %s9) # 8-byte Folded Reload
+; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   call i32 (i32, ...) @func(i32 0, i16 1, i8 2, i32 3, i16 4, i8 5, float 6.0, i8* null, i64 8, double 9.0, i128 10, fp128 0xLA000000000000000)
   ret i32 0
 }